SU1339558A1 - Program control device - Google Patents

Abstract

The invention relates to computing and can be used to build control and automatic machines for processing discrete information. The purpose of the invention is to reduce hardware costs by conserving the memory capacity of the machine by applying the principle of double encoding. The device contains a generator, a counter, a decoder chip, two registers, two triggers, a delay element, an And element, two groups of memory blocks, two groups of switches, a group of key elements, a group of multiplexers and a group of decoders. The goal is achieved using the specified combination of features. 2 Il.

Description

113

The invention relates to computing and can be used to build control automata and automata for processing discrete information.

The purpose of the invention is to save equipment.

FIG. 1 and 2 shows the functional diagram of the device.

The software control unit contains a generator of 1 pulses, counters 2, a second de-digitizer 3, a first decoder 4, a memory block 5, a second group of blocks ... 5 "memory, a group of elements And 6 ,,, 6, first trigger 7, element And 8, reset input 9, group of information inputs 10 ... 10r.o. 10c, address 11 register, output register 12, first switch group 13, ... 13 c, delay element 14, device start 15 input, fourth group of inputs 16 ... 16j logical conditions, first group of inputs 17, .. 17 logical conditions , mode control input 18, output 19 of the end of operation attribute, group of multiplexers 20 (... 20f, decoder group 21., 21 a, second group of information outputs 22i ... 22p, first group of information outputs 23 ,. ..23a, third group of inputs 24 (.... 24; for logical conditions, the second group of switches 25, .. „25, fourth decoder 26, second group at inputs 27 .. „27 Logical conditions, the third decoder 28, the first group of blocks 29" .. 29 memory, the first 30 and second 31 inputs of the recording resolution, the second trigger 32.

The device works as follows.

The value of the signal at input 18 of the device determines its mode of operation. In the recording mode, the outputs of the multiplexers 20 are in a state of high output impedance (i.e. disconnected), the elements of AND 6 are open and, together with the switches 13, switch to the inputs of the register 11 of the address of the group of inputs 16 and 17 of the device. The switches 25 in the recording mode commute to the inputs of the decoder 26 a group of inputs 27 of the device. The decoder 26 in any mode, in accordance with the arrival of 1m to its inputs, the code allows operation of only one memory block from group 5 and one from group 29. The outputs of memory blocks that are not allowed to operate at that moment are 0

five

0

five

-SS2

Research Institute of high impedance (third state).

Before starting work, it is necessary to record information about the operation of the control device in the memory bins 5, and in the memory blocks 29, coded designations of sets of input variables analyzed in each state of the device. First, constants are written to the memory blocks 29, which serve to address the blocks

5 memory when recording information in them

06 Algorithm operation of the control device. The number of these constants depends on the size of one block of 5 memory.

Suppose, for example, that the address address bit of one memory block 5 is equal to (F-L), then the numbers from 0 to (2, 1) are sequentially recorded in memory block 29. For this, the device is set to the write mode by the logical zero signal from the input 18, and the signal from the device input 30 sets the recording blocks 29 to the recording mode. A code is established at the inputs of the device, according to which the operation of one of the memory blocks 29 is permitted. The operation mode of memory blocks 5 is indifferent at this stage. The logic zero signal from the device input 15 prohibits the passage of pulses from generator 1 through the AND 8 element to counter 2, and the signal from device 9 input resets triggers 7 and 32, counter 2 and register 12. Then, at inputs 15 and 9 devices are set to logical unit signals. In this case, the pulses from the generator 1 through the element 8 are fed to the input of the counter 2, from the outputs of which in the parallel code the number of counted pulses is fed to the decoder 3. As a result, a pulse arrives at the input of register 11, by which the address specified on inputs 16 and 17 is written to it, the address is decrypted by decoder 28 and a cell is selected in memory blocks 29, after which a trigger 32 is triggered by a signal from decoder 3 The memory 29 receives the access signal and information from the input buses of the device 10, .. The legal value (a number from 0 to 2-1) is recorded in the previously selected cell of that memory block 29, the code of which is set at the inputs 27 of the device. The signal from the decoder 3 then sets the trigger 32 to its original state, which prohibits accessing the memory blocks 29, and also signals on output 19 that it is necessary to set new information and a new address. In this case, through the delay element 14, the counter 2 is reset to its initial state. The process is repeated until all numbers from O to (2 -1) are written to the memory block.

Then, a new number of the selected memory block 29 is input to the inputs 27, and the same information is recorded in it. The address matching process ends after the address is written - 15 which translates memory blocks 5 into

formations in all memory blocks 29.

Then, information about the operation of the control device is written to the memory blocks 5. For this, the signal from input 30 sets the memory blocks 29 to read mode, and the signal from input 31 sets the memory blocks 5 to write mode. Then a process similar to writing information into memory blocks 29 occurs.

The decoder 26, in accordance with the code on the inputs 27 of the device, selects one of the memory blocks 29 for reading information and one of the memory blocks 5 for writing. The generator 1, the counter 2, the decoder 3 and the triggers 7 and 32 control the writing of the address to the register 11, reading the number from the memory block 29 and writing information from the buses of the device 10, ..., Um to the memory block 5. On a signal from the decoder 3, the register 11 records the address from the inputs 16 and 17 of the device, which is decoded by the decoder 28 and selects a memory in block 29; from which the number is read. At that, L most significant bits of the address are sent to the group of inputs of the decoder 4, Then, the trigger 32 is triggered by the signal of the decoder 3, and the address signal is sent to the memory blocks 29. In this case, from memory 29, the number from O to () is read, representing the lower digits of the cell address in memory block 5, which are fed to the second group of inputs of the decoder 4. The latter decrypts the address and selects the cell in memory block 5. Trigger 7 is triggered by the signal from the decoder 3, as a result of which the memory and memory blocks 5 are sent to the selected one. cell of memory block 5 is recorded information20

thirty

35

readout, and the signal from input 30 switches the memory blocks 29 to the write mode. Thereafter, coded denoted sets of input variables are analyzed in memory blocks 29, which are analyzed in each a-th state of the control device. The writing process is similar to the above writing of the address constants in the memory blocks 29 and the pack

25 is equal to generator 1, counter 2, decoders 3, 26 and 28, trigger 32. After the recording is finished, memory blocks 2 are switched to read mode by a signal from input 30, and the signal of a logical unit to input 18 of the device switches it to read mode.

In this case, switches 13 and 25 commute the outputs of register 12, the key elements of And 6 are disconnected from the trunk, and the outputs of multiplexers 20 are connected to a group of inputs of register 11, then a pulse signal of a logical zero is fed to input 9 of the device, direct counter 2, triggers 7 and 32 and register 12 in the initial state.

The process of reading information from memory blocks 5 and 29 is similar to the process of writing the operation of the device into memory blocks 5 and is controlled by generator 1, counter 2, decoders 3, 4, 26 and 28, triggers 7 32. of the memory blocks 29 are determined by a set of signals on the third and fourth groups of outputs of the register 12 and the corresponding inputs of 24 devices which switch in this state to the input of the register 11, the read addresses from the memory blocks 5 are determined by the set of signals on the third and fourth groups in moves the register 12 and the appropriate number (dial number) read from the unit

40

45

50

Qi with tire 10 ,,., those triggers 7 and

10c device. Za- 32, and all after them

counter 2 is reset, a new information is set up on buses 10 and a new address on inputs 16 and 17, and the process is repeated. This happens until the selected memory block 5 is filled, after which a new code is applied to the inputs 27, electing a new pair of memory blocks 5 and 29, and the process is repeated. It ends when the information about the operation algorithm of the control device is entered into all blocks 5 of the memory;

Then from input 31 comes a signal.

0

five

readout, and the signal from input 30 switches memory blocks 29 to write mode. Thereafter, coded designations of sets of input variables are analyzed in memory blocks 29, which are analyzed in each a -th state of the control device. The writing process is similar to the above-described writing of address constants in memory blocks 29 and the pack 5 is equal to generator 1, counter 2, decoders 3, 26 and 28, trigger 32. After the recording is finished, memory blocks 29 are switched to read mode by a signal from input 30, and the signal of the logical unit, which enters the input 18 of the device, puts it into read mode.

At that, switches 13 and 25 switch the outputs of register 12, key elements of AND 6 are disconnected from the trunk, and the outputs of multiplexers 20 are connected to a group of inputs of register 11, then a logical zero pulse signal is fed to device 9, a driving counter 2, triggers 7 and 32 and register 12 to its original state.

The process of reading information from memory blocks 5 and 29 is similar to the process of writing the device operation algorithm into memory blocks 5 and is controlled by generator 1, counter 2, decoder 3, 4, 26 and 28, triggers 7 and 32, while reading addresses from blocks 29 memories are determined by a set of signals on the third and fourth groups of outputs of register 12 and the corresponding inputs 24 of devices that switch in this state to the input of register 11, the read addresses from memory blocks 5 are determined by a set of signals on the third and fourth groups groin register 12 and outputs the appropriate number (dial number) read from the unit

0

five

0

BP

29 memories. The number of a pair of blocks 5 and 9 of the memory from which the city of reading is produced is determined by the set of signals from the fifth group of outputs of the register 12 and the signal from the decoder 26, respectively. This provides the possibility of increasing the memory of the device to the required dimensionality tasks. The multiplexers 20 commute to the input of the register 11 in each qth state of not more than K inputs, and the functions for determining the states are removed from the fourth group of outputs of the register 12. They serve to combine the states of the device in which only a small number of input variables are analyzed and save the memory of control devices,

In the output signals of the blocks 29, the numbers of the sets of background variables are coded, which are the youngest part of the address word of the 5 memory blocks. The output signals of the memory blocks 5, which are fed to the inputs of the decoder 21, encode the output functions of the control device. At the same time, the subgroups of output signals, which are fed to the inputs of the corresponding deshators, are chosen so that inside each of them the signals take on the true value at times that do not coincide with other signals of the subgroup. This is a group of 23 outputs. The output signals, for which coding cannot be performed, are output directly to the device output. (Group of outputs 22).

Claims (1)

Invention Formula Software control device containing pulse generator, counter, first and second decoders, memory block, first and second switch groups, first trigger, AND element, delay element, address register, output register, multiplexer group, decoder group - The properties are connected to the control inputs of the switches of the first and second groups, the outputs of the first group of switches are connected to the first group of information inputs of the address register, the first group of outputs of which is connected to the howling group de1iifratora first inputs, the outputs of which are connected to the address input unit na 50 five about 0 5 0 5 five 58 MIs, whose pyholems with (.) oiienes are correspondingly (informational inputs of the output register, the first group of KOTopoi O outputs are connected to the corresponding inputs of the group decoders, the outputs of which are connected to the first group of the device’s output, the second group of outputs of the output register is connected to the second group of device outputs, the output of the generator is connected to the first input of the element I, the input start of the device is connected to the second element And, the output of which is connected to the counting input of the counter, the outputs of which are connected to the inputs of the second the encoder, the first output of which is connected to the write register address enable input, the second output of the second decoder is connected to the setup input of 1 first trigger, the third output of the second decoder is connected to the write register write output output input, the device reset input is connected to the output register reset input. the first reset input of the counter and with the first input of the installation in O of the first trigger, the fourth output of the second decoder is connected to the second input of the installation in. About the first trigger, with the input of the delay element and with the output the sign of the end of the device operation, the output of the delay element is connected to the second reset input of the counter, the output of the first trigger is connected to the memory access enable input, the group of information inputs of the device is connected to the data input group of the memory block, the third output output register is connected respectively the first information inputs of the switches of the first group and with the group of control inputs of the multiplexers of the group, the first and second groups of inputs of the logical conditions of the device are connected respectively but with the second information inputs of the switches of the first and second groups, the third group of inputs of the logical conditions of the device is connected to the first group of information inputs of the multiplexers of the group, the fourth group of outputs of the output register is connected to the second group of information inputs of the multiplexers of the group, in order to save equipment, the device contains a group of elements And, the second 713 the trigger, the first and second groups of memory blocks, the third and fourth decoders, the fourth group of inputs of the logical conditions of the device connected to the first inputs of elements AND groups whose outputs are connected to the second group of information inputs of the address register, the input of the device mode selection connected to the second inputs Both the groups and the inputs of the resolution of operation of the multiplexers of the group, the outputs of which are connected to the second group of information inputs of the address register, the first and second groups of outputs of which are connected to the input The third decoder, the outputs of which are connected respectively to the address inputs of the memory blocks of the first group, the outputs of which are connected by the second group of inputs of the first decoder, the outputs of which are connected to the address inputs of the memory blocks of the second group, the outputs of which are connected to the group of information inputs of the output register, that group of outputs is connected respectively with the first information eight iJTOpofi i-pyn switches, the outputs of which are connected to the inputs of the fourth decoder, the outputs of which are connected to the work enable inputs of the corresponding memory blocks of the first and second groups, the first write enable input of the device, the second input of the device recording permission is connected to the inputs of the recording permission of the memory blocks of the second group, the group of information inputs of the device is connected to the data inputs of the memory blocks of the first and second groups, the reset input of the device The data is connected to the first input of the installation to the second trigger, the output of which is connected to the inputs of the permission of the memory blocks of the first group, the output of the first trigger is connected to the inputs of the resolution of the work of the memory blocks of the second group, the fourth output of the second decoder is connected to the second input of the second settings the trigger, the fifth output of the decoder is connected to the input of the installation in 1 of the second trigger. hch c 10 /: 10, P j  at -eleven Qu five, 7OV . 3i h; to l the composer A. Mihailov Editor E. Papp Tehred M. DVDKKorrektor G. Reshetnik Order 4223/39 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Sh 25, 26 g 2f 2 h-7- k . 23 22; 2Zp 7Dt FIG. 2