SU615514A1 - Apparatus for monitoring employee coming-in and coming-out - Google Patents

Description

one

The invention relates to intruder alarm devices and can be used in enterprise burglar alarm systems in automating the control of the exit and entry mode of workers and employees at enterprises checkpoints.

Devices are known that are designed to automate the functions of controlling input-output mode at checkpoints of enterprises, containing switching elements, a command receiving unit, logical nodes and a memory block. However, the known devices have discomfort due to which they have not found wide application in the objects of national economy, namely, the devices are characterized by complexity and the presence of a large number of nodes. In addition, devices do not provide reliable control of the use of individual signaling ciphers.

The closest to the proposed technical solution is a device for controlling the input and output of workers and employees, containing a command receiving unit, the inputs of which are connected to the input buses of the device and the outputs are connected to the first inputs of the AND elements, the other inputs of which are connected to the output of the imaging unit.

output information, and the outputs through the OR element - with the input of the memory block, the outputs of which are connected to the first inputs of the AND elements, the second inputs of which

connected to the outputs of the decoder, and the outputs - with the element OR. However, here again, a daily preparation of the device for operation is necessary, due to the tactics of the device, except

Moreover, the number of individual ciphers is not enough, limited by the number of contact pairs of switching elements and control of the initial use of individual ciphers is not reliable enough.

The aim of the invention is to improve the reliability of the device and the expansion of its functionality.

For this, two devices have been entered into the device.

groups of electoral circuits, limiter, information recording instructions driver, additional AND element, matching node, two memory control block generators, additional

the OR elements, the memory elements, the analysis register polling driver, and the inverter group. The outputs of the first group of electoral circuits are connected via an additional OR element to the input of the output information generator, and their first inputs are connected to the output of the polling signal of the analysis register, the second to the corresponding outputs of the receiving unit and the third to the outputs of the memory element whose first input is with the output of the gragger, and the second with the output of the AND element connected by one input to the output of the corresponding OR element, and the other parallel to the input of the generator of the polling signals of the analysis register and the inputs from sponding elements and - to the output of the recording command information, the input of which parallel to the input matching unit connected to the output of the first shaper sigialov memory control unit. The second driver of the control unit of the memory unit is connected to the output of the OR element and the second input of the matching unit connected to the output of the second input of the memory unit connected to the outputs of the corresponding memory elements, the first inputs of which are combined in parallel with the input of the first generator of the control signals of the memory unit connected via a limiter to the output of the command receiving unit, and the second inputs of these memory elements are connected via the corresponding OR element to the outputs of the selective circuits, the first of which the first input is connected to the output of the corresponding OR element, the second input is connected to the output of the corresponding inverter, and the third input is connected to the corresponding output of the memory unit to which the first input of the second selective circuit is connected, the other input of which is connected to the output of the corresponding OR element to which the first entry of the third selectively; circuit, the second input of the inverter is connected to the corresponding output of the decoder.

The drawing shows a block diagram of a control device containing a command receiving unit 1, a protection unit 2, a logic unit 3, a decryptor 4, a trigger node 5, an OR element 6, an analysis register 7, an output information driver 8, a memory block 9, a block 10 adjustment, bus AND service commands, output bus 12, generator 13 of the polling signal of the analysis register, element 14, limiter 15, first driver 16 of the memory control signals, memory driver 17 of the information recording commands, second driver 18 of the memory control signals, node with 19, memory element 20, electoral schemes 21-24, element OR 25, input rails 26, informative zlly 27, a group of inverters 28, electoral circuits 29-31, elements OR 32, memory elements 33 and elements 34-34 , element OR 35, input bus 36, elements AND 37-40 and elements OR 41, 42.

Shaper 13 of the polling signals of the analysis register, element 14, limiter 15, shapers 16, 18 of the emulation unit of the memory unit, shaper 17 of the information recording command and the matching node 19 constitute a protection unit 2 connected to the outputs of the command receiving unit 1, the drain node 5 , the element OR 6 and the inputs of the analysis register 7 and the memory block 9.

The inverter 28, the selective circuits 29-31, the OR element 32 and the memory element 33 constitute informative nodes 27, the totality of which represents a correction block 10 connected to the outputs of the protection unit 2, logic block 3, decoder 4, the inputs and outputs of the memory block ty 9.

The memory element 20, the electoral circuits 21-24 and the OR element 25 comprise an analysis register 7 connected by inputs to the corresponding outputs of the command receiving unit 1 and the protection unit 2, and the output to the input of the output information driver 8.

The group of elements AND 34-34 and the element OR 35 constitute the trigger node 5 connected to the outputs of the decoder 4, the memory block 9 and one of the inputs of the protection unit 2.

Elements 37-40 and elements OR 41, 42 constitute a logical unit 3, inputs connected to the corresponding outputs of the command receiving unit 1, protection unit 2, output information generator 8, and outputs to the inputs of the OR element 6 and adjustment unit 10.

The mode of operation of the device is determined by the command received over the width of 11 service commands to the command receiving unit 1. The response information produces shaper 8 output information. Tires 26 on the memory block 9 receive the code of the lower bits of the individual cipher, in accordance with which the address of the cell containing information about the employee having this individual cipher is selected.

The decoder 4 selects a certain bit array of cells of us 9, in accordance with the code of the most significant bits of the individual cipher sent to the decoder via buses 36.

The number of informative nodes 27 and elements AND 34 corresponds to the number of bit arrays of memory cells of memory block 9. With this scheme 29, information about the exit of employees from the object is recorded, and using the electoral schemes 31, the employees enter the object. Using selective circuits 30, information is analyzed that is contained in the cells of the remaining bits of this address, in accordance with which the memory elements not selected by the decoder 4 information nodes are set.

The device works as follows.

When signals are received by the users 11 on the unit 1 for receiving commands and the individual code for the codes 26 and 36, the device generates a response signal to allow or prohibit the passage through the checkpoint through this code and records information about the employee’s arrival at the enterprise or about leaving the company . At the same time, if the right of access to the object is allowed, the command receiving unit generates resolving potentials (the signal “1 to the electoral circuit 23 of the analysis register 7 and the AND 40 element of the logic unit 3, as well as the trigger signal to the limiter 15 of the protection unit 2. The limiter 15 generates a signal reset to the memory element 20 of the analysis register 7, the memory element 33 of the adjustment block 10, and starts the first shaper 16 of the memory control signals 16. The signal generated by the shaper 16 starts the shaper 17 of the front-end information commands through the node 19 is read -information at the address arriving on code buses 26. This information in the form of a multi-digit binary number is fed to the first inputs of the AND 34 elements of the trigger node 5. The information from the outputs of the decoder 4 is received to the other inputs of these elements. On one of the outputs the decoder, in accordance with the code of the high bits of the individual pinch, received on width 36, develops the resolving potential, under the action of which the corresponding element AND 34 carries out the analysis of the information contained in the memory cell corresponding to stvuyuschey Dandan individual cipher. In the event that this cipher has not yet been used to enter the object and the memory cell has not been specially recorded with information prohibiting entry into the enterprise using this cipher, then the 34 element from memory block 9 is denied from the memory decoder 4. the potential (signal “O”) and OB remains closed. The other elements AND 34 remain closed by the inhibitory potential coming from the decoder 4, and the potential from the element OR 35 keeps the element AND 14 in the closed state. As a result, the memory element 20 remains in the initial state and at its output 43 there is a inhibitory potential, and at output 44 it is resolving. In this way, the selective circuit 23, prepared by two inputs with a resolution potential, is opened by a signal produced by the generator 13 of the polling of the analysis register. The output signal at its output passes through the OR 25 element on the output information generator 8, which, under the action of this signal, produces response information allowing the input to the object via the bus 12) And the signal

element 40. The element 40, prepared by another input by the command receiving unit 1, is triggered and the signal at its output goes through the OR element 42 to the FROM elements, 31 of the adjustment block 10 and through the OR element 6 to the memory block 9 and a second driver 18 of the control / memory unit. As a result, the selective circuit 31 of the selected decoder 4 of the informative node 27 is triggered and a signal appears at its output, which, passing through the OR 32 element, places the memory element 33 into a single state. At the exit of this memory element appears information reflecting the arrival of the employee at the facility. This information is fed to the memory unit 9 and is stored in the cell corresponding to this individual code according to the control signals generated by the shaper 18 and the element OR 6.

When you try again, use this cipher to “move to the object or when you try to enter, after the information that prohibits entry to the object by this cipher has been entered into the cell, does not produce a response signal allowing the input. In this case, when a signal is received from the memory unit 9 to the element 34, selected by the decoder 4, the resolving potential enters and is triggered. The generated signal at its output passes through the element OR 35 and prepares the element AND 14 to receive the signal produced by the shaper 17. Under the influence of this signal, it triggers and converts the memory element 20 into a single state, and the output potential 44 closes the selective circuit 23 and it does not pass the signal produced by the shaper 13 to the element 25. As a result, the shaper 8 generates information that prohibits entry to the object.

When the access to the right to exit the object is made, the device works in the same way as it does when it receives a right-to-object call.

However, in this case, the command receiving unit 1 generates resolving potentials for the elements AND 22, 39 and therefore the employee will receive permission to pass only if the memory cell corresponding to his individual cipher contains information that the employee has previously arrived at the object and no information was entered prohibiting the exit from the object. This is done as follows. The shapers of the protection unit 2, as described earlier, produce control signals, under the action of which information is read from memory unit 9 and fed to element 34. To one of them, in accordance with the code of the individual number

The resolving potential comes from the decoder 4 and it works if the corresponding memory cell contains information allowing the output from the object, since the same potential will go to this circuit from the memory block.

The generated signal at its output passes through the OR element 35 and prepares the AND 14 element to receive a signal from the transceiver 17, with the appearance of which it operates and converts the memory element 20 to the unit state. As a result, a resolving potential appears at its output 43, and the circuit 22, prepared at another input by the resolving potential, coming from the command receiving unit, passes a signal from the polling generator 13 to the element OR 25. Under the action of the current signal at the output of the element OR 25 shaper 8 generates a response signal allowing the output from the object and the signal to the element AND 39, which is triggered and the signal at the output goes through the element OR 41 the first input of the electoral circuits 29 of the adjustment block 10 and through the element OR 6 n and the memory unit 9 and the second driver 18. At this time, the second input of the circuit 29, selected by the decoder 4 of the information node 27, from the inverter 28 receives the inhibitory potential, which keeps it in the initial state. As a result, the memory element 33 of this informative node will remain in the initial state and at its output there is information reflecting the fact of the employee’s exit from the object. This information is fed to the memory block 9, where it will be recorded in the corresponding cell by the control signals generated by the shaper 18 and the OR 6 element.

When you try to use this cipher again, when the output from the object is completed, the shaper 8 of the output information does not produce permissive signals.

The recording of prohibitive ocynie information is as follows.

Upon receipt of write commands on buses II, as described above, the address of the memory cell is selected, into which the information is to be written and selected by the decoder 4 of the informative 27, which will be used to coordinate the contents of the memory cell. At the same time, the command receiving unit simultaneously with the trigger signal supplied to the limiter 15 generates a ramping potential for one of the elements And 37, 38 of the logic unit 3 and does not produce the resolving potential for the selective circuits of the analysis register 7. When a signal is received from the imager of 17 sets of information recordings on elements I 37, 38, one of them will work, and on receipt of information that prohibits

the entrance to the object, the element 38 will work, and the entry of a command prohibiting the exit from the object - the element 37.

When element 37 (38) triggers, the signal that appears at its output through the element OR 41 (42) is fed to the input of the electoral circuit 29 (31), as well as through the element OR 6 to the driver 18 and the memory block 9. At the same time, the circuit 31 of the selected node 27 from the decoder 4 comes the resolving potential, and the circuit 29 from the inverter 28, prohibits.

As a result, by a command that prohibits entry to an object, circuit 31 is triggered, and by a command that prohibits exit from an object, circuit 29 remains in its original state. When the circuit 31 is triggered, the signal from its output through the OR element 32 transfers the memory element 33 to a single state, and the information from its output is transferred to the corresponding cell of the memory block 9 using control signals produced by the imaging unit 18 and the OR element 6.

By a command prohibiting exit from the object, the selective circuit 29 of the selected node 27 remains closed and, therefore, the memory element 33 remains in the zero state. When transferring this information to the memory unit 9, the corresponding cell is set to the state prohibiting exit from the object.

The output of information from the device about the employees present or absent at the facility is carried out by a command of polling those present (absent).

The selection of memory addresses in which it is necessary to analyze the contained information is carried out in the same way as described by the command for access to the input or output right. However, in this case, the unit 1 receiving commands simultaneously with the start signal supplied to the limiter 15, generates the enabling potential to the selective circuit 21 (24) of the analysis register 7. In this case, if information was stored in the selected cell that the employee is present foTcyTCTByeT) on the object, then on the selected decoder 4, element 34 from memory block 9 receives the enabling (inhibitory) potential and it works (does not work). As a result, the memory element 20 is or is not transferred to the single state and the selective circuit 21 (24) passes or does not pass the signal from the imaging unit 13 to the OR element 25. The output information generator 8 generates a response signal indicating that the employee with the data individual cipher is present or absent on the object.

Claims (1)

Invention Formula Device for controlling the entry and exit of workers and employees, containing a unit receiving commands whose inputs are connected to the device input buses, and outputs to the first inputs of the AND elements, other inputs of which are connected to the output of the output information generator, and outputs through the OR element to the input of the memory block whose outputs are connected to the first inputs of the AND elements , the second inputs of which are connected to the outputs of the decoder, and the outputs - with the OR element, characterized in that, in order to increase the reliability of the device and expand its functionality, two groups of electoral circuits are introduced: information record commanding unit, additional AND element, matching node, two memory control unit generators, additional OR elements, memory elements, analysis register polling signal generator and inverter group, the outputs of the first group of electoral circuits are connected to the input through the additional OR element the driver of the output information, and their first inputs - with the output of the driver of the polling signals of the analysis register, the second with the corresponding; the outputs of the command receiving unit and the third with the output A memory element, the first input of which is connected to the output of the limiter, and the second to the output of the AND element connected by one input to the output of its corresponding OR element, and the other parallel to the input the driver of the polling of the analysis register and the inputs of the corresponding I-elements to the output of the driver of the information recording commands, the input of which in parallel with the input of the matching node is connected to the output of the first driver of the memory control signals, the second driver of the memory control signals is connected to the output of the OR element and the second the input of the matching node connected by the output with the second input of the memory unit connected to the outputs corresponding to their memory elements, the first inputs of which are combined and a pair allele to the input of the first shaper of the control signals of the memory unit are connected via a limiter to the output of the command receiving unit, and the second inputs of these memory elements are connected via the corresponding OR element to the outputs of selective circuits, the first of which is connected to the output of the corresponding OR element, the second input - with the output of the corresponding inverter and the third input - with the corresponding output of the memory unit to which the first input of the second electoral circuit is connected, the other input of which is connected ene yield the corresponding OR gate connected to the first input of the third selection circuit, the second input of which is parallel to the input of the inverter is connected to the corresponding output of the decoder.