RU1306360C - Device for information input with restricted access - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has introduced second decoder 9, second register 10, OR gate 12, memory unit 13, NOR gate 11, AND gate 8. Commutation elements unit 5 has two commutation elements: "record" and "clear". This provides possibility to restrict use of data by means of programming commutation elements that excluded from subsequent operations. EFFECT: prohibition of unauthorized data input. 1 dwg

Description

 The invention relates to computing and communication technology and is intended to enter control information.

 The aim of the invention is to prevent the entry of unauthorized data.

 The drawing shows a block diagram of a device.

 The device comprises a pulse generator 1, a counter 2, a multiplexor 3, a first decoder 4, a switching element block 5, a chatter protection unit 6, a first register 7, an AND 8 element, a second decoder 9, a second register 10, an OR-NOT 11 element OR 12, a memory unit 13, a timer 14, and an alarm element 15.

 The device operates as follows.

 From the generator 1, the pulses arrive at the counter 2, at the output of which all possible states of the counter 2 are successively and periodically issued, the number of which is equal to or greater than the number of possible switching elements of block 5. In this case, each of the switching elements is associated with one of the possible states (combinations) counter 2.

 The decoder 4 selects a subset of the states of the counter 2 and provides a signal to the corresponding input of block 5.

 The multiplexer 3 in the framework of the selected subset of states scans along the vertical buses of block 5, interrogating their states, and if a signal is detected, outputs it to block 6 of protection against bounce.

 Block 5 switching elements contains switching elements, the total number of which is determined by the selected alphabet. Moreover, each element corresponds to a code peculiar only to it. Block 5 contains two switching elements of a technological nature “Record” and “Erase”. When any switching element is closed, the horizontal and vertical buses are connected in accordance with the location of the element in the switching matrix.

 Thus, when the switching element of the block 5 is closed, the state of the decoder 4, the multiplexer 3, and the corresponding counter code 2 are fixed in the register 7. The fixing moment corresponds to the moment the signal arrives from the output of the chatter protection block 6.

 Block 6 generates a signal arriving from multiplexer 3 with a certain delay exceeding the transient time (bounce time), which eliminates data output errors. Element And 8 does not impede the passage of the signal to the synchronizing input of the register 7 from the output of block 6, with the exception of cases associated with programming the keyboard.

 In programming mode, the device operates as follows.

 The second decoder 9 provides the selection of states corresponding to the pressed technological buttons "Record" and "Erase".

 Register 10 is designed to memorize the actions of the “Record” and “Erase” commands until a combination appears corresponding to pressing the next button.

 The states of register 10 are recorded at the moment of arrival of the synchronization pulse from block 6. Moreover, all the time, with the exception of pressing the “Record” and “Erase” buttons, it will have zero states at the output, which excludes the recording mode in the memory block 13.

 The OR-NOT 11 element is designed to combine all operations associated with the need to block the issuance of data. The issuing of the “Record” and “Erase” commands, as well as data related to the category of unresolved, is blocked both in the recording and erasing modes and in the operating mode. In this case, in programming mode, blocking is carried out using the decoder 9, register 10 and the OR element 12, and in operating mode using the memory unit 13. The OR element 12 combines the outputs of the register 10, making the “Write” and “Erase” commands equivalent, giving when these commands appear, the write enable signal to block 13. The nature of the recorded information is determined by the technological commands: with the “Write” command, “1” is written to the memory block 13, and “0” with the “Erase” command. Recording is carried out at the moment of the pulse from the output of block 6 from the subsequent pressing after technological commands, including the “unauthorized” buttons for operation. The memory unit 13 provides the recording, storage and issuance of one-bit words recorded at the addresses and corresponding specific codes of the switching elements.

 The issuance of the status of the memory unit 13 is carried out regardless of the buttons. At the output of the memory block 13, a sequence of binary elements is formed corresponding to certain states of the counter 2 and controlling, via the OR-NOT 11 and AND 8 elements, the blocking of data output. Blocking the issue occurs when a single signal from the output of the memory unit 13.

 The timer 14 is used to set the time interval of the action of the signaling element 15, which is usually used as a light-emitting diode or sound source.

 The action of an alarm indicating that the last button pressed refers to the discharge of "unauthorized" for operation, can be interrupted by pressing the next "authorized" button for operation or by a timer after a specified time.

 Programming of the buttons (data) that are excluded from further work is performed in the following order: when the "Record" button is pressed, a signal appears at the output of the decoder 9, which will block the issuance of a command to the output of register 7 through the OR-NOT 11 and AND 8 elements. With the signal coming from the block 6, the state of the decoder 9 will be rewritten in register 10, which through the element OR 12 will allow writing to the memory unit 31 of a single state. Recording will occur when the next button is pressed and the signal from block 6 arrives. At the same time, the next (zero) state is recorded in register 10, which prohibits writing to memory block 13 and the latter goes into read mode, thereby ensuring further blocking.

 Similarly, the process of erasing previously recorded information is carried out, with the only difference being that in the memory block 13 in this case is written not "1" as before, but "0", thereby unlocking this "unauthorized" button. In the operating mode, at times corresponding to the “unresolved” buttons, the memory unit 13 blocks the output of data. With each blocking, the output of data, regardless of the nature of the blocking signal, starts the timer 14, signaling with the help of the signaling element 15 that the actions of the operators are prohibited.

 In order to avoid accidental or intentional erasure of previously recorded restrictions, the "Erase" button is structurally executed inaccessible or with the possibility of blocking it using one of the known methods, for example, filling.

 Thus, the device allows you to impose restrictions on the amount of data used, which is especially important in automated radio communication systems to limit the used power of transmitting means, to exclude the use of unauthorized frequencies and restrictions on changes in the contents of programmers. In computing systems, the device allows you to impose restrictions on the use of data and eliminates the accidental damage to programs or data by low-skilled personnel, especially in the learning process.

 The advantages of the equipment should also include a high degree of efficiency of programming processes.

Claims (1)

 A DEVICE FOR ENTERING INFORMATION WITH LIMITED ACCESS, containing a pulse generator, counter, first register, first decoder, block of switching elements, a multiplexer, a chatter protection unit, the output of the pulse generator is connected to the counter input of the counter, the information outputs of the first and second groups of which are connected to the information the inputs of the first register, the information outputs of the first counter group are connected to the inputs of the first decoder, the information outputs of the second counter group are connected to the address inputs of ultiplexer, the outputs of the first decoder are connected to the inputs of the block of switching elements, the outputs of which are connected to the information inputs of the multiplexer, the output of which is connected to the input of the anti-bounce block, one of the information outputs of the second group of the counter is connected to the control input of the anti-bounce block, the outputs of the first register are information outputs of the device, characterized in that, in order to exclude the entry of unauthorized data, a second decoder, a second register, the element And, e the OR-NOT element, the OR element, the memory unit, the information outputs of the first and second groups of the counter are connected to the inputs of the second decoder and the address inputs of the memory unit, the first and second outputs of the second decoder are connected to the information inputs of the second register, the first and second inputs of the OR-NOT the output of which is connected to the first input of the And element, the output of the chatter protection unit is connected to the second input of the And element, the gate inputs of the memory unit and the second register, the first output of the second register is connected to the first input of the element that OR and the information input of the memory block, the second output of the second register is connected to the second input of the OR element, the output of which is connected to the third input of the OR-NOT element and the write / read inputs of the memory block, the output of which is connected to the fourth input of the OR-NOT element And connected to the control input of the first register.