JPS5931157B2 - Data storage device storage content protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage content protection device for a data storage device of a sequence control device that employs the host art program method.

This type of sequence control device cyclically reads out a control program stored in a program storage device at regular intervals, takes in information from external equipment according to this control program, and executes predetermined calculations based on the results. Then, the external control targets are sequentially controlled.

When such a sequence control device executes an operation,
A data storage device is provided internally for purposes such as storing one phase of internal information or temporarily storing elapsed time information of a timer. However, since it is not known what kind of information is stored inside such a data storage device at the time of starting operation, it is necessary to clear the information. Therefore, such a sequence control device is equipped with an initial clear circuit inside. This circuit detects the starting point of operation by detecting the rise of the power supply, and generates a clear signal while the program counter specifies at least one round scan of the program storage device from this detection point, and this clear signal is generated. Clear information is written to each address of the data storage device based on designated address information of the data storage device read from the program storage device during the program execution. By installing such a circuit, the program is simplified. However, even if a momentary power outage occurs during operation and the power is restored the next time, this initial clear circuit operates and unconditionally clears all information in the data storage device. If all the contents of the data storage device are cleared, it will be impossible to continue operating in the same state as before the power outage without any erroneous operation. Therefore, conventional sea case control devices have been designed to stop operation when a power outage occurs, and to continue in the stopped state even after power is restored. Once the power has been restored, the operator manually collects the information necessary for continued operation, such as the value in the middle of counting the number of products and the process number that was being executed when the power outage occurred. It was designed to write to a predetermined address in the storage device. In the sequence control device described above, if some of the information stored in the data storage device can be protected from being cleared even after a momentary power outage occurs and the power is restored, it will be possible to continue operation without erroneous operation. There are many cases where you can proceed.

For this reason, conventionally, an auxiliary data storage device that is unaffected by the above-mentioned initial clear circuit is installed externally, and information to be retained is exchanged between this auxiliary data storage device and the sequence control device. Things were being thought of. However, this method has various problems, such as the layout of the auxiliary data storage device, the waste of input/output circuits required to control this storage device, and the creation of extra programs required to control this storage device. It was hot. The present invention has been made in view of the above-mentioned points, and even if the power supply voltage disappears due to a power supply abnormality such as a momentary power outage, and the power supply voltage is restored and the initial Talia circuit is activated, data will not be stored. It is an object of the present invention to provide a storage content protection device for a data storage device that can protect any one or more predetermined addresses of the device from being cleared.

In order to achieve the above object, the present invention is characterized by:
an initial clear circuit that generates a clear signal while the program counter scans at least one cycle of the program storage device after detecting the rise of the power supply voltage, the initial clear circuit generating a clear signal while the program counter scans the program storage device at least once, based on addressing information of the data storage device read from the program storage device; wherein clear information is written to the data storage device while the initial clear circuit is generating a clear signal, an address setting for setting one or more arbitrary addresses of the data storage device; and a means for comparing the address designation information specifying the address of the data storage device with the set address information from the address setting means, detecting a match between the two pieces of information, and outputting a match signal through the gate means. a coincidence detection means for controlling the opening of the gate means by a Talia signal outputted from the initial clear circuit, and detecting clear information to the data storage device by the coincidence signal outputted via the gate means. A storage content protection device for a data storage device that prohibits writing.

An embodiment of the present invention shown in FIG. 1 will be described below.

Reference numeral 1 denotes a program storage device, which stores a control program in which a sequence is converted into a logical formula.

2 is a program counter, and a program storage device 1
Each of the plurality of addresses is sequentially scanned and specified, and the instruction codes constituting the control program stored in each address are sequentially read out.

The program counter 2 cyclically scans and designates each address of the program storage device 1 at a constant period. 3 is an arithmetic processing unit, and 4 is an input/output circuit.

The input/output circuit 4 is composed of a plurality of sets of circuits, each of which is connected to an input device or a suitable controlled object, and stores the operating or inactive state of the input device or controlled object. Then, it receives the operand part 0PA of the instruction code from the program storage device 1, and thereby sends the logic information 1N of the circuit at the specified address to the arithmetic processing device 3. The arithmetic processing unit 3 receives the operation unit 1NST of the instruction code from the program storage device 1, inputs the logic information 1N from the input/output circuit 4, executes the operation specified by the operation unit NST, and outputs the resulting logic information 0UT. is stored in the address of the output circuit 4 specified by the operand section 0PA. Then, control objects connected to this input/output circuit 4 are sequentially controlled using the stored contents. 5 is a data storage device, and 6 is a memory control circuit that controls reading and writing of the data storage device 5.

The memory control circuit 6 inputs the instruction code from the program storage device 1 to the operation unit 1NST, decodes whether it is a read command or a write command, and sends a corresponding signal to the read/write terminal of the data storage device 3. Apply to R/W. The data storage device 5 is configured to input the operand part of the instruction code from the program storage device 1 as addressing information DAD, and input the output information of the arithmetic processing device 3 as write information WDA.
The read information RDA is input information to the arithmetic processing device 3. Then, in response to a signal from the memory control circuit 6, if this is a signal instructing writing, write information WDA is stored at the address specified by address designation information DAD, and if this is a signal instructing reading. , outputs the contents of the address specified by the address designation information DAD as read information RDA.
Reference numeral 7 denotes an initial clear circuit, which is composed of, for example, a power recovery detection circuit 8 that detects the rise of the voltage of the power supply Vcc and outputs a signal, and a monostable multivibrator 9 that operates in response to a signal from this circuit 8. The case is shown below.

Although the power return detection circuit 8 can be configured with various circuits,
It is generally constructed from an integrating circuit or the like. The monostable multivibrator 9 has its metastable time set to an arbitrary value longer than the time required for the program counter 2 to designate at least one round scan of the program storage device 1. Reference numeral 10 denotes a data gate circuit, which is interposed in a path for sending the write information WDA from the arithmetic processing device 3 to the data storage device 5, and transmits and cuts off the write information WDA by opening and closing the gate circuit.

The data gate circuit 10 is controlled to open and close by the output signal from the initial clear circuit 7, and is closed by the clear signal CL from the initial clear circuit 7 and opened otherwise. By opening this data gate circuit 10, write information W from the arithmetic processing unit 3 is input.
By applying DA as it is to the data storage device 5 and closing it, the passage of this write information WDA is interrupted,
It is configured to apply clear information to the data storage device 5 as write information WDA. Reference numerals 11, 12, and 13 are address setting means, coincidence detection means, and gate means, which constitute the main parts of the present invention.

The address setting means 11 is composed of, for example, a plurality of digital switches, and is configured such that an arbitrary address of the data storage device 15 can be set by operating these switches. The coincidence detection circuit 12 is composed of, for example, a comparator, and receives address designation information DAD specifying the address of the data storage device 5 from the program storage device 1 and set address information SAD from the address setting means 11. Then, the address designation information DAD and the setting address information SAD are constantly compared, and when the coincidence of both pieces of information is detected, a coincidence signal e is outputted. The gate means 13 is constituted by, for example, an AND circuit as shown in the figure. The coincidence signal e, which is the output of the coincidence detection means 12, is transmitted to the gate means 1.
3 to the memory control circuit 6 manually. The output of the initial clear circuit 7 is input to the control input terminal of the gate means 13. Then, the coincidence signal e
passes through the gate means 13 and is applied to the memory control circuit 6 only while the clear signal CL is generated from the initial clear circuit 7. The memory control circuit 6 receives this match signal e and applies a write inhibit signal to the read/write terminal R/W of the data storage device 5. FIG. 2 is a time chart showing the operating waveforms of each part of the sequence control device shown in FIG. 1, and Cc is the power supply C.
c voltage, a is the output of the power recovery detection circuit 8, CL is the output of the monostable multivibrator 9, e is the coincidence detection circuit 12
The output waveform of is shown.

The operation will be explained below with reference to FIG.

The program counter 2 sequentially cyclically scans and designates each address of the program storage device 1, and sequentially cyclically reads out the control program stored in the program storage device 1. The arithmetic processing unit 3 inputs information sent from the input/output circuit 4 or the data storage device 5 according to the control program, executes processing according to the control program, and outputs the results specified by the control program. It is stored at a specified address in the input/output circuit 4 or the data storage device 5. The input/output circuit 4 activates or deactivates external devices etc. according to the stored contents. In this way, the external devices are sequentially controlled according to the control program. Now, assume that an abnormality occurs in the power supply Vcc for some reason and a power outage occurs.

It is assumed that the power supply Vcc is restored at time T shown in FIG. The power return detection circuit 7 detects the return of the power supply Cc (7) and generates a power return detection signal a at time T2. This signal a activates the monostable multivibrator 9, which generates a clear signal CL having a preset time width T. When the power supply Cc is restored, the sequence control device operates normally. However, since the initial clear circuit 7 is generating the Talia signal CL, the data gate circuit 10 closes and outputs clear information. Therefore, no matter what kind of information WDA is output from the arithmetic processing device 3, this information WDA is cut off by the data gate circuit 10, and the data gate circuit 1
0 sends clear information to the data storage device 5 as write information WDA. While a control program is scanned, read out, and executed, writing is always performed to the address of the data storage device 5 used by the control program. Therefore, all addresses in the data storage device 5 used by the control program stored in the program storage device 1 are cleared. However, at a certain point in the period T during which the initial clear circuit 7 is generating the clear signal CL, for example at time T2, the same address as the setting address set by the address setting means 11 is output from the program storage device 1, and the data storage Suppose that it joins device 5. Then, the coincidence detection means 12 detects this and outputs a coincidence signal e. Initial clear circuit 7 uses clear signal CL
is generated, so the gate means 13 opens the gate. Therefore, the coincidence signal e is applied to the memory control circuit 6 through the gate means 13. As a result, the memory control circuit 6 applies a write inhibit signal to the read/write terminal R/W of the data storage device 5.
Therefore, clear information is not written to the address set by the address setter 11, and the contents of this address continue to hold the information before the power outage occurred. In this manner, at time T4 when the clear signal CL from the initial clear circuit 1 disappears, all addresses in the data storage device 5 except for the address set in the address setting means 11 are cleared. In this way, the address setting means 11
The contents of the address set in 1 will retain the contents before the power outage even if a momentary power outage or the like occurs while the sequence control device is operating. Therefore, at an address of the data storage device 5,
If the control program is configured to store information necessary for continuous operation of the sequence control device, and this address is set in the address setting means 11, the operation can continue even if a momentary power outage occurs. This eliminates the hassle of having the operator manually write in information necessary to continue operation in the event of a momentary power outage or the like. Moreover, the advantage that all addresses not set by the address setting means 11 are cleared by power-on operation can be maintained.

In addition, when it is desired to also clear the address of the data storage device 5 set by the address setting means 11 at the time of initial startup, etc., the signal line from the address setting means 11 to the coincidence detection means 12, the specified address information is sent to the coincidence detection means 12. Manually operated opening/closing means is interposed in any one of the signal line for applying DAD, the signal line from the coincidence detection means 12 to the memory control circuit 6, and the signal line from the initial clear circuit 6 to the gate means 13, and this opening/closing means is operated. When started in the open state, no match signal e is applied to the data control circuit 6, so all addresses in the data storage device 5 are cleared.

If this opening/closing means is closed after a predetermined period of time after startup, the information stored in the address set in the address setting means 11 will be retained even if the power supply Cc is turned on, unless this opening/closing means is opened thereafter. become. Further, the clear signal CL from the initial clear circuit 7 is inputted to the data gate circuit 10 via the 0R gate circuit, the coincidence signal e is inputted to the gate means 13, and the coincidence signal e is inputted via the manually operated opening/closing means. It is also possible to input the signal to the 0R gate circuit of the lever and open/close the opening/closing means. In the above embodiments, for convenience of explanation, the case where the address setting means 11 sets only one arbitrary address of the data storage device 5 has been described, but the address setting means 11
And if the coincidence detection means 12 is configured as shown in FIG.
Any plurality of addresses in the data storage device 5 can be used as addresses that are not cleared when the power is turned on.

That is, the embodiment shown in FIG.
It is possible to set only each of them or a combination of them. FIG. 3 will be explained below. That is, the main part of the address setting means 11 consists of eight selection switches SWO, SWl, SW2, .
..., SW7, and each switch SWO, SW1, SW2, ..., SW7 is connected between the power supply CO and the ground via a resistor R, respectively. The main parts of the coincidence detection means 12 include a decoder D and eight AND gate circuits AOFA1 and A2 blocks.
7 and an 8-input 0R gate circuit 0R. The decoder D transfers the addressing information DAD to the data storage device 5.
Input signals on any three signal lines of the bus to be applied to the bus, decode them, and output terminal Y corresponding to this input. ,Yl
, Y2, ..., Y7 output signals. Output terminal Y. , Yl, Y2, . . . , Y7 signals are sent to corresponding AND gate circuits A, respectively. ,Al,A2,・
..., input to the signal input terminal of A7. The respective outputs of the selection switches SWO, SWl, SW2, . . . , SW7 are connected to corresponding AND gate circuits A. , Al, A2, . . . , A7. And each AND
Gate circuit A. , Al, A2, .
2N7 to the input terminal of the 0R circuit 0R, the output of this 0R circuit 0R is outputted via the NOT circuit N8, and this output is used as the output of the coincidence detection circuit 12. In this way, for example, if the capacity of the data storage device 5 is 256 words, the selection switches SWO, SWl, SW2, . . .
..., 32 words can be set by closing one of the SW7s, and the other 32 words can be set by closing the other selection switch. Furthermore, if you close two of these selection switches, you will get 64 words, and the same goes for 94 words.
word, 128 word, etc., selection switch SWO, SWl
, SW2, . . . , SW7, any plurality of addresses can be selected. In this embodiment, the data storage device 5 is divided into eight sections, and each or a combination thereof can be set.
The number of divisions is not limited to eight, and various divisions can be made by simple modification or application of the circuit. Further, in the above embodiment, the case where the initial clear circuit 7 is configured with the power return detection circuit 8 and the monostable multivibrator 9 has been described. The counter 2 may count one value and generate the clear signal CL at least until the next value is counted.

That is, in this type of sequence control device, the program counter 2 is also reset to the address where the first instruction of the control program in the program storage device 1 is stored in response to a signal from the power return detection circuit 8. Therefore, after the power return detection circuit 8 outputs the signal, the clear signal is kept at least until the next count value of the program counter 2 specifies the address of the program storage device 1 where the first instruction of the control program is stored. It may also be something that is designed to generate.
In short, the present invention is not limited to the above, as long as it generates a clear signal while the program counter 2 specifies at least one round scan of the program storage device 1 after detecting the rise of the power supply. Further, in the above embodiments, the data storage device 5 was described as being installed alone, but a part of the program storage device 1 may be used as the data storage device 5.

As is clear from the above explanation, according to the present invention, even if the power supply voltage disappears due to a power supply abnormality such as a momentary power outage, and then the power supply voltage is restored and the initial clear circuit is activated, the data storage device Any one or more predetermined addresses can be protected from being cleared. Therefore, if the control program is configured to store information necessary for continuous operation of the sequence control device at a certain address in the data storage device 5, and this address is set in the address setting means 11, power outages can be avoided. Even if a problem occurs, operation can continue from the moment the power is restored. Therefore, it is possible to completely eliminate the trouble of having the operator manually write information necessary for continuing operation into a predetermined address of the data storage device in the event of a power outage. Furthermore, the configuration is extremely simple, inexpensive, and easy to operate compared to the conventional configuration in which an auxiliary data storage device that is unaffected by the initial clear circuit is installed externally.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of a sequence control device to which the present invention is applied, Fig. 2 is a time chart showing operation waveforms of each part of Fig. 1, and Fig. 3 is another example of the main part of the present invention. FIG.

Claims (1)

[Claims] 1. An initial clear means is provided for generating a clear signal while the program counter specifies at least one round scan of the program storage device after detecting the rise of the power supply voltage, and the initial clearing means generates a clear signal while the program counter specifies at least one round scan of the program storage device, and an address for setting any one or more addresses of the data storage device, in which the initial clear circuit writes clear information to the data storage device while the initial clear circuit is generating a clear signal; A setting means compares the address designation information specifying the address of the data storage device with the setting address information from the address setting means, detects a match between the two pieces of information, and outputs a match signal via the gate means. a coincidence detecting means for controlling the opening of the gate means by a clear signal output from the initial clear circuit, and controlling the opening of the gate means by a clear signal outputted from the initial clear circuit, and detecting the clear information to the data storage device by the coincidence signal outputted via the gate means. A storage content protection device for a data storage device that prohibits writing.