JPS5972689A - Program loading system - Google Patents

Abstract

PURPOSE:To erase the storage content with a simple constitution and to prevent erroneous erasure by controlling the erasure of the program instruction of a storage device and the load in response to the coincidence between input data and a prescribed data. CONSTITUTION:When the input data via an encoder 11 and a register 12 is coincident with a prescribed data such as data 00 not being the program data of a prescribed data generating circuit 20, a write control circuit 13 is controlled via a data comparison circuit 21, the data 00 is written in an address of a program data memory 16 accessed by an address generating circuit 15, and the data is erased substantially. Further, the circuit 21 transmits the input via the register 12 as it is as the program instruction when the comparison result is dissident, and this is loaded. Then, the storage content is erased with a simple constitution not requiring an erase switch and a memory clear control circuit and the erroneous erasure is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program loading system, and more particularly to a program for storing a program instructing a series of operations so that a plurality of songs are played in a predetermined playing order in a storage device of an automatic performance player or the like. Regarding loading method.

Each command in a program that instructs a series of operations of an automatic performance player or the like is recorded on a recording medium such as a record, for example, with data specifying each of a plurality of songs to be played.
It is made up of numerical values that indicate the recording order of the specified songs, and serves as a performance instruction for the specified song.

A program loading device for storing a program formed by a plurality of such instructions in a storage device using a conventional program loading method is shown in FIG. This is a numerical key switch for generating data corresponding to each decimal number. Key switch SWo%
Each of the SWs 9 has one end grounded and the other end connected to each of the corresponding input terminals of the encoder 11. When one of the key switches swo to SW is selectively pressed, a low level signal is supplied to the corresponding input terminal of the encoder 11. Then, the encoder 11 outputs 4-focus data encoded in BCD (binary coded decimal) corresponding to each decimal number from 0 to 9 and a key human force detection signal α consisting of, for example, a high level signal. .

The 4-bit data output from the encoder 11 is supplied to the register 12. Further, the key human force detection signal α output from the encoder j1 is supplied to the write control circuit 13. A write command input terminal of the write control circuit 13 is connected to a write command switch SW whose one end is grounded, and the other end of which is grounded. By suppressing the write command switch SW, □, an input data write command signal consisting of a low level signal is supplied to the write command input terminal. Also,
This write control circuit 13 includes a memory clear control circuit 14.
A predetermined data write command signal C is supplied. The write control circuit 13 supplies a clock pulse d to the register 2 when the key human power detection signal α is supplied, and outputs an output vanofer control signal e to the register 2 for a predetermined time when the input data write command signal is supplied. 12, a write address generation command signal f is also supplied to the address generation circuit 15, and when a predetermined data write command signal C is supplied, the write address generation command signal f is supplied to the address generation circuit 15. . The register 12 has a configuration in which, for example, two 4-bit parallel registers are connected, and the register 12 latches the data supplied from the encoder 1 to the register in the previous stage by the clock pulse d supplied from the write control circuit 13. The data held in the previous register is launched into the subsequent register. Therefore, the key switches sw1 to sw9 are selectively suppressed by 2
By doing this repeatedly, the decimal number 2 is stored in register 12.
Data for digits is retained.

Next, when the write command switch SW, □ is pressed, the write control circuit 13 supplies the output buffer control signal e to the register 12, and the write address generation command signal f.
is supplied to the address generation circuit]5.

The address generation circuit 15 includes, for example, a 4-bit binary counter that counts and amplifies in response to the write address generation command signal f and the read address generation command signal g, and a monostable multivibrator that is triggered by the read address generation command signal g. It has become. The output of the binary counter in this address generation circuit 15 is supplied to the address input terminal of the memory 1Ji5. Further, when the output buffer control signal is supplied to the register 12, the output buffer in the register 12 is activated,
The 8-pin data, in which the lower 4 bits are formed by the output of the register in the previous stage and the upper 4 bits are formed by the output of the register in the latter stage, that is, the data for 2 digits of the BCD encoded lO base number, is transferred to the output buffer. It is sent to bus 17. Then, the two-digit decimal number data sent to the data bus 17 is stored in the storage location in the memory 16 specified by the output of the address generation circuit 15 as a command for instructing the operation of the automatic performance player.

By repeating the operation of selectively suppressing key switches swo-sw9 twice and then suppressing switches SW and □ a predetermined number of times, a series of operations is performed so that automatic performance is performed according to a predetermined performance order. The commanding program is stored in memo January 6th.

Here, when a wrong program is stored due to an erroneous operation of the key switch swo-sw9, etc., and if you want to erase the stored contents of the memory 16, press the clear switch SW, 2 whose one end is grounded, and the other end of the switch 5W12 A clear command signal consisting of a lower level signal is supplied to the memory clear control circuit 14. The memory clear control circuit 14 supplies a predetermined data write command signal C to the write control circuit 13 a predetermined number of times at predetermined time intervals when the clear command signal C is supplied, and also outputs a two-digit decimal number.
oo'' and is configured to send 8-bit data encoded in BCD to the data bus 17. Therefore, when the clear switch 5W12 is pressed, the counter in the address generation circuit 15 counts and amplifies the program. The address designating the storage location in the memory 16 where the program is to be stored changes sequentially, and data "00" is sequentially written to the location where the program was stored, and the stored contents of the memory 16 are erased.

For example, when an automatic performance start switch (not shown) is pressed after the program is stored in the memory 16 without error, a read command signal is supplied to the read control circuit 18 from the control circuit (not shown) of the automatic performance player. Ru. Then, the read address generation command signal g is supplied from the read control circuit 18 to the address generation circuit 15. In the address generation circuit 15, a read address generation command signal g
As the binary counter counts up, the monostable multi-vibrator is triggered and, for example, a high-level signal i with a predetermined time width is output from the Q output terminal of this monostable multivibrator. and is supplied to the clock input terminal of the output sofa circuit 19. Then, the memo January 6 is in the read mode for a predetermined period of time, and the address generation circuit 15
The instruction stored at the location specified by the address output of is read out and sent to the data bus 17. This read command is held in the output bannofer circuit 19 when, for example, the high level signal i of a predetermined time width outputted from the address generation circuit 15 disappears. The commands held in the output buffer circuit 19 are then supplied to a control circuit (not shown) of the automatic performance player.

As mentioned above, in devices using the conventional program loading method, a Clear Inch 5W12 is required to erase the memory contents of Memo January 6, which increases the number of operation switches and creates design constraints when downsizing the device. As the number of notes increases, it becomes easier for the operation switch to be operated erroneously, and in the worst case, the stored contents of the memo January 6 may be erased by mistake.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a program loading method that does not require an operation switch for erasing the contents of a storage device and can prevent the contents of a storage device from being erased accidentally. The program loading method is characterized by comparing input data with predetermined data and erasing the contents of the storage device only when the input data and the predetermined data match.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

As shown in FIG. 2, the key switch swo-sw9. Write command switch SW1□, encoder 11. register 12
, write control circuit 13. Address generation circuit 15. Memory 16. Data bus 17. Read control circuit 18. The output sofa circuit 19 is connected in the same manner as in FIG.

However, in this example, the BCD coded 8
Predetermined data generation circuit 20 that outputs predetermined bit data
is provided. The output of this predetermined data generation circuit 20 is supplied to a data comparison circuit 21. The data comparison circuit 21 supplies a predetermined data write command signal C to the write control circuit 3 a predetermined number of times at predetermined time intervals when the bit pattern of the output of the register 12 and the bit pattern of the output of the predetermined data generation circuit 20 match. At the same time, the 8-bit B corresponding to the 2-digit decimal number "00"
Sends the CD encoded data to the data bus 17,
The register 12 is configured to send the output of the register 12 to the data bus 17 when the two bit patterns do not match.

In the above configuration, the data output from the predetermined data generation circuit 20 is data that cannot be a command in a program that instructs a series of operations of the automatic performance player, that is, data that corresponds to the decimal number °゛OO'', for example. Then, like the device in Figure 1, press the key switch swo.
- Memo 1 is a program that commands a series of operations by repeating the operation of selectively suppressing SW9 twice and then pressing switch SW, , for a predetermined number of times.
116.

In addition, after selectively suppressing the key switches 5Wo-8W9 twice in succession so that the same data as the data output from the predetermined data generation circuit 20 is held in the register 2, the switches SW, □ When the data is suppressed, the data compared in the data comparison circuit 21 match, and the data comparison circuit 21 supplies the write control circuit 13 with a predetermined data write command signal C a predetermined number of times at a predetermined time interval, and a two-digit decimal number ゛00 8-bit BC corresponding to “
D-coded data is sent to the data bus 17. Then, in the apparatus shown in FIG. 1, the clear switch SW. The counter in the address generation circuit 15 counts up in the same way as when ``is pressed'', and the memory location where the program was stored is changed in sequence. Data “00” is sequentially written to the memory 16.
The memory contents of will be erased. Further, when a read command signal is supplied to the read control circuit 18 from the control circuit (not shown) of the automatic performance player, the memo
The instructions stored in are read out and output from the cover sofa circuit 1.
It is held at 9. The command held in the output bumper circuit 19 is sent to a control circuit (not shown) of the automatic performance player.

In the above operation, the contents of the memory 16 are erased by pressing the numeric input key switch swo- in the same way as when each instruction forming the program is stored in the memo 6.
This is when the data sent from the register 12 to the data comparison circuit 21 by operating sw9 and the write command switch SW, □ matches the predetermined data, so there is no need for an operation switch such as a clear switch for erasing the stored contents. Since the number of operation switches can be reduced, it is possible to easily downsize the device and reduce erroneous operations. Furthermore, since the stored contents of the memory 16 are erased only when a plurality of operation switches are operated in a predetermined procedure, it is possible to expect the effect that erroneous erasure of the stored contents due to erroneous operations can be prevented.

FIG. 3 is a block diagram showing an example in which a microconbeater is used to configure a device for storing in a storage device a program that instructs an automatic performance player to perform a series of operations using the program loading method according to the present invention. In FIG. 3, timing pulses having different generation times are supplied from a timing pulse generation circuit 30 to each input signal line of a key matrix 31. In FIG. The output signal lines that intersect with the input signal lines are connected to the operation switch detection circuit 32.
is connected to the input terminal of At each intersection of the input signal line and the output signal line, key switches SWo to SW9 and a write command switch SW are provided so as to connect the two signal lines when pressed. switch 5W
When any one of o-8W9 and SW is suppressed, one of the timing pulses having different generation times is supplied to one of the input terminals of the operation switch detection circuit 320.

Then, the operation switch detecting circuit 31 identifies the operation switch that has been suppressed and outputs 4-bit BCD encoded data corresponding to that operation switch. This 4-pin data is supplied to the input port 33 and launched. A read command signal is also supplied to the input port 33 from a control circuit (not shown) of the automatic performance player. From this input port 32, information indicating whether 4-bit data has been launched, information indicating which of the numerical input key switch and write command switch has been pressed, and information indicating whether a read command signal is supplied. The 8-pin data including the 4-pin data latched together with the information shown is taken into the processor sensor 35 via the data bus 34. Pro sensor 35, ROM36, RA
Processes the captured data in cooperation with M37.

Then, the processor 35 uses a predetermined area of the RAM 37 as a program memory area to store therein a program that instructs a series of operations of the automatic performance player, erases the stored contents of the program memory area, or erases the contents stored in the program memory area. (Read the command to output port 3
8 to a control circuit (not shown) of the automatic performance player. Note that the address output of the processor 35 is sent to the input port 33 and the ROM 3G via the address node 39.
, RAM 37, and output port 38.

A part of the operation of the device according to the invention shown in FIG.
This will be explained with reference to the flowchart shown in the figure. The switch input processing operation includes determining whether or not the operation switch has been suppressed (FIG. 3, 81). Determine whether the suppressed operation switch is a numerical value or not (
Figure 32). When the numerical character input is suppressed, the 4-bit data contained in the data taken in from the input port 33 is stored in the RAM 370.
The 4-bit data that has already been written to the memory having a storage capacity of 8 bits set in a predetermined location other than the program memory area is written so as not to be erased (33 in the same figure), and returns to Sl. . If the suppressed switch is not a numerical value of 1 or 2 inches, it is determined whether the write command switch has been suppressed or not in step S4J of the same figure, and if the write command switch has not been suppressed, the process returns to S1. If the suppressed switch is a write command switch, it is determined whether data corresponding to the two-digit decimal number "00" has been written into the buffer (see Figure 8).
5). If the data corresponding to "00" has been written in the buffer, the memory contents in the program memory area in the RAM 37 are erased (FIG. 36) and the process returns to Sl.The data corresponding to "00" is written in the buffer. If not, the data written in the buffer is written in the program memory area of the RAM 37 as an instruction (see FIG. 37). Then, add 1 to the address value for specifying the storage location in the program memory area (see Figure 8).
8), return to Sl.

However, when the above-mentioned device is installed, the contents of the memory that stores the program that commands a series of operations of the automatic performance player can be erased by writing a decimal number "00" into the buffer when the write command switch is pressed. Since this is done when data has been written, the same effect as the device shown in FIG. 2 can be obtained.

In the above embodiment, the input data is decimal '0'.
It is assumed that the contents of the memory will be erased if the data corresponds to 0"Ic, but if the program is not written to the storage device of a device such as an automatic performance player where the decimal number "oo" has a meaning, for example, an arithmetic device. In the case of loading, the contents of the memory may be erased when data corresponding to the maximum value, such as the decimal number "99", is input.

In addition, in this example, the input data is BCD encoded 8-bit data that corresponds to a 2-digit decimal number, but it is also assumed that the input data corresponds to a 2-digit hexadecimal number or a 2-digit octal number. The present invention can be applied even when the data is 8 bits or 6 pits, and the present invention can also be applied when the number of digits of input data is not 2 digits (3 digits or 4 digits).

As detailed above, according to the program loading method according to the present invention, input data and predetermined data are compared, and when the input data and the predetermined data match, the memory contents of the storage device into which the program is loaded are erased. ,
Since an operation switch for erasing memory content is no longer necessary, it is possible to expect the effects that the equipment can be easily downsized and erroneous operations are reduced. Furthermore, since the stored contents are erased only when a plurality of operation switches are operated in a predetermined procedure, it is possible to expect the effect that erroneous erasure of the stored contents can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an apparatus for storing a program in a storage device using a conventional program loading method, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. 4, a block diagram showing the embodiment, is a flowchart showing the operation of the apparatus shown in FIG. 3. Explanation of codes of main parts 11...Encoder 12...Register 13
...Write control circuit 15...Address generation circuit 16...Memory 20...Predetermined data generation circuit 21.
・Data comparison circuit 30 ・Timing pulse generation circuit 31 ・Key matrix 32 ・Operation switch detection circuit 33 ・Input port 3
5... Processor 36... ROM3
7. RAM Applicant Pioneer Co., Ltd. Agent Patent Attorney Motohiko Fujimura

Claims (1)

[Claims] A program loading method for storing a program instructing a series of operations so that a plurality of songs are played according to a predetermined playing order in a storage device of an automatic performance player, etc., the step of comparing input data and predetermined data. , erasing the storage contents of the storage device when the input data matches the predetermined data; and when the input data and the predetermined data do not match, storing the input data as an instruction in the program; A program loading method comprising the step of storing the program in a device.