SU733018A1 - Buffer memory - Google Patents

Description

one

The invention relates to a calculator. A technique that can be used in servicing subscribers' requests in the order they are received.

A device for accumulating incoming information is known, comprising a multi-stage shifting accumulator, a polling unit, and AND elements.

The additional register included in the scheme for storing information that is in service reduces the reliability of the device.

A buffer storage device is known, which contains series-connected groups of memory cells and control cells corresponding to each such group and consisting of a bi-memory element, a coincidence element and an arrest element G2.

In such a device, the transmission of information. A group of free storage cells is passed through the preceding cells, which reduces the circuit operation efficiency.

The closest to this technical solution is a buffer memory device containing a register registerkave array, the set inputs KOTOpbJX are connected to the outputs of the first AND elements, the first inputs of which are connected to the input buses of the device, and the second inputs to the inverse outputs of the control register, the setting inputs which is connected to the outputs of the first OR elements, the inputs of which are connected to the inverse outputs of the corresponding storage registers 3.

A disadvantage of the known device is the limited performance of the sequential operation of the registers and the delay in processing the next subscriber request.

The purpose of the present invention is to improve the speed and reliability of the device.

The goal of the facility is to ensure that the vcrpoiV-Too is stored in the buffer.

impulse distributor, pulse formers, AND elements and OR elements are entered, the direct outputs of the control register are connected to the third inputs of the first AND elements of the corresponding storage registers and to the inputs of the second OR element, the output of which is connected to the control input of the pulse distributor are connected to the inputs of the corresponding pulse formers and to the first inputs of the second elements And, the second inputs of which are connected to the direct outputs of the corresponding storage registers and outputs W ryh AND elements are connected to the inputs of third OR elements, moves BL are connected to the output busbars device vkody impulEzsov shapers are connected to respective reset inputs of storage registers to the control register posledne1T1 inverse output of which third discharge element podyugyuchen to pervm inputs minutes,. the second inputs of which are connected to the forward output control register, except for the first and last, and the outputs of the third AND elements are connected to the inputs of the fourth OR element, the output of which is connected to the third inputs of the first AND elements of the first storage register.

The drawing shows a functional diagram of the buffer storage device.

The device contains memory registers 1, the first elements And 2, re-. control gist 3, the first elements OR .4, and the storage registers 1 are executed on the triggers 5, the second element OR 6, the pulse distributor 7, the second elements AND 8, the third elements OR 9, the formers of pulses Yu, the third elements AND 11 and the fourth element OR 12. In the initial state, registers 1 and 3 are reset and the first And 2 elements of the first storage register 1 are open to receive the request, and the request for subsequent storage registers 1 is prohibited by signals from the direct outputs of the control register 3, which prohibit the operation of elitel pulses 7 via an OR gate 6. Received request by changing the state of the control register 3 via the first OR 4, thus permits delivery of the next request ele- blowing storage register 1 and including

pulse distributor 7, the output of which sequentially begins to interrogate the storage registers 1 and transmit the information read from them

the formation to the output of the device through the second elements AND 8 and the third elements OR 9. Resetting the storage registers and the control register after polling occurs on the falling edge of the signal from

pulse distributor 7.

If at this moment the following requests arrive at the device's input, they will be written to the subsequent memory registers 1. In order to exclude

writing subsequent requests to the first memory register, which zeroed out reading the information from it, in the absence of information on the requests in the last memory register and

if it is in intermediate registers, i.e. to observe the order of registering requests from the inverse output of the last bit of control register 3 to the first inputs of the third elements 11

there is a signal prohibiting such

write to first memory register 1,

In the presence of information in the last register 1 or in the absence of it in the intermediate storage registers. : Writing requests to the first memory register is permitted.

Claims (1)

35 claims Buffer memory device containing a matrix of memory p & gistra, the installation inputs of which are connected to the outputs of the first elements AND, the first inputs of which are connected to the input buses of the devices, and the second inputs to the inverse outputs of the control register, the installation inputs of which are connected to the outputs of the first elements OR whose inputs are connected to inverse codes of the corresponding storage registers, characterized in that, in order to increase its speed and reliability, a pulse distributor is inserted into it s, pulse shapers ,, the AND and OR elements, straight v1hody control register coupled to the third inputs of the first member and the respective storage registers and to the inputs of the second OR gate whose output is connected to a control input of distribution