CN113946524B - Read-write dual-port RAM system and method based on FPGA - Google Patents
Read-write dual-port RAM system and method based on FPGA Download PDFInfo
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Abstract
The invention discloses a read-write dual-port RAM system and a method based on FPGA, the system comprises a main control system and a plurality of data acquisition systems, wherein the data acquisition systems comprise: the data acquisition communication module is used for acquiring data; the CPU module is connected with the data acquisition communication module and is used for receiving, storing and transmitting the data information acquired by the data acquisition communication module; the FPGA module comprises an upper module and a lower module, wherein the upper module performs information interaction with the main control system or the CPU module through an upper module dual-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module dual-port RAM, the upper module dual-port RAM and the lower module dual-port RAM are built on the FPGA chip, and the CPU module and the main control system realize data information read-write interaction through the upper module dual-port RAM and the lower module dual-port RAM. The advantages are that: the system realizes high-speed and reliable data transmission of the CPU module and the main control system through the double-port RAM based on the FPGA chip.
Description
Technical Field
The invention relates to the technical field of digital processing of railway traffic signals, in particular to a read-write dual-port RAM system and method based on an FPGA.
Background
With the rapid development of electronic technology, a large number of high-speed data acquisition control systems put higher demands on the communication function and performance of modern railway traffic signals. In a high-speed data acquisition system, a common data transmission system can cause a data blocking phenomenon under the condition of large data volume, and the quality of the data acquisition system can directly influence the working performance of the whole communication system. The development trend of the data acquisition system is high-speed and real-time, and high requirements are put on the transmission and control speed of the data, so that in order to enable the control system and the data acquisition system to quickly and effectively exchange information, the system resources are fully utilized, and a system and a method capable of quickly processing traffic signals in rail transit are urgently needed.
Disclosure of Invention
The invention aims to provide a read-write dual-port RAM system and a read-write dual-port RAM method based on an FPGA (field programmable gate array), which realize high-speed and reliable data transmission of a CPU (central processing unit) module and a main control system through an upper module dual-port RAM and a lower module dual-port RAM of an upper module and a lower module based on FPGA chips, wherein the dual-port RAM is based on the FPGA chips, and the capacity of the dual-port RAM is divided according to the capacity of the selected FPGA.
In order to achieve the above purpose, the present invention is realized by the following technical scheme:
The read-write dual-port RAM system based on the FPGA comprises a main control system and a plurality of data acquisition systems, wherein the data acquisition systems comprise:
The data acquisition communication module is used for acquiring data;
The CPU module is connected with the data acquisition communication module and is used for receiving, storing and transmitting the data information acquired by the data acquisition communication module;
The FPGA module comprises an upper module and a lower module, wherein the upper module performs information interaction with the main control system or the CPU module through an upper module dual-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module dual-port RAM, the upper module dual-port RAM and the lower module dual-port RAM are built on the FPGA chip, and the CPU module and the main control system realize data information read-write interaction through the upper module dual-port RAM and the lower module dual-port RAM.
Optionally, the FPGA module further includes:
one end of the CPU interface module is connected with the CPU module, the other end of the CPU interface module is respectively connected with the upper module and the lower module, and the CPU module transmits data information to the upper module and/or the lower module of the FPGA module through the CPU interface module;
The first ISA interface module is connected with the upper module, and the main control system is connected with the first ISA interface module through a first ISA bus so as to communicate the main control system and the upper module;
And the second ISA interface module is connected with the lower module, and the main control system is connected with the second ISA interface module through a second ISA bus so as to communicate the main control system and the lower module.
Optionally, the CPU interface module generates a chip selection signal of the FPGA internal module, where the chip selection signal is used to confirm interaction between the CPU module and the upper module or the lower module;
The CPU interface module is used for transmitting the information data of the upper module and the lower module of the FPGA module to the CPU module.
Optionally, the main control system transmits the control command to the FPGA module through the first ISA bus or the second ISA bus, and the first ISA interface module or the second ISA interface module analyzes the read operation timing sequence and the write operation timing sequence of the control command, and converts the read operation and the write operation of the upper module dual-port RAM or the lower module dual-port RAM.
Optionally, the main control system is connected with an upper module of the FPGA module of each data acquisition system through a first ISA bus, and the main control system is connected with a lower module of the FPGA module of each data acquisition system through a second ISA bus.
Optionally, the upper module dual-port RAM or the lower module dual-port RAM is a dual-port RAM of 16Kbyte, an a port of the dual-port RAM is connected with the CPU interface module, a B port of the dual-port RAM is connected with the first ISA interface module or the second ISA interface module, and signals transmitted at the a port include: a 16-bit data bus signal, a 14-bit address bus signal, a write enable signal, a read enable signal, an interrupt signal, the signals transmitted by the B port comprising: a 16-bit data bus signal, a 20-bit address bus signal, a write enable signal, a read enable signal, an interrupt signal, an enable signal, and a direction select signal.
Optionally, the first ISA interface module and the second ISA interface module are configured to generate and clear an interrupt, write a fixed address of an address bus according to the CPU module, the first ISA bus and the second ISA bus, trigger a corresponding interrupt, read the fixed address according to the CPU module, the first ISA bus and the second ISA bus, and clear the corresponding interrupt.
Optionally, the method for reading and writing the dual-port RAM system based on the FPGA includes:
S1, a main control system sends a control command to an FPGA module;
s2, judging that the main control system performs communication interaction with an upper module or a lower module in the FPGA module according to the FPGA address information in the control command;
S3, performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command;
S4, the main control system executes the writing of the memory, sets a main control system writing completion mark and triggers the CPU module to read and interrupt; the main control system finishes writing the memory, executes the CPU module to read the memory, sets a CPU module reading completion mark, and clears the CPU module reading interrupt;
S5, the CPU module executes the writing memory, sets a writing completion mark of the CPU module, and triggers the main control system to read and interrupt; and the CPU module finishes writing the memory, executes the main control system to read the memory, sets a main control system reading completion mark and clears the main control system reading interrupt.
Optionally, the main control system sends the control command to the first ISA interface module and the second ISA interface module of the FPGA module through the first ISA bus and the second ISA bus.
Optionally, the first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence in the control command, and converts the read operation time sequence and the write operation time sequence into the read operation of the upper module dual-port RAM or the lower module dual-port RAM.
Compared with the prior art, the invention has the following advantages:
In the read-write dual-port RAM system and the read-write dual-port RAM method based on the FPGA, the system realizes high-speed and reliable data transmission of the CPU module and the main control system through the upper module dual-port RAM and the lower module dual-port RAM of the upper module and the lower module, the dual-port RAM is based on an FPGA chip, and the capacity of the dual-port RAM is divided according to the capacity of the selected FPGA.
Furthermore, the ISA bus is adopted in the system to realize the connection of the main control system and the dual-port RAM, so that the problem of incompatible speed is solved, the problem of unmatched interface protocols of the existing dual-port RAM is effectively avoided, and the dual-port RAM has good speed compatible with the ISA bus.
Drawings
FIG. 1 is a schematic diagram of a read-write dual-port RAM system based on an FPGA of the present invention;
FIG. 2 is a schematic diagram of an FPGA module of the present invention;
Fig. 3 is a schematic diagram of the functional relationship in the method of the read-write dual-port RAM system based on FPGA of the present invention.
Detailed Description
The invention will be further described by the following detailed description of a preferred embodiment, taken in conjunction with the accompanying drawings.
As shown in fig. 1, the dual-port RAM System for reading and writing based on FPGA of the present invention includes a main Control System (Control System) and a plurality of data acquisition systems (Communication circuit), wherein the data acquisition systems include: the system comprises a data acquisition communication module, a CPU module and an FPGA module. The main control system may be referred to as a VLE circuit board.
Specifically, the data acquisition communication module is used for data acquisition, the CPU module is connected with the data acquisition communication module, and the CPU module is used for receiving, storing and transmitting the data information acquired by the data acquisition communication module. The FPGA module comprises an upper module and a lower module, wherein the upper module performs information interaction with the main control system or the CPU module through an upper module dual-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module dual-port RAM, the upper module dual-port RAM and the lower module dual-port RAM are built on the FPGA chip, the CPU module and the main control system realize data information read-write interaction through the upper module dual-port RAM and the lower module dual-port RAM, for example, the CPU writes acquired data information into the upper module or the lower module, and the main control system reads the acquired data information through the upper module dual-port RAM or the lower module dual-port RAM so as to improve data transmission efficiency.
In this embodiment, as shown in fig. 1, the main control system is connected to an upper module of the FPGA module of each data acquisition system through a first ISA bus, and the main control system is connected to a lower module of the FPGA module of each data acquisition system through a second ISA bus. The CPU module is connected with the FPGA module through a Local Bus. The main control system reads and writes the upper module double-port RAM and the lower module double-port RAM through the first ISA bus and the second ISA bus, and the CPU module reads and writes the acquired data to the upper module double-port RAM and the lower module double-port RAM through the local bus.
Furthermore, the upper module double-port RAM or the lower module double-port RAM is 16KByte double-port RAM, and the maximum characteristic of the double-port RAM is stored data sharing. A memory is equipped with two separate sets of address, data and control lines allowing two separate CPUs or controllers to access memory locations asynchronously at the same time. The data interface formed by the dual-port RAM can carry out high-speed and reliable information transmission between two processors or boards. In the embodiment, the upper module dual-port RAM and the lower module dual-port RAM can realize high-speed and reliable data information transmission between the CPU module and the main control system. Furthermore, the upper module dual-port RAM and the lower module dual-port RAM are built on the FPGA chip, so that the problems of small capacity, fixed interface, mismatching rate, high cost and the like of the existing dual-port RAM chip can be avoided, the FPGA chip can well solve the problems of parallelism and speed in digital signal processing, and the flexible configurable characteristic of the FPGA chip ensures that a digital signal processing system formed by the FPGA module is easy to modify, test and upgrade, reduces the design cost and shortens the development period.
In this embodiment, an a port of the dual-port RAM is connected to the CPU interface module, a B port of the dual-port RAM is connected to the first ISA interface module or the second ISA interface module, and signals transmitted at the a port include: a 16-bit data bus signal (DATA SIGNAL), a 14-bit address bus signal (ADDRESS SIGNAL), and various Control signals (e.g., write enable signal, read enable signal, interrupt signal), the signals transmitted by the B-port include: a 16-bit data bus signal (DATA SIGNAL), a 20-bit address bus signal (ADDRESS SIGNAL), and various Control signals (e.g., write enable signal, read enable signal, interrupt signal, enable signal, direction select signal).
The FPGA module, namely the VLE circuit board, identifies the upper module double-port RAM module and the lower module double-port RAM through the base address of the FPGA plus the address of the upper module or the lower module. As shown in fig. 1 and fig. 2 in combination, the FPGA module realizes reading and writing of the dual-port RAM, and mainly includes the following modules: a CPU interface module (cpu_interface module), a first ISA interface module (first interface_isa module), and a second ISA interface module (second interface_isa module).
One end of the CPU interface module is connected with the CPU module through a local bus, the other end of the CPU interface module is respectively connected with the upper module and the lower module, and the CPU module transmits data information to the upper module and/or the lower module of the FPGA module through the CPU interface module. The first ISA interface module is connected with the upper module, and the main control system is connected with the first ISA interface module through a first ISA bus so as to facilitate data information interaction between the main control system and the upper module. The second ISA interface module is connected with the lower module, and the main control system is connected with the second ISA interface module through a second ISA bus so as to facilitate data information interaction between the main control system and the lower module.
Further, the CPU interface module parses the command of the CPU module, and then generates a chip selection signal of the internal module of the FPGA, where the chip selection signal is used to confirm with which module (upper module or lower module) the CPU module interacts. Furthermore, the CPU interface module is not only used for reading the data of the CPU module to the upper module and the lower module, but also used for returning the information data of the upper module and the lower module of the FPGA module, namely the register value, to the CPU module.
The main control system transmits control commands to the FPGA module through the first ISA bus or the second ISA bus, and the first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence of the control commands and converts the read operation and the write operation of the upper module dual-port RAM or the lower module dual-port RAM.
Further, the first ISA interface module and the second ISA interface module are configured to generate and clear an interrupt, write a fixed address of an address bus according to the CPU module, the first ISA bus and the second ISA bus, trigger a corresponding interrupt, read the fixed address according to the CPU module, the first ISA bus and the second ISA bus, and clear the corresponding interrupt.
It should be noted that, the FPGA module of the present invention is not limited to include the above modules, and may include other modules, such as a clock signal module and a counter module, according to practical application requirements, which are not described and limited herein, but only a part of modules related to data reading and writing are described.
Based on the same inventive concept, the invention also provides a method for reading and writing the dual-port RAM system based on the FPGA, as shown in figure 3, the method comprises the following steps:
S1, the main control system sends a control command to the FPGA module.
S2, judging which module (upper module or lower module) of the FPGA module is in communication interaction with the main control system according to the FPGA address information in the control command. The upper module dual-port RAM and the lower module dual-port RAM both receive address signals and then judge whether the main control system is communicated with the upper module or the lower module according to the offset address of the address, so that the dual-port RAM module corresponding to the communicated module receives the control command of the main control system and then reads and writes the data of the dual-port RAM.
S3, performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command.
S4, the main control system executes the writing of the memory, sets a main control system writing completion mark, and triggers the CPU module to read and interrupt. And after the execution of the writing memory of the main control system is finished, executing the reading memory of the CPU module, setting a reading completion mark of the CPU module, and clearing the reading interrupt of the CPU module, wherein the executing memory of the CPU module is used for reading the data written by the VLE circuit board for the CPU module, namely, after the writing of the VLE circuit board is finished, notifying the CPU module that the reading operation can be performed, and then, the CPU module reads the data.
S5, the CPU module executes the writing memory, sets a writing completion mark of the CPU module, and triggers the main control system to read and interrupt. And the CPU module finishes writing the memory, executes the main control system to read the memory, sets a main control system reading completion mark and clears the main control system reading interrupt. That is, after the writing operation of the CPU module is completed, the read interrupt of the VLE is triggered, and when the VLE receives the read interrupt, the VLE can perform the read operation. Optionally, the sequence of the step S4 and the step S5 is not mandatory, and can be exchanged according to actual requirements.
Further, the main control system sends the control command to the first ISA interface module and the second ISA interface module of the FPGA module through the first ISA bus and the second ISA bus.
Further, the first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence in the control command, and converts the read operation time sequence and the write operation time sequence into the read operation of the upper module dual-port RAM or the lower module dual-port RAM.
The FPGA-based read-write dual-port RAM system and the method are applied to practical engineering, and practice proves that stable data transmission can be realized, the reliability of data acquisition control is further improved, and the situation of large data congestion can not occur.
In summary, in the dual-port RAM read-write system and method based on the FPGA of the present invention, the system realizes high-speed and reliable data transmission between the CPU module and the main control system through the upper module dual-port RAM and the lower module dual-port RAM of the upper module and the lower module, and the dual-port RAM is based on the FPGA chip, and the capacity of the dual-port RAM is divided according to the selected capacity of the FPGA.
Furthermore, the ISA bus is adopted in the system to realize the connection of the main control system and the dual-port RAM, so that the problem of incompatible speed is solved, the problem of unmatched interface protocols of the existing dual-port RAM is effectively avoided, and the dual-port RAM has good speed compatible with the ISA bus.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (10)
1. The read-write dual-port RAM system based on the FPGA is characterized by comprising a main control system and a plurality of data acquisition systems, wherein the data acquisition systems comprise:
The data acquisition communication module is used for acquiring data;
The CPU module is connected with the data acquisition communication module and is used for receiving, storing and transmitting the data information acquired by the data acquisition communication module;
The FPGA module comprises an upper module and a lower module, wherein the upper module performs information interaction with the main control system or the CPU module through an upper module double-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module double-port RAM, the upper module double-port RAM and the lower module double-port RAM are built on an FPGA chip, and the CPU module and the main control system realize data information read-write interaction through the upper module double-port RAM and the lower module double-port RAM;
When a read-write dual-port RAM system based on the FPGA operates, judging that the main control system performs communication interaction with an upper module or a lower module in an FPGA module according to FPGA address information in a control command sent by the main control system;
performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command;
The main control system executes the writing memory, sets a main control system writing completion mark and triggers the CPU module to read and interrupt; the main control system finishes writing the memory, executes the CPU module to read the memory, sets a CPU module reading completion mark, and clears the CPU module reading interrupt;
the CPU module executes the writing memory, sets a writing completion mark of the CPU module and triggers the reading interrupt of the main control system; and the CPU module finishes writing the memory, executes the main control system to read the memory, sets a main control system reading completion mark and clears the main control system reading interrupt.
2. The FPGA-based read-write dual port RAM system of claim 1, wherein the FPGA module further comprises:
one end of the CPU interface module is connected with the CPU module, the other end of the CPU interface module is respectively connected with the upper module and the lower module, and the CPU module transmits data information to the upper module and/or the lower module of the FPGA module through the CPU interface module;
The first ISA interface module is connected with the upper module, and the main control system is connected with the first ISA interface module through a first ISA bus so as to communicate the main control system and the upper module;
And the second ISA interface module is connected with the lower module, and the main control system is connected with the second ISA interface module through a second ISA bus so as to communicate the main control system and the lower module.
3. The FPGA-based read-write dual port RAM system of claim 2, wherein said CPU interface module generates a chip select signal for an FPGA internal module, said chip select signal being used to confirm interaction of said CPU module with an upper module or a lower module;
The CPU interface module is used for transmitting the information data of the upper module and the lower module of the FPGA module to the CPU module.
4. The FPGA-based dual port RAM system of claim 2, wherein the main control system transmits the control command to the FPGA module via the first ISA bus or the second ISA bus, and the first ISA interface module or the second ISA interface module analyzes the read operation timing and the write operation timing of the control command, and converts the read operation and the write operation of the upper module dual port RAM or the lower module dual port RAM.
5. The FPGA-based read-write dual port RAM system of claim 2 or 4, wherein said main control system is coupled to an upper module of an FPGA module of each data acquisition system via a first ISA bus, and said main control system is coupled to a lower module of an FPGA module of each data acquisition system via a second ISA bus.
6. The FPGA-based read-write dual port RAM system of claim 2, wherein the upper module dual port RAM or the lower module dual port RAM is a 16Kbyte dual port RAM, an a port of the dual port RAM is connected to the CPU interface module, a B port of the dual port RAM is connected to the first ISA interface module or the second ISA interface module, and signals transmitted at the a port include: a 16-bit data bus signal, a 14-bit address bus signal, a write enable signal, a read enable signal, an interrupt signal, the signals transmitted by the B port comprising: a 16-bit data bus signal, a 20-bit address bus signal, a write enable signal, a read enable signal, an interrupt signal, an enable signal, and a direction select signal.
7. The FPGA-based read-write dual-port RAM system of claim 2, wherein the first ISA interface module and the second ISA interface module are configured to generate and clear interrupts, write fixed addresses of the address bus according to the CPU module, the first ISA bus, and the second ISA bus, trigger corresponding interrupts, read fixed addresses according to the CPU module, the first ISA bus, and the second ISA bus, and clear corresponding interrupts.
8. A method of operating an FPGA-based dual port RAM system as claimed in any one of claims 1 to 7, comprising:
S1, a main control system sends a control command to an FPGA module;
s2, judging that the main control system performs communication interaction with an upper module or a lower module in the FPGA module according to the FPGA address information in the control command;
S3, performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command;
S4, the main control system executes the writing of the memory, sets a main control system writing completion mark and triggers the CPU module to read and interrupt; the main control system finishes writing the memory, executes the CPU module to read the memory, sets a CPU module reading completion mark, and clears the CPU module reading interrupt;
S5, the CPU module executes the writing memory, sets a writing completion mark of the CPU module, and triggers the main control system to read and interrupt; and the CPU module finishes writing the memory, executes the main control system to read the memory, sets a main control system reading completion mark and clears the main control system reading interrupt.
9. The method for operating an FPGA-based dual port RAM system of claim 8,
The main control system sends control commands to the first ISA interface module and the second ISA interface module of the FPGA module through the first ISA bus and the second ISA bus.
10. The method of operating an FPGA-based dual port RAM system of claim 9,
The first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence in the control command and converts the read operation time sequence and the write operation time sequence into read operation of the upper module dual-port RAM or the lower module dual-port RAM.
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