CN113946524A - Read-write dual-port RAM system and method based on FPGA - Google Patents
Read-write dual-port RAM system and method based on FPGA Download PDFInfo
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- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
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Abstract
The invention discloses a read-write dual-port RAM system and a method based on FPGA, the system comprises a main control system and a plurality of data acquisition systems, wherein, the data acquisition systems comprise: the data acquisition communication module is used for acquiring data; the CPU module is connected with the data acquisition communication module and is used for receiving, storing and transmitting data information acquired by the data acquisition communication module; the FPGA module comprises an upper module and a lower module, the upper module performs information interaction with a main control system or a CPU module through an upper module double-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module double-port RAM, the upper module double-port RAM and the lower module double-port RAM are established on the FPGA chip, and the CPU module and the main control system realize the read-write interaction of data information through the upper module double-port RAM and the lower module double-port RAM. The advantages are that: the system realizes high-speed and reliable data transmission of the CPU module and the main control system through the double-port RAM based on the FPGA chip.
Description
Technical Field
The invention relates to the technical field of digital processing of railway traffic signals, in particular to a read-write dual-port RAM system and a method based on an FPGA.
Background
With the rapid development of electronic technology, a large number of high-speed data acquisition control systems put higher demands on the communication function and performance of modern railway traffic signals. In a high-speed data acquisition system, a general data transmission system can cause a data blocking phenomenon under the condition of large data volume, and the quality of the data acquisition system can directly influence the working performance of the whole communication system. The development trend of data acquisition systems in high speed and real time puts higher requirements on the transmission and control speed of data, and in order to enable the control system and the data acquisition system to exchange information quickly and effectively and make full use of system resources, a system and a method for realizing the quick processing of traffic signals in rail transit are urgently needed.
Disclosure of Invention
The invention aims to provide a read-write dual-port RAM system and a method based on FPGA, the system realizes high-speed and reliable data transmission of a CPU module and a main control system through an upper module dual-port RAM and a lower module dual-port RAM which are based on FPGA chips of an upper module and a lower module, and the dual-port RAM is based on the FPGA chips and divides the capacity of the dual-port RAM according to the capacity of the selected FPGA.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a read-write dual-port RAM system based on FPGA comprises a main control system and a plurality of data acquisition systems, wherein the data acquisition systems comprise:
the data acquisition communication module is used for acquiring data;
the CPU module is connected with the data acquisition communication module and is used for receiving, storing and transmitting data information acquired by the data acquisition communication module;
the FPGA module comprises an upper module and a lower module, the upper module performs information interaction with a main control system or a CPU module through an upper module double-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module double-port RAM, the upper module double-port RAM and the lower module double-port RAM are established on the FPGA chip, and the CPU module and the main control system realize the read-write interaction of data information through the upper module double-port RAM and the lower module double-port RAM.
Optionally, the FPGA module further includes:
one end of the CPU interface module is connected with the CPU module, the other end of the CPU interface module is respectively connected with the upper module and the lower module, and the CPU module transmits data information into the upper module and/or the lower module of the FPGA module through the CPU interface module;
the first ISA interface module is connected with the upper module, and the main control system is connected with the first ISA interface module through a first ISA bus so as to communicate the main control system with the upper module;
and the main control system is connected with the second ISA interface module through a second ISA bus so as to communicate the main control system with the lower module.
Optionally, the CPU interface module generates a chip selection signal of the FPGA internal module, where the chip selection signal is used to confirm that the CPU module interacts with the upper module or the lower module;
and the CPU interface module is used for transmitting the information data of the upper module and the lower module of the FPGA module to the CPU module.
Optionally, the main control system transmits the control command to the FPGA module through the first ISA bus or the second ISA bus, and the first ISA interface module or the second ISA interface module analyzes the read operation timing sequence and the write operation timing sequence of the control command and converts the read operation timing sequence and the write operation timing sequence into read and write operations on the dual-port RAM of the upper module or the dual-port RAM of the lower module.
Optionally, the main control system is connected with the upper module of the FPGA module of each data acquisition system through a first ISA bus, and the main control system is connected with the lower module of the FPGA module of each data acquisition system through a second ISA bus.
Optionally, the upper module dual-port RAM or the lower module dual-port RAM is a 16Kbyte dual-port RAM, an a port of the dual-port RAM is connected to the CPU interface module, a B port of the dual-port RAM is connected to the first ISA interface module or the second ISA interface module, and a signal transmitted by the a port includes: 16 bits of data bus signals, 14 bits of address bus signals, write enable signals, read enable signals and interrupt signals, wherein the signals transmitted by the port B comprise: a 16-bit data bus signal, a 20-bit address bus signal, a write enable signal, a read enable signal, an interrupt signal, an enable signal, a direction select signal.
Optionally, the first ISA interface module and the second ISA interface module are configured to generate and clear interrupts, perform write operation on a fixed address of the address bus according to the CPU module, the first ISA bus, and the second ISA bus, trigger corresponding interrupts, and perform read operation on the fixed address according to the CPU module, the first ISA bus, and the second ISA bus, and clear corresponding interrupts.
Optionally, a method for reading and writing a dual-port RAM system based on an FPGA includes:
s1, the main control system sends a control command to the FPGA module;
s2, judging that the main control system is in communication interaction with an upper module or a lower module in the FPGA module according to the FPGA address information in the control command;
s3, performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command;
s4, the main control system executes the write memory, sets the write completion flag of the main control system, and triggers the CPU module to read and interrupt; the main control system finishes the execution of writing the memory, executes the CPU module to read the memory, sets a CPU module read completion mark and clears the CPU module read interruption;
s5, the CPU module executes the write memory, sets the write completion flag of the CPU module, and triggers the main control system to read and interrupt; and the CPU module finishes the execution of the write memory, executes the main control system to read the memory, sets a main control system read completion mark and clears the main control system read interruption.
Optionally, the main control system sends the control command to the first ISA interface module and the second ISA interface module of the FPGA module through the first ISA bus and the second ISA bus.
Optionally, the first ISA interface module or the second ISA interface module analyzes a read operation timing sequence and a write operation timing sequence in the control command, and converts the read operation timing sequence and the write operation timing sequence into a read-write operation on the dual-port RAM of the upper module or the dual-port RAM of the lower module.
Compared with the prior art, the invention has the following advantages:
in the read-write dual-port RAM system and the method based on the FPGA, the system realizes high-speed and reliable data transmission of the CPU module and the main control system through the upper module dual-port RAM and the lower module dual-port RAM of the upper module and the lower module, the dual-port RAM is based on the FPGA chip, and the capacity of the dual-port RAM is divided according to the capacity of the selected FPGA.
Furthermore, the system of the invention adopts the ISA bus to realize the connection of the main control system and the double-port RAM, solves the problem of incompatible speed, effectively avoids the problem of unmatched interface protocols of the existing double-port RAM, and has good compatible speed of the ISA bus.
Drawings
FIG. 1 is a schematic diagram of a read-write dual-port RAM system based on FPGA according to the present invention;
FIG. 2 is a schematic diagram of an FPGA module of the present invention;
fig. 3 is a schematic diagram of an action relationship in the method for reading and writing the dual-port RAM system based on the FPGA of the present invention.
Detailed Description
The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
As shown in fig. 1, a read-write dual-port RAM System based on FPGA of the present invention includes a main Control System (Control System) and a plurality of data acquisition systems (Communication circuits), wherein the data acquisition systems include: the system comprises a data acquisition communication module, a CPU module and an FPGA module. The master control system may be referred to using VLE circuit boards.
Specifically, the data acquisition communication module is used for acquiring data, the CPU module is connected to the data acquisition communication module, and the CPU module is used for receiving, storing, and transmitting data information acquired by the data acquisition communication module. The FPGA module contains module and lower module, it carries out information interaction with main control system or CPU module through last module dual-port RAM to go up the module, the module carries out information interaction with main control system or CPU module through module dual-port RAM down, goes up module dual-port RAM and lower module dual-port RAM and establishes on the FPGA chip, the CPU module with main control system realizes data information's reading and writing interaction through last module dual-port RAM and lower module dual-port RAM, for example CPU writes in the data information who gathers in last module or lower module, and main control system reads the data information who gathers through last module dual-port RAM or lower module dual-port RAM to improve data transmission efficiency.
As shown in fig. 1, in this embodiment, the main control system is connected to the upper module of the FPGA module of each data acquisition system through a first ISA bus, and the main control system is connected to the lower module of the FPGA module of each data acquisition system through a second ISA bus. The CPU module is connected with the FPGA module through a Local Bus (Local Bus). The main control system reads and writes the upper module double-port RAM and the lower module double-port RAM through the first ISA bus and the second ISA bus, and the CPU module reads and writes acquired data to the upper module double-port RAM and the lower module double-port RAM through the local bus.
Furthermore, the upper module dual-port RAM or the lower module dual-port RAM is a 16Kbyte dual-port RAM, and the dual-port RAM is mainly characterized by storage data sharing. A memory is provided with two independent sets of address, data and control lines, allowing two independent CPUs or controllers to simultaneously and asynchronously access memory cells. The data interface formed by the dual-port RAM can perform high-speed and reliable information transmission between two processors or boards. In this embodiment, the upper module dual-port RAM and the lower module dual-port RAM enable high-speed reliable data information transmission between the CPU module and the main control system. Furthermore, the upper module double-port RAM and the lower module double-port RAM are built on the FPGA chip, so that the problems of small capacity, fixed interface, unmatched speed, high cost and the like of the conventional double-port RAM chip can be solved, the problems of parallelism and speed can be well solved by realizing digital signal processing by the FPGA chip, and the digital signal processing system formed by the FPGA module is easy to modify, test and upgrade, the design cost is reduced, and the development period is shortened.
In this embodiment, the port a of the dual-port RAM is connected to the CPU interface module, the port B of the dual-port RAM is connected to the first ISA interface module or the second ISA interface module, and the signal transmitted by the port a includes: a 16-bit Data bus signal (Data signal), a 14-bit Address bus signal (Address signal), and various Control signals (Control signals) (such as a write enable signal, a read enable signal, and an interrupt signal), where the signals transmitted by the port B include: a 16-bit Data bus signal (Data signal), a 20-bit Address bus signal (Address signal), and various Control signals (e.g., a write enable signal, a read enable signal, an interrupt signal, an enable signal, and a direction select signal).
The FPGA module, namely the VLE circuit board, identifies the upper module double-port RAM module and the lower module double-port RAM module by adding the address of the upper module or the address of the lower module to the base address of the FPGA. As shown in fig. 1 and fig. 2, the FPGA module for implementing read/write of the dual-port RAM mainly includes the following modules: the interface module comprises a CPU interface module (a CPU _ interface module), a first ISA interface module (a first interface _ ISA module) and a second ISA interface module (a second interface _ ISA module).
One end of the CPU interface module is connected with the CPU module through a local bus, the other end of the CPU interface module is respectively connected with the upper module and the lower module, and the CPU module transmits data information to the upper module and/or the lower module of the FPGA module through the CPU interface module. The first ISA interface module is connected with the upper module, and the main control system is connected with the first ISA interface module through a first ISA bus so as to facilitate data information interaction between the main control system and the upper module. The second ISA interface module is connected with the lower module, and the main control system is connected with the second ISA interface module through a second ISA bus so as to facilitate the data information interaction between the main control system and the lower module.
Further, the CPU interface module analyzes a command of the CPU module, and then generates a chip selection signal of an internal module of the FPGA, where the chip selection signal is used to confirm which module (upper module or lower module) the CPU module interacts with. Furthermore, the CPU interface module is not only configured to read data of the CPU module to the upper module and the lower module, but also configured to return information data, i.e., register values, of the upper module and the lower module of the FPGA module to the CPU module.
The main control system transmits a control command to the FPGA module through a first ISA bus or a second ISA bus, and the first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence of the control command and converts the read operation time sequence and the write operation time sequence into read-write operation on the upper module double-port RAM or the lower module double-port RAM.
Furthermore, the first ISA interface module and the second ISA interface module are used for generating and clearing interrupts, writing fixed addresses of the address bus according to the CPU module, the first ISA bus and the second ISA bus to trigger corresponding interrupts, and reading the fixed addresses according to the CPU module, the first ISA bus and the second ISA bus to clear corresponding interrupts.
It should be noted that the FPGA module of the present invention is not limited to include the above modules, and may further include other modules, such as a clock signal module and a counter module, according to the actual application requirement, and details and limitations are not repeated herein, and only a part of the modules related to data reading and writing are expressed.
Based on the same inventive concept, the invention also provides a method for reading and writing the dual-port RAM system based on the FPGA, as shown in fig. 3, the method comprises the following steps:
and S1, the main control system sends a control command to the FPGA module.
And S2, judging which module (upper module or lower module) in the FPGA modules the main control system communicates with according to the FPGA address information in the control command. After receiving the address signal, the upper module dual-port RAM and the lower module dual-port RAM judge whether the main control system communicates with the upper module or the lower module according to the offset address of the address, so that the dual-port RAM module corresponding to the communicating module reads and writes data of the dual-port RAM after receiving the control command of the main control system.
And S3, performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command.
And S4, the main control system executes the write memory, sets a main control system write completion flag and triggers the CPU module to read and interrupt. The main control system finishes the execution of writing the memory, executes the CPU module to read the memory, sets a CPU module read completion mark and clears the CPU module read interruption, wherein the execution of the CPU module to read the memory is used for reading the data written by the VLE circuit board for the CPU module, namely after the VLE circuit board finishes the writing, the CPU module is informed of the read operation, and then the CPU module reads the data.
And S5, executing the write memory by the CPU module, setting a write completion flag of the CPU module, and triggering the main control system to read and interrupt. And the CPU module finishes the execution of the write memory, executes the main control system to read the memory, sets a main control system read completion mark and clears the main control system read interruption. That is, after the write operation of the CPU module is completed, the read interrupt of the VLE is triggered, and when the read interrupt is received by the VLE, it indicates that the VLE can perform the read operation. Optionally, the sequence of step S4 and step S5 is not mandatory, and may be exchanged according to actual requirements.
Furthermore, the main control system sends the control command to the first ISA interface module and the second ISA interface module of the FPGA module through the first ISA bus and the second ISA bus.
Further, the first ISA interface module or the second ISA interface module analyzes a read operation timing sequence and a write operation timing sequence in the control command, and converts the read operation timing sequence and the write operation timing sequence into a read-write operation for the dual-port RAM of the upper module or the dual-port RAM of the lower module.
The read-write dual-port RAM system and the read-write dual-port RAM method based on the FPGA are applied to practical engineering, practice proves that stable data transmission can be achieved, the reliability of data acquisition control is further improved, and the condition of large amount of data congestion cannot occur.
In summary, in the read-write dual-port RAM system and method based on FPGA of the present invention, the system realizes high-speed and reliable data transmission between the CPU module and the main control system through the upper module dual-port RAM and the lower module dual-port RAM of the upper module and the lower module, and the dual-port RAM divides the capacity of the dual-port RAM according to the capacity of the selected FPGA based on the FPGA chip.
Furthermore, the system of the invention adopts the ISA bus to realize the connection of the main control system and the double-port RAM, solves the problem of incompatible speed, effectively avoids the problem of unmatched interface protocols of the existing double-port RAM, and has good compatible speed of the ISA bus.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (10)
1. The utility model provides a read-write dual port RAM system based on FPGA which characterized in that contains main control system and a plurality of data acquisition system, wherein, data acquisition system contains:
the data acquisition communication module is used for acquiring data;
the CPU module is connected with the data acquisition communication module and is used for receiving, storing and transmitting data information acquired by the data acquisition communication module;
the FPGA module comprises an upper module and a lower module, the upper module performs information interaction with a main control system or a CPU module through an upper module double-port RAM, the lower module performs information interaction with the main control system or the CPU module through a lower module double-port RAM, the upper module double-port RAM and the lower module double-port RAM are established on the FPGA chip, and the CPU module and the main control system realize the read-write interaction of data information through the upper module double-port RAM and the lower module double-port RAM.
2. The FPGA-based read-write dual port RAM system of claim 1 wherein said FPGA module further comprises:
one end of the CPU interface module is connected with the CPU module, the other end of the CPU interface module is respectively connected with the upper module and the lower module, and the CPU module transmits data information into the upper module and/or the lower module of the FPGA module through the CPU interface module;
the first ISA interface module is connected with the upper module, and the main control system is connected with the first ISA interface module through a first ISA bus so as to communicate the main control system with the upper module;
and the main control system is connected with the second ISA interface module through a second ISA bus so as to communicate the main control system with the lower module.
3. The FPGA-based read-write dual-port RAM system of claim 2,
the CPU interface module generates a chip selection signal of an FPGA internal module, and the chip selection signal is used for confirming the interaction of the CPU module and the upper module or the lower module;
and the CPU interface module is used for transmitting the information data of the upper module and the lower module of the FPGA module to the CPU module.
4. The FPGA-based read-write dual-port RAM system of claim 2,
the main control system transmits a control command to the FPGA module through a first ISA bus or a second ISA bus, and the first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence of the control command and converts the read operation time sequence and the write operation time sequence into read-write operation on the upper module double-port RAM or the lower module double-port RAM.
5. The FPGA-based read-write dual-port RAM system of claim 2 or 4,
the main control system is connected with the upper module of the FPGA module of each data acquisition system through a first ISA bus, and is connected with the lower module of the FPGA module of each data acquisition system through a second ISA bus.
6. The FPGA-based read-write dual-port RAM system of claim 2,
the upper module double-port RAM or the lower module double-port RAM is a 16Kbyte double-port RAM, an A port of the double-port RAM is connected with the CPU interface module, a B port of the double-port RAM is connected with the first ISA interface module or the second ISA interface module, and signals transmitted by the A port comprise: 16 bits of data bus signals, 14 bits of address bus signals, write enable signals, read enable signals and interrupt signals, wherein the signals transmitted by the port B comprise: a 16-bit data bus signal, a 20-bit address bus signal, a write enable signal, a read enable signal, an interrupt signal, an enable signal, a direction select signal.
7. The FPGA-based read-write dual-port RAM system of claim 2,
the first ISA interface module and the second ISA interface module are used for generating and clearing interrupts, writing fixed addresses of the address buses according to the CPU module, the first ISA bus and the second ISA bus to trigger corresponding interrupts, and reading the fixed addresses according to the CPU module, the first ISA bus and the second ISA bus to clear corresponding interrupts.
8. The method for reading and writing the dual-port RAM system based on the FPGA according to any one of claims 1 to 7, comprising the following steps:
s1, the main control system sends a control command to the FPGA module;
s2, judging that the main control system is in communication interaction with an upper module or a lower module in the FPGA module according to the FPGA address information in the control command;
s3, performing read-write operation through the upper module dual-port RAM or the lower module dual-port RAM according to the control command;
s4, the main control system executes the write memory, sets the write completion flag of the main control system, and triggers the CPU module to read and interrupt; the main control system finishes the execution of writing the memory, executes the CPU module to read the memory, sets a CPU module read completion mark and clears the CPU module read interruption;
s5, the CPU module executes the write memory, sets the write completion flag of the CPU module, and triggers the main control system to read and interrupt; and the CPU module finishes the execution of the write memory, executes the main control system to read the memory, sets a main control system read completion mark and clears the main control system read interruption.
9. The method for reading from and writing to a dual port RAM system based on an FPGA of claim 8,
and the main control system sends the control command to the first ISA interface module and the second ISA interface module of the FPGA module through the first ISA bus and the second ISA bus.
10. The method for reading from and writing to a dual port RAM system based on an FPGA of claim 9,
and the first ISA interface module or the second ISA interface module analyzes the read operation time sequence and the write operation time sequence in the control command and converts the read operation time sequence and the write operation time sequence into read-write operation on the double-port RAM of the upper module or the double-port RAM of the lower module.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119419A (en) * | 2006-08-01 | 2008-02-06 | 中兴通讯股份有限公司 | Method for implementing conference telephone |
| CN201673402U (en) * | 2010-06-13 | 2010-12-15 | 北京国电智深控制技术有限公司 | Controller of decentralized control system |
| JP2011187003A (en) * | 2010-03-11 | 2011-09-22 | Renesas Electronics Corp | Interface circuit and reconfigurable integrated circuit device |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN105681783A (en) * | 2016-01-14 | 2016-06-15 | 西安电子科技大学 | Design method for audio and video data acquisition interface circuit |
| CN105700849A (en) * | 2016-02-25 | 2016-06-22 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio acquisition based on FPGA |
| WO2018120243A1 (en) * | 2016-12-31 | 2018-07-05 | 深圳配天智能技术研究院有限公司 | Digital control system based on field-programmable gate array, and data transmission method thereof |
-
2021
- 2021-10-15 CN CN202111202827.7A patent/CN113946524A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119419A (en) * | 2006-08-01 | 2008-02-06 | 中兴通讯股份有限公司 | Method for implementing conference telephone |
| JP2011187003A (en) * | 2010-03-11 | 2011-09-22 | Renesas Electronics Corp | Interface circuit and reconfigurable integrated circuit device |
| CN201673402U (en) * | 2010-06-13 | 2010-12-15 | 北京国电智深控制技术有限公司 | Controller of decentralized control system |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN105681783A (en) * | 2016-01-14 | 2016-06-15 | 西安电子科技大学 | Design method for audio and video data acquisition interface circuit |
| CN105700849A (en) * | 2016-02-25 | 2016-06-22 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio acquisition based on FPGA |
| WO2018120243A1 (en) * | 2016-12-31 | 2018-07-05 | 深圳配天智能技术研究院有限公司 | Digital control system based on field-programmable gate array, and data transmission method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 张毅凯等: ""基于PCI总线的双通道数据采集系统"", 《通信技术》, pages 57 - 59 * |
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