SU441858A1 - Numerical programme-control digital device - Google Patents

Description

The invention is referred to the field of automation unitary enterprise () avlenp by contour movement of the working parts of automatic devices and 1 is intended for use in systems of numerical programming 4ipaB, ieiiiiH.

l1: (BCCi; i) digital iipoipaxjMHoro numeric control devices, content 6; ioK vol 1 –a) connected to a block; a1, lei and input, the output of which is connected to the) tip. and to the corresponding outputs of the buffer nozzle, the connected operational registers and the calculator, the machine control unit, the controlled generator and the automatic process unit, the input control unit, the operational registers, the calculator and the controlled generator are also connected to the control panel. ,

The proposed device is distinguished by the fact that it has a program control unit, a command control unit, a priori scheme and a computational results control circuit, and a buffer storage, operational registers and a calculator are made in the form of a single magnetic matrix accumulator with both spikes.

At the same time, the groups of address buses matrix storage devices corresponding to the buffer drive, operating registers and calculator are connected via address decoders and pulsed current drivers to the corresponding outputs of the command control units and the control unit by the program, other output 1 | which are connected to the inputs of the control unit vgyu.aom,

control panel, machine drive control circuits, result control, computation, and priority control circuits. The inputs of the program control block are connected to the corresponding outputs of the control block of the command, the calculation result control circuit, the control panel and the priority circuit. Bit and; ini matrix accumulator through amplifiers and keys are connected to the regeneration register, the circuit controlling the results of the calculations, controlled by the generator and the unit of technological automatic machines.

In addition, the priority scheme has two-point and three-position keys, regeneration cores of key states and pulse current drivers. Winding 1

the readings of the on-off and three-on-off switches are connected to the windings of the recording of regeneration cores, the read-out windings of the pulsed current formers and the reset windings of the keys are included in the readout circuit.

This reduces the amount of hardware used, simplifies the device and increases its reliability.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - priority scheme.

The functional diagram contains a magnetic matrix accumulator 1, consisting of a buffer storage unit 2, an operational storage unit 3, a functional part 4; the decoder 5 of the address of the buffer storage unit, the decoder, 6 addresses of the operative storage unit, pulse current drivers 7, playback amplifiers 8, keys 9, regeneration register 10, calculation results control circuit 11, controllable generator 12, technological machines 13, circuit 14 priority, input control unit 15, program control unit 16, command control unit 17, address registers 18 and 19, control panel 20, machine drive control unit 21.

The priority scheme includes the cores 22 and 23 with the windings 24 and 25 forming the two-position key, the cores 26 and 27 with the windings 28 and 29 forming the second two-position key; key, cores 30, 31 and 32 with windings 33, 34 and 35, forming a three-position key, current formers 36 and 37, regeneration cores 38-44, diode nodes 45 and 46, cores 47, 48 and 49 output formers, diode nodes. you are 50 and 51, output shapers 52.

The device works as follows.

The start is made by the current pulse coming from the console 20 to the input 53 of the block 16. As a rule, the control unit begins to function, carried out a program for transmitting information from block 2 to block 3. This program of the PCO g is sent in the form of G1. The steps of the commands initiated at output 54 of block 16 correspond to each command of the address information received at the inputs (|) of raters 6 and 5. of registers 18 and 19. Following the next command, block 17 at exit 55 excites the end signal, c. Your request for the next command from the second unit is 16. Any of the executed commands is to excite the appropriate controllers from the outputs 56 of the block 17. These signals, in the form of current pulses, provide excitation of the decoupler 5) (reading and writing block 2); dei1ffratora 6 (Scrapes apie and write block 3); transfer of the address from register 19 or 18 to decryptor 6; the excitation of the angles of their input, s, of the drivers of 7, providing impulses of different amplitude and polarity, in the obiM case, one-time in the address ipsh of several cells of the functional part 4 of the accumulator.

Depending on the amplitude and polarity of the address current in the address bus of the cell

RH performs one or another logical operation on all bits of the word stored in this cell and the word that enters the digit bus of the record. When this. M in time with the reading of the functional part can

J be carried out. Or the reading of one cell by the current pulse -I, which corresponds to the appearance of the signal at the input of the amplifier 8 i-ro bit a (one bit stored in the word line), or the reading of one cell of pulse m +1, that

0 corresponds to the appearance of signals at the input of the amplifier i-ro bit a,. 1 for reading two simultaneously., Gokalp cells; -I. which corresponds to the student’s} sisha.Yuv at the entrance of the force, - | i-ro bit and a i v and with 1.2no. meter read. my cell), or read

S two cells by currents, which corresponds to a} v a I, or, finally, simultaneously reading one cell by current, and another 1 × G1 J. That corresponds to output c-nrna. V and i- Pos.-1disy from operapp c.ic; iyeT

0 p. 1 zoBat. .Ini provided that

 l and

- 0.

In the beat of the record in the free code, the player can conduct1) sya and .Ill the recording with iipe.Uia is the usual1 | . I1cm chip (ga1eniemi1, which corresponds to the state of the heart of the i-th bit after bf (b ;, is the value of the binary bit of the syuva coming through the bit write buses)., n.ni for 1п1сь without preliminary reading of 1П1н, which corresponds to () core.

or recording under addressing current, early -I. That the state of the core corresponds after recording a-l. All the listed functions per recording can be performed at the same time 1) 0 in.: The number of cells with the right combination of: c) iie5 radios in different cells. TaKoii, on the other hand, a set of logical operations can be performed in addresses n and c. ) work; Pakoppte.t with a coefficient of bi-cientome selection equal to -3.

Impulses from the output of usi.chitel i;) i nimoP1Ik / pochy 9 commutici MOiXi yudar,;: i;, with

0

on different yyuki or l.) the inputs of the same block. Odip from keys, excite pz11 (from block 7 on exit 56 in the case of performing the operation of sdr.iga words paodin bit R.le5 I, provision of a connection of the output usi ..1 i-ro bit to the input of the preparatory register 10 (i -) th bit

1 {alpchne function. A full lUi selection of logical operations in the functional part 4 lines, as well as a shift key operation and using a switching key, allows performing any logical or computational operation in the proposed device, expressing the algorithm for its execution through elementary operations. Of the possible computational operations, the command list contains the commands for addition, subtraction, addition of units, subtraction of units, multiplication by ten, and others.

In order to speed up operations such as a shift, one of the switching keys connects the outputs of the amplifier to the read inputs of the register 10 bits by means of a decrease in the current pulse at the output of this amplifier. Such a switch with the presence of the write driver (i + 0th bit from the i-bit driver in the register allows the addition operation with through transfer between the bits). The pulses of the recording drivers that start from each other are written to one of the cells are the word corresponding to the shifts in the i-th bit. The current pulse in the address bus of this cell has a duration greater than the sum of the natural delays from the discharge. to the discharge and the duration of the discharge bit pulse.

Any of the commands is as follows. Word or words from cells of block 2 or 3 are written into cells of functional part 4. The addresses of these cells are previously entered from output 57 of block 16 into decoders 5 and 6, registers 18 and 19, the entered information is converted into functional parts according to the algorithm corresponding to this command and expressed through the mentioned electronic operations.

The sequence of control signals necessary for the execution of this algorithm is provided by block 17 on output 56.

The result of the execution of the command is transmitted by block 3 or 2 to the result cell in accordance with the address of the cell indicated by block 16.

By removing the transfer from block 2 to block 3 in the manner described above, and revealing the characteristic features of the subsequent programs (according to the phrase information transmitted from block 2), block 16 provides the setting of the priority circuit 14 at input 58 in the output code corresponding to either equi-stantniglu or non-equidistant contour control. In addition, on output 59, block 16 sends a start signal to program carrier 60 to block 15. At this time, the start of working out of block 2 phrases is crossed with input to block 2 of the next fraction.

The development of a phrase, the input of the next phrase with the conversion of a decimal code into a binary one and the determination of coordinates of an equidistant contour are carried out in the mode

the separation of BpeMeiiii between the indicated users using priority scheme I.

At the input 61 of the priority circuit, from block 15, the signals are sent to execute the program for transmitting the next line, received from the program of the mono carrier, to block 2.

In the case of transmitting numerical information, for example, increments, the transfer of lines of the same word is carried out according to a program that also translates a decimal code into a binary one. The value of the line itself transmitted to block 2 is output 62 from block 15 as a result of a read pulse from output 59 of block 16.

At input 63 of the priority circuit, the signal is sent from generator 12 to a request for executing the program for determining the coordinate, which needs to be followed by its elementary movement, i.e. the next step. The frequency of the steps, and hence the linear speed of movement, depends on the frequency of the generator, since the appearance of a pulse at the input 64 of the machine drive control unit 21 corresponds to an elementary movement along one of the coordinates. For exactly which of the coordinates you need to do uiar, determines the spgnal from the output of 65 b. Yuka 16, I will make the cut, first perform; and one-step calculation programs {in the number, for example, the calculation of the estimated function).

In addition to calculating the evaluation functions stored in certain cells of block 3, in the same program of the step, the current coordinate value is calculated (cell definition, and control calculations to determine the end of the phrase development) by the values of given values. The frequency of the steps, also the frequency of the generator 12, is determined by the number received by the amplifier 8 from the amplifier 8 through the corresponding switch key during the transmission of the phrase information from block 2 to block 3. In addition, due to the change in the frequency of the generator, it is possible to effect the output from 66 fmta 20. The signal from the output 67 of the drive control circuit 21 enters the drive flock (according to the corresponding coordinates), as well as the feedback signal to the generator input in order to stabilize the set speed at various angles womb obrabatyvae.mogo circuit.

The execution of the equidistant contact program is carried out in all time intervals that are free of the two programs indicated, up to the end of the decomposition of the tool radius (R) into two components of the vector. The end of this decomposition corresponds to the appearance of the reset signal of the equidistant loop calculation program supplied through. input 58 to circuit 14 from block 16. The value of R-, necessary to control the end of decomposition R, is fed to block 3 from block 15 from output 62, and to block 15 comes from output 68 of the console 20.

The end of any of the programs mentioned above is accompanied by a program ending signal going to input 6.9 of circuit 14 of block 16. After the signal to input 69 is transmitted, the priority circuit depends on the request signals (inputs 61, 63), on the set priority, and on the set mode of operation (input 58) generates a signal in block 16 on the beginning of the execution of one of the programs. Input 70.

The branching within the programs, depending on the results of the calculation, is carried out using the control circuit 11. Information from the amplifier outputs through the corresponding switching keys 9 is fed to the input of this circuit. This is the number and information on the meaning of the sign bit. On output 71, block 16 excites the circuit. 11 control in case of branching on this program. The control information (in response to the signal from output 71) is fed to the input 72 of block 16.

The function of the control circuit also includes ensuring the execution of programs for inputting the value of R from the console 20 to block 3; input from the number of leads to the end of working out the phrase corresponding to the output of the Signal, pacing - braking to the new speed value at the end of the next phrase, as well as the program for emergency withdrawal of the tool in case of a failure.

All iipoi frames are executed without the participation of the circuit. 14 priorities, as with the use of | 1OLg; e11II any of them there is in principle no need to work on a different program.

In the priority scheme, the key on the cores 22 and 23 stores information about the presence of a request for a program to transfer a line from block 15 to block 2. The request comes in the form of a current pulse at input 73.

The key on the cores 30, 31 and 32 stores information about the mode of operation of the priority scheme. If the circuit containing the winding 33 has the most conductivity, then a calculation of the equidistant contour is required. When the circuit with winding 34 has the greatest conductivity, no calculation of the equidistant loop is required. If the highest conductivity is observed on a circuit with a winding 35, then the priority circuit is in an idle state (there are no signals at outputs 74). The magnetization of the core 32 in the direction corresponding to the low impedance of its read winding is conducted by the signal of the end of the phrase processing, as well as by the signal of the initial installation.

The key adjustment on the cores 30, 31 and 32 in one of the two operating modes is carried out via tuning inputs 75. The current pulse passing to input 75 and on the winding of mounting the cores 30.31 and 32 corresponds to the end of decomposition of the instrument radius into two parts vectors, after which the calculations of the coordinates of the equidistant contour are read as terminated.

In the event that the calculator finishes the next program on the input 76 of the training

current driver 36 receives a current pulse in an odd-m clock cycle. In an even beat, the driver generates, as a result of which the driver 37 is prepared according to the state of the cores 22-32

writing to the cores 38 and 39 is carried out. In the output of the current pulse pulse of the imaging unit 36 passing through one of the diodes of the node 45 and one of the diodes of the node 46, writing is performed to one of the cores 38-41 and to one of the cores 42, 43

and 44.

The next odd clock triggers the phantom 37, as a result of which the cores 22--32 and the cores 47, 48 and 49 of the output shapers 52 are installed. The current pulse from the shaper 37 passes through one of the four diodes of the node 50 and one of the three diodes of the node 51 At the same time, depending on the availability of zagfos; in6o, none of the cores 47, 48 and 49, or only one

of them. Since the first queue in this scheme is given to block 15, the key 37 on the cores 22 and 23 is always provided by Hviny.ib on the former 37 if the DJB performs a request on the cores 26 and 27 if there is a request from the generator; 1 and

Since the calculation of the equidiation loop is carried out only at a free time (without requests), the key reset on the cores 30, 31 and 32 can be ignited by the pulse at the input 75.

In the next even clock, the readout of the 77 output drivers and the signal about the beginning of the next program to the block 16 comes from the outputs 74. In order not to lose the request (the odd clock), randomly coinciding with the pulse of the driver 37, the write windings on the cores with the windings 22-32 from inputs 78, 73 and 75 are made with a predominance of MDS in comparison with the windings of the record on these cores in the circuit of the imager 37.

Claims (2)

1. A digital numerical control device containing a program input unit connected to an input control unit, the output of which is connected to a buffer store, and corresponding to CTBViouiHM along the 11pod buffer paths: - 1ts: 1I am connected 1 | and B1) 1 numerator, drive unit gaggle. a controlled generator and a unit of technological automata, the control unit of the house, operational registers, computing the body and the controlled generator connected to a control panel, characterized in that, in order to save equipment and improve the reliability of the device, it contains the control unit of the program, the control unit of the command, the priority priority circuit and the control circuit of the calculation results, and the buffer storage, operational registers and the calculator are compiled as a single magnetic matrix storage device with mini-MH-type busbars m tiered address matrices .1 corresponding to the buffer drive, operational registers and calculator tiepcs address decoders and pulse and pulsators (current rotors are associated with the corresponding outputs of the command control blocks and the program control block, the other outputs of which connected to the inputs of the first control input, the control of the control panel, the skiller pilGlcHi: i machine, cxMi) i ./1 1ezultat) in the calculations, tenium and cxi.my I1:) ior gheget; BXO.UJ b.yuk program management sv. Chy with the corresponding output of the control unit block command, the scheme of control of the results of calculations, the control unit and the priority scheme; The bit busses of the matrix accumulator through amplifiers and keys of the hypersdimony i to the register of j egeyeration, the circuit of the comp. res.; computation of computations, traces of the displacement of the circuit;) and blockch technological; X avtol; and Comrade 2. The device according to i. , or. (C.-i so that. with the aim of ynpoJueiiiiH is hstrostn ;; and iovileyii ep; n;.:;, uniost1-. scheme with: riteta sodezhptt two 1103;:; | about 1n; - ;; perenci:; scientific research institute of state; I of keys, and. e 4) C) :: mg rovate, P1 current; region; arrays,; .. from the positional and GRSP; PCSPP: yoke key no.:i SOSDINSN; OOOGKZM;) Sili; Ci; SerDSCHP i. regeneration, in; e ;; obyotk ;; .jniiici; and:.; :: pulse; s ibopirozatslsy Tf; K; i; Shredding JviH Whose. Y