SU542995A1 - Device for modifying commands - Google Patents

Description

The invention relates to computing, in particular to devices for modifying instructions and can be used in the construction of control devices for digital computers. A device for modification is known comprising an index register, AND elements, an arithmetic register, an address information switch, an operand address decoder register, and an operation decoder. It is characterized by the presence of a special register of the address of the operand with complex connections with other blocks, and the modification can follow only part of the bits of one half of the command word, which leads to an increase in the cost of the equipment. The closest to the invention in terms of technical sushi and the achieved result is a device for modifying a comaid containing an operational and tactical unit whose discharge outputs are connected to the first inputs of the elements of the first and second groups, the arithmetic logic unit whose outputs are connected with the bit inputs of the block by the operative of it, the control block, whose inputs are connected to the outputs of the PI elements of the first row, the first, second and third outputs are connected respectively to the second inputs of the AND elements of the first group, the second inputs of the elemey group of the second group and with the control input of the arithmetic logic unit, whose inputs are connected to the outputs of the elements of the second group, the first group of address inputs of the operational unit is connected to the main inputs of the device, and the memory memory module contains the address register, the decoder , current drivers and the first group of cells whose address inputs are connected via serially connected current drivers, a decoder and address register with the first group of address inputs of the operational memory block m. In this known device, the presence of a single address path, both when referring to cells of stored information, and when referring to cells, as well as the functions of the Yandex.And registers, leads to a decrease in the speed of the device and its complexity. The purpose of the invented - the increase in speed and simplification of the scheme. In the described device, this is achieved by the fact that in it the group of outputs of the control unit is connected to the second group of address inputs of the operative type block, which contains the second grunyu cells and reverse current drivers, and the second ground address inputs of the operative block are connected to us via reverse current current drivers connected to the address inputs of the second group of cells, the bit inputs and outputs of which are connected respectively to the bit outputs of the first ground of the cells of the memory unit and the bit outputs of the block erativnoy memory.

The drawing shows the block diagram of the described device.

It contains a block of 1 RAM, block 2 controls, groups 3, 4 elements And, arithmetic logic unit 5; the memory unit contains the address register 6, the decoder 7, current drivers 8, groups

9.10 cells, reversible current drivers 11, groups 12, 13 address inputs, bit inputs 14, bit outputs 15; the control input of the arithmetic logic unit is input 16.

When selecting a command from a group of 9 cells, the signals at outputs 15 of block 1 appear, which pass through a group of 3 elements AND to a group of inputs of control unit 2. In block 2, the command code is analyzed and clarified whether modification is required. If the command needs to be modified, then control block 2 starts the corresponding driver 11, and the command is recorded in a group of 10 cells. At the same time, the selected team is regenerated in a group of 9 cells.

In one of the cells of group 10, the value of the modifier is stored, which is entered there in advance by running at the right time one of the drivers of the modifier 11 that records the modifier. The number of steps or the number of commands to be modified is stored in one of the cells of group 10.

Further work is performed according to the following algorithm. In odd cycles, odd-numbered generators 11 are alternately excited and the contents of the cells that store the modifier and the modifiable command are transmitted through a group of 4 elements AND to the inputs of the arithmetic unit 5, where they are added. When the contents of the modifier cell are transferred in an even cycle, the modifier is regenerated, for which the corresponding write driver 11 generates an address write current. Regeneration of the modifiable command cell does not occur. The result of the addition comes from the arithmetic logic unit 5 to the bit inputs 14 of the operational memory block and can be sent to one of the cells of group 9 if immediate modification of the modified command is not required, or recorded again.

10. It depends on the operation algorithm of the control unit 2. Then, the arithmetic logic unit 5 enters the contents of the cell storing the number of steps, and one is subtracted from it. If the result of the subtraction is zero, then the arithmetical-logic unit 5 generates a signal that the modification is completed.

Thus, any zero in the word of a command or several fields simultaneously can be modified depending on

what number is entered in the modifier cell.

For execution, the modifiable command is selected from the corresponding cell of group 10 according to the signals of control unit 2. If the modification is made in advance, then the modified team is selected from the ground of 9 cells in the same way as the other teams.

Conducting a modification of the firmware command allows the advantages of indexing using hardware registers to be combined with saving equipment and increasing homogeneity, which is especially effective for processors on homogeneous magnetic matrices. The modification of the command in the invention requires an additional three units of automaton time, while during the update via the registers connected to the common decoder, 12 micro-tacts are required for the microprogram modification of the commands.

Claims (1)

Invention Formula A device for modifying commands containing a block of RAM, the bit outputs of which are connected to the first inputs of the AND elements of the first and second groups, an arithmetic logic unit, the outputs of which are connected to the bit inputs of the RAM, the control unit whose inputs are connected to the outputs of the elements And the first soil, the first, second and third outputs are connected respectively to the second inputs of the elements AND of the first group, with the second inputs of the elements Both the second group and the control input of the arithmetic logic unit, whose inputs are connected to the outputs of the elements And the second group, the first group of address inputs of the operative memory block is connected to the soil inputs of the device, and the operative block of us contains the address register, decoder, drivers currents and the nerve cell group, the address inputs of which are connected via serially connected current drivers, a decoder and an address register with the first group of address inputs of the RAM block, characterized in that, in order to improve the speed and simplicity of the device, the output block of the control block connected to the second group of address inputs of the memory block, which contains the second group cells and reversible current drivers, the second group of address inputs of the RAM block through reversible current drivers connected to the address inputs of the second group of cells, the bit inputs and outputs of which are connected respectively to the bit outputs of the first group of memory cell and the bit outputs memory block.