SU1561073A1 - Apparatus for preliminary sampling of commands - Google Patents

Abstract

The proposed device is expediently used in processors, the architecture of which assumes the use of a buffer memory, the pipeline execution of instructions. The application of the proposed device is most effective if a significant number of one-step commands are used in the processor software. The goal is to increase the device speed by providing a constant load of the device command buffer, which is continuously swapped from the trunk side and information is downloaded at the request of the processor. The command preselection device comprises a request generation unit, a request matching unit, a register unit, a reading node, a recording node, a loading control node. 2 hp ff, 4 ill.

Description

The invention relates to computing and can be used in processors, the architecture of which involves the use of a buffer memory, pipeline execution of commands.

The aim of the invention is to improve the speed of the device.

Figure 1 presents an example implementation of an electronic computer that includes this device; FIG. 2 is a functional diagram of the prefetch device of the command FIG. 3 — functional diagram of the account management node; 4 is a functional diagram of the device occupancy analysis node; FIG. 5 is a timing diagram of a processor pulse train.

The electronic computer, which explains the application area of the device (Fig. 1), contains a pre-selection device 1, a processor 2, information input 3, random access memory 4, a system backbone 5, a second information output of a buffer command memory block 6, a block firmware control 7, the first information output of the buffer memory block of commands 8, the internal backbone of the processor 9.

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The device 1 contains (FIG. 2) a query generation unit 10, a query matching unit 11, a register unit 12, a recording unit 13, a reading unit 14 and a load control unit 15 (command address counter, SpAC), a read output of the command 16, a query generation unit Inputs 17 and 18, respectively, of reading and writing the operad of the device, output 19 of the initialization attribute of the device request, output 20 of the write write block recording, output 21 of stating the query generation block, inputs 22 of the register block, input 23 of the mode of operation of the register block, end 24 exchange request matching lock, output 25 of the read information blocking attribute of the device, read sign 26 of the operand of the device, write output sign 27 of the device operand, n1 inputs 281-28 + device information read input 29, device request control input 29, device enable permission inputs 30, input 3I blocking the device request, output 32 of the block of the load control block, output 33 of the zero block of the load control block, p-bit control counter 34, adder 35, account control node 36, occupancy analysis node 37 device, the element And 39, elements AND-NOT 40 and 41, the fourth trigger 42, the input 38 sign of fullness of the block of registers. In this case, node 36 (FIG. 3) contains a generator 43, a p-bit counter 44, a decipher, a torus 45, elements AND-OR-NOT 46, OR 4 and-OR 48 o

Node 37 (Fig. 04) contains p-bit decoder 49, comparison circuit 50, AND-OR element 51, OR group, output 53 (interlocking output 53 In addition, device 1 contains registers 54, port control inputs B, inputs port control C, trigger 57, element AND-HE 58, input. 59 gating devices, p-bit counter 60, decoder 61, group of buffer registers 62-62, elements AND, AND-OR

 b41-64p, OR 651-65p 1 and the third

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trigger 66, sixth through eighth

triggers 67-70, fifth, tenth, eleventh triggers 71-73, AND elements

74, and 75-75

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And 761-76e

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and the elements OR 77, AND-NOT 78, the first trigger 81, the element OR 82, the element AND 83, the element AND-NOT 84.

A command prefetch device 1 (FIG. 1) is included in processor 2.

In device 1, information input 3 receives the command code from system RAM 4 via bus 5. From information output 6 of device 1, information enters the firmware control unit (CPU) 7 of processor 2. From information output 8, information arrives on the internal bus 9 of processor 2.

Block 10 is intended to form a request to read the command code from the system RAM 4.

Output 16 of block 10 receives a request to read the command code. Vkod 16 is connected to the input 16 of block 11, to the inputs 17 and 18 of which receive requests for trunk 5 from the microcommand to read or write the operand, respectively.

Block 11 is designed to match the request from block 10 with requests from processor 2. At output 19 of block 11, a command initialization signal is generated for trunk 5. Output 19 is connected to input 59 of circuit 133 that generates a signal for writing the command code to block 12 via input 3, which It is an informational input 3 of CB11 1. The recording signal arrives

to input 20 of block 120 I

The output 21 of the block 10 is connected to the input 21 of the circuit 14, the group of outputs 22 and the output 23 of which are connected to the groups of control inputs 22 and the control input 23 of block 12. At inputs 22 and 23, signals are received to output information from the registers of block 12 in the BMU 7 through a group of outputs 6 or onto a bus 9 through a group of outputs 8 o. The groups of outputs 6 and 8 of block 12 are information outputs of device b. Block 12 is intended for temporary storage of a command code.

From the output 24 of the block 1I to the input 24 of the block 10 receives a signal characterizing the end of the exchange on the highway 5 from the request to read the command. The output 25 of unit 10 and the outputs 19, 26, and 27 of unit 11 are outputs 19, 25-27 of the FECD 1. From the exits 19, 26, and 27, there are requests originating from

line 5, respectively, reading the command and operand, write operand. Output 25 receives a blocking signal for the processor 2 clock frequency.

On the group of control inputs 28 28 of the block 10 and the circuit 14, on the input

29 of block 10 and inputs 30 and 31 of node 15 receive control signals from the field of microcommands, to control input

28 - signal from BMU 7. Node 15 is designed to generate control signals for operation of unit 10 and nodes 14 and 13 in the event of a processor 2 reset. From the output 32 of the node 15 to the input 32 of the unit 10 a blocking signal is received. From the output 33 of the node 15 a signal is received zeroing at the inputs 33 of block 10 and nodes 13 and 14.

The node 36 has a group of inputs 28-28 and +, which are the inputs of block 10. The output of node 36 is connected to the counting input of the counter 34 operating on the subtraction, and is the output 21 of block 10. The inputs D1-DR of the counter 34 are connected to the outputs of the adder 35 The inputs A1-AP of which are connected to the outputs Q1-QP of the counter 34, and the inputs B1-BP are connected to the circuit 38. The circuit 38 sets a constant number, for example the number n, the bit size of which is less than p in the binary code. The set number n is added in the adder 35 with the contents of the Y counter 34.

The counter size p of the counter 34 is determined by the maximum number 2 p. This statement will be explained later.

Input 24 of block 10 through the element AND-NOT 40 is connected to the write enable input of the counter 34.

Thus, the change in the content of the counter 34 occurs under the action of a signal at the input 24. The reset of the counter 34 occurs at the input R by a signal from the node 15 to the input 33.

The node 37 analyzes the information on the outputs Q1-QP of the counter 34. From the result of the analysis, the first output of the node 37 generates a request to read the command from the system's RAM 4, through the AND 39 element, to output 16 of the block 100. At the second output of the node 37 signal captured by trigger 42 "

The contents of the counter 34 is supplied to the p inputs of the decoder 49 and p

the inputs of the comparison circuit 5 (J, to the other input of which the node 38 receives the set number n in binary code of the size p ". The inverse output of the comparison circuit 50, which is the first output 53 of the node 37, is connected to the input of the AND element 39 of the block 10. At the output comparison circuit 50 appears

3 signal 1, if the value of y from counter 34 in binary code does not exceed the threshold set by node 38 in Section 12 (FIG. 6) is intended for temporary storage of a command code. Block 12

5 contains 2 n K-bit buffer registers 54; Recording from trunk 5 is performed simultaneously in n registers 54 through AI-An ports. Information in registers 54-54 comes from information input 3. Since nq each port A receives K information bits, the width of highway 5 must be at least Km.

Record management is done

5 at the entrance 20. Register level control 54-5411 at the address XO or X1 is produced by a signal from input 20g. Inputs 20 and 202 are the control input 20 of block 12 connected to the output of circuit 13.

Information is output from the B1-VP ports to the internal bus 9 of the processor 2. Information output is possible both from one port B, and simultaneously from all B1-VP. Therefore, the bus width 9 should not be less than K-p0. Information output from ports C1-SP is made in BMU 7 and is possible only from one port C. Routes 6-6 are united by mounting OR and are information output 6 of FECD 1. When reading information, the selection of the port number is made for ports В1-В „through the inputs 55 -55, for

from ports C1-SP - to the inputs 56 -56. Inputs 551-55p and 5b -56p are groups of control inputs 22 of block 12 connected to the outputs of node 14. Read pointer from registers

0 О or 1 level on ports В1-ВП, С1-С is connected to control input 23 of block 12 connected to output 23 of node 14.

Node 13 (Fig. 7) contains a trigger 57 operating on a front, an AND-HE element 58. Resetting the flip-flop 57 is performed via an R input from the output 33 of the node 15, the First input of the IS-NE 58 is connected to the output 19 of block 11, and second

its input is the control magician through the wrong input 59. At input 59, a strobe signal arrives, subject to the reliability of the information on the highway 5.

The output 201 of the element 58 and the direct output 20a of the trigger 57 are the output 20 of the node 13.

Node 14 (Fig. 8) is designed to generate read signals when outputting information from block 12.

Triggers 67-69 (Fig „9) pre-memorize requests for trunk 5 - reading a command from block 10 to input 16 of block 11, reading OR writing an operand from a microcommand to inputs 17 and 18.

The trigger 70 captures the end of the exchange on the highway 5. The signal end of the exchange is fed to the input 79.

In addition, for the correct use of block 11, the additional elements OR 77 and AND-NE 78 are introduced. From output 80, a signal is generated that forms the mode of operation on highway 5, reading. The output connects to the multiplexer of the HEAT condition 7. Therefore, before generating a new request for trunk 5, processor 2 can determine whether its previous request has served on output 80 if the previous request has not yet been served, since trunk 5 has been read commands, processor 2 is about to wait. Resetting triggers 67-69 is performed from the input. Resetting the initial installation of processor 2. Node 15 contains a trigger 81 operating on the front, and the elements OR 82, AND 83, AND-NE 84.

For the operation of the blocks and nodes (Fig. 2-4) of the device 1, as well as the processor 2, a clock sequence of pulses T1 and T2 is used, the time diagram of which is presented in Fig.5. Frequency fn is the reference frequency.

The device works as follows

Let at the initial moment of time after turning on the power to the input the Reset of the block 11 and the node 15 comes. set signal zero. The triggers 67-69 of block 11 are set to state zero, m0. There are no requests for trunk 5. The trigger 81 of node 15 is set to

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The signal O from the output 32 of the node 15 is fed to the input 32 of the block 10, and then to the blocking input of the element. And 39. From the output 16 of the block 10, a request to read a command from the system RAM 4 is not generated. Then from the microcommand to the input 30 of the node 15 a signal 1 is received, which controls the loading of SCAC0. By the signal T2 from the output 33, the counter 34 of the block 10, the triggers 57 of the circuits 13 and 60, 66 of the node 14 are reset. reading command. This signal is produced at the output of the comparison circuit 50. If the contents of the counter 34 has the value Oi and n, then the output of the comparison circuit 50 is signal 1. Positive drop of the T1 clock trigger 81 of the node 15 is set to one at the end of the clock cycle. At output 16 of block 10, a signal 1 is generated, which passes through element 74 of block 11, clocked by the same signal T1, and at the end of this clock is fixed by trigger 67. At the beginning of the next clock through element 75, the request is fixed by RS trigger 71. At output 19 of block 11 a signal is generated that initializes the reading of the command on line 5.

At output 202 of block 13 there is a signal O, therefore the pointer of the address for registers 54 / | -54p of block 12 - X0. The signal of record O into these registers at ports A1-AP is formed with the arrival of signal 1 at input 59 of block 13, which characterizes the transmission reliability information on the highway 5.. With its arrival, information from highway 5 to the inputs 3 -3n is written to the registers. At the end of the signal exchange 1 at the input 59 is removed, the trigger 57 on the positive differential is set to one. The pointer of the address level of the registers 54 of block 12 to the ports A1-LP becomes XI, and the next entry of the command code will be made to these registers.

The positive differential coming to the input 79 of block 11, characterizes the end of the exchange on the highway 5. Let the arrival of this differential be clocked by the middle of the clock. Trigger 70 is set to one. At output 76, signal 1 appears, which at the end of a given clock cycle, signal O arrives at the W input of counter 34.

Under the action of this signal, the content of the adder 35 is recorded in the counter 34, in this case Y 0, then the number 34 is recorded in the counter 34. The node 37 analyzes the contents of the counter 34. At the output of the comparison circuit 50 the signal 1 reappears, which goes to The input 16 of the block 11 is written to the counter 34 during the time T1, so the first half-cycle of the next clock trigger 70 is set to zero. By a positive differential on the C input, trigger 67, and then trigger 71, on the R input, are zeroed. The lock on the input And 74 is removed. At the end of this clock cycle, the trigger 67 is set to one again, and at the beginning of the next clock cycle, a request is initialized to the highway 5 for reading the command code. The maximum number recorded in counter 34 is 2n, the bit of which in the binary system p.

If, when loading SCA, under the action of a control signal from a micro command (signal 1 at input 30), its contents were A, then at the end of the exchange from output 24 of block 11, a signal appears that changes the content of SCAC to A + n. Thus when reading the command code in the registers 54 of the VK 12, the SCCA automatically increases by the number of ps. Under the action of the signals received at the inputs of the device 1, the registers of block 12 are read. Under the influence of the signals from the inputs 28-2811, the information is output to the bus 9 , from input 28ГН1 ( channeling signal from the BMU 7) - in the BMU 7.

The signals from the inputs 28 - 28h characterize the number of registers 54 BC 12 simultaneously read by ports B1-BP. Under the action of the signal from input 28, one register 54 is read, under the action of 28, two registers 54 and so on at the same time, under the action of 28 - n registers 54. Under the action of the signal from input 28, one register 54 is always read from ports C1-SP

Using a signal at input 28, processor 2 reads the operation code

61073Y

a rare command in the BMU 7, where the starting address of the microcommand for processing this command is formed. In most cases, the command is executed.

5 per processor cycle 2, i.e. for one microinstruction. In the selected microcommand, the number of registers 54 can be indicated by the signals at the inputs 28-28p that need to be read onto bus 9 (reading the remainder of the command, for example, the immediate operand), in order to execute the command of the specified format. After upload

jtj SCA trigger 60 reset. At output 1 of the decoder 61 - signal 1. The recording of signals in registers 62-62 is happening. Dit on the end of the stroke T1. In this case, the read address pointer with

20 ports В1-В |, or С1-СП come from register 621 „

The signal from the output of the trigger 66 indicates from which register level to read, In this

In the case of B1-Bp or C1-SP, the case is read from the CW level. Suppose, for example, at the beginning of a clock cycle, signal 1 came to input 28. In this case, the output of the OR elements

2Q 65, 65g - signals 1, hence, at the output of AND-OR 64.64 - also signals 1, Signals 1 are received at the control inputs 55, 55 of block 12, which allow the output of information on ports B1, B2 from the registers 54% 54 level CW.

-At the same time, the signal 1 from the input 28 enters the block 10 to the input of the node 36 and through the element AND-OR 48 includes

-0 generator 43. When signal 1 appears at the output 2 of the decoder 45, it is passed through an AND-OR-HE element 46, Signal O at the output of element 46 blocks the operation of the generator 43, i.e. with

, from the output 21 of the node 36 from the signal 28 two pulses are generated.

The generator 43 generates a sequence of pulses of the type square, the duration T2 / 2 of which is determined 5Q by the allowable duration necessary for the operation of the counters 34 of the block 10 and 60 of the circuit 14, i.e. the choice of their element base.

The two pulses generated by node 36 are fed to the subtracting counting input of counter 34. The contents of counter 34 become.

The same two pulses arrive at the input 21 of node 14 and then to the counter

60. At output 3 of decoder 61, signal 1 appears, which is written to buffer register 62 at the end of T1. The read address pointer from ports B1-B or C1-Ch is changed by the number 2. Starting from register 54 of the XO level, it is possible to read the Next command code when new signals come from the microcommand to the inputs 28-28 1f at the Beginning time. To transition the readout of information from level X1, trigger 66 serves which fixes the overflow on

TO PUCK P + COUNT 60. At. THIS POSSIBLE

4en simultaneous output of information d of several registers of one and another level.

Let us estimate the duration of the processor clock 2. Under the action of the signal from Input 28n, the generator 43 must produce n pulses during the clock, which change the contents of the counter 34 by the value of J - and are counted by the Counter 60 o In addition, at the end of this clock cycle, the counter 34 is possible Writing the number n at the end of the exchange. Therefore, by the arrival of the positive shelf taKTa T1 (FIG. 5), it is necessary for Counter 34 to switch reliably from fi pulses.

If the critical path for processing information in processor 2 is shorter than the calculated Tact duration from the sequence n of generator pulses 43, then it is possible jie to increase the clock speed of processor 2. To do this, you need to organize the processor 2 in this way, for example, at the microprogram level to get this information could process in two or more cycles

There may be cases when the need of the processor 2 in the amount of readable information is greater than what is currently available in block 12 o. For this case, the signals from inputs 28-28 + are compared with the contents of counter 34 at the beginning of the clock cycle. The output of the decoder 49 generates a signal characterizing the number of the counter 34. The AND-OR 51 element collects various combinations of signals arriving at inputs 28-28 P4 and signal Y when there is a lack of read information from block 12. At output 53 of node 37 signal 1 characterizes the lack of information in block 12. Signal 1 with

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the second output of the node 37 is fixed in the trigger 42 in the second half-cycle.

From output 25 of block 10, an O signal appears in the first half-cycle, which blocks the clock frequency of processor 2. The execution of this microcommand stops.

In order that the counter 34 does not change its state when the microinstruction is stopped, the blocking signal O is received at the input 25 of the circuit 36. The generator 43 stops. By this time, counter 44 managed to record a certain number of pulses from the signal at one of the inputs +,

At the end of the exchange on line 5, the number n at the end of the cycle is recorded in counter 34. At the beginning of the next clock cycle, the blocking signal 1 is removed at the output 25 of the block 10. The generator 43 resumes operation and reaches the required number of pulses. This microcommand on which the processor 2 has stopped is executed from

Stopping the operation of processor 2 from the signal at output 25 of block 10 impairs its performance.

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To reduce the likelihood of this signal occurring, it is necessary to create a program of operation of processor 2 as follows: to increase the frequency of the request for 5 reading the command code to the maximum (processor 2 should turn to line 5 should be much less frequent); reduce the cycle of exchange with the system RAM 4; when information is output for p clock cycles from block 12, a blocking signal should not be generated at output 25 of block 10, where. p - the number of cycles in the cycle of exchange with the RAM 4 At the end of the p-th cycle, the buffer registers 54 of the block 12 are swapped.

In block 11, requests for reading a command and from processor 2 are managed. Writing to trigger 67 occurs at the end of a cycle, writing to triggers 68, 69 - at the beginning of a cycle 5 Initializing a request to trunk 5 for reading a command is possible at the beginning, and from processor 2 - in the second half of the next bar.

A query fixed in trigger 67 blocks 75, 75 and vice versa.

If at the start of the cycle the triggers 67 and 71 are reset to the end

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exchange on trunk 5, the request recorded at the beginning of this cycle in trigger 68 or 69, in the second half of this cycle forms a request for highway 5 from processor 2. Reset triggers 68 and 72 or

69 and 73 occurs at the end of a measure. In this case, a request to read the command code may be generated at the beginning of the next clock cycle. Trigger

70fixes the end of the exchange in the second half-cycle, where this information is processed. In the first half-cycle, the trigger is reset to zero 70. The formation of the read mode on trunk 5 occurs on the signal from output 80, the recording from output 27. Information for processor 2 — whether its previous request served arrives

from the output of SO -. A request to read a coma code is formed by the hardware and is not monitored by processor 2. To firmware control the request generated at output 16 of block 10, signal 1 is used, coming from a microcommand to input 29o This signal blocks the request if no signal O is generated at output 25 of the block 10, since blocking the request when the processor 2 is stopped does not make sense, Signal 1 at input 31 sets the trigger 81 to zero and blocks the request from output 16 of block 10, as well as receiving an exchange end signal at AND 40.

Signal 1 from input 31 is active when it is necessary to unload the SCAC.

The address of the current command when executing transition commands can be calculated, since the SCAC indicates the lead address, and the offset from this address is contained in the counter 34,

At the end of the exchange, the reading of the command in the SCAC and the counter 34 is recorded

NUMBER BY

In the case of unloading, the SCAC will zero the trigger 81, the signal O from its output will block the download of the SCAC and the counter 34, as well as forming a request for

reading command.

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Then, the address of the current command is calculated in the data processing unit of processor 2. For this purpose, information should be provided from the SCAC and counter 34 to the internal bus 9 of processor 2.

Device 1 is an automaton that allows the processor 2 to combine the current command and write the next command code to the buffer registers. UPVC 1 monitors the status of the buffer registers and generates a request to read the command code, if the counter has 34 responsible for the number of occupied registers 54 of block 12, has a value of 0 6 n, FPC 1 automatically manages requests (its own and

r from processor 2) to trunk 5.

Device 1 can stop the computation of processor 2 if the need of processor 2 for command information is more than what it has

0 at the moment in block 12. Reducing the cycle of exchange with the system's RAM 4, organizing the operation of processor 2 so that, in the intervals between swapping block 12, its information consumption is less than the resource of block 12, reduces the likelihood of the processor 2 stopping.

When reloading SCAC, rebooting of block 12 is not required. In the same case, where the SCAC is loaded, the return to the zero pointer of the write-read address of block 12 is returned and the command read request is generated.

Device 1 allows the simultaneous recording of a command code into n registers 54 of block 12 in one exchange cycle

By varying the number of registers 54 in block 12, the number of simultaneously loaded and unloaded registers, it is possible to achieve a constant load of block 120

The most effective use of the proposed device is in processors, in the software of which a significant number of one-step commands are used.

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Claims (1)

Invention Formula 1 o A command preselection device containing a block of registers whose information inputs and outputs are respectively information input and output of the device, characterized in that, in order to improve the speed of the device, it contains 15 device occupation analysis node, account management node, control counter, adder, counter, decoder, first to eleventh triggers, first to ninth elements AND, first to fifth elements AND - NOT, first and second elements OR, a group of n + 1 registers (where n is the number of units of information written or read at the same time into a block of registers), a group of n elements AND, a group n -1 of OR elements and a group n of AND elements - OR, and a group of n + 1 inputs of information read characters device connected to the group n + 1 information the inputs of the account management node and the first group p + 1 information inputs of the device occupancy analysis node, the group of information outputs of the control counter is connected to the second group of information inputs of the device occupancy analysis node and the group of inputs of the first adder adder, the group of inputs of the second addend, which is connected to the group of inputs of the code of the indication of being filled with the information of the block of registers of the device, the information output of the adder is connected to the information input of the control counter, the output of the control unit the counter is connected to the subtracting input of the control counter and the summing input of the counter, the output of the first AND-NO element is connected to the enable input of the recording of the control counter, the direct output of the first trigger is connected to the first input of the first AND element and the first input of the first AND-NOT element, the second input of which connected to the first synchronization input of the device, the inverse output of the first trigger is connected to the direct input of the second NAND element, the output of which is connected to the information input of the first trigger, the synchronization input of which It is connected to the first synchronization input of the device, the output of the first element OR is connected to the input, is set to O of the first trigger, the first input of the first element OR is connected to the lock input of the device request, the enable input of the device request is connected to the inverse input of the second element NAND and to the first input the second element And, the second input of which is connected to the second synchronization input 561073 devices that sixteen ten 15 20 25 the output of the second element I is connected to the reset inputs of the control counter and the counter, with the installation inputs of the second and third triggers, the blocking output of the device occupancy analysis node is connected to the information input of the fourth trigger, the synchronization input of which is connected to the third synchronization input of the device, the inverse output of the fourth the trigger is the output of the read lock indication of the device information and is connected to the account lock input of the account management node and to the first input of the third element AND - NOT, The second input of which is connected to the control input of the device request, the output of the third element AND-NOT is connected to the second input of the first element AND, the output of the request of the device analysis node of the device is connected to the third input of the first element AND, the output of which is connected to the first input of the third element AND the input of which is connected to the first synchronization input of the device, the direct output of the fifth trigger is the output of the sign of initialization of the device request and connected to the first input of the fourth NAND element and the first input of the fourth element I5 whose output is connected to the third input of the first I-HC element and the synchronization input of the sixth trigger, the output of the third element I is connected to the installation input of the 1st sixth trigger, whose information input and informational inputs of the seventh and eighth triggers are connected to the zero potential bus of the device, the inputs The settings of the 1st and seventh triggers are, respectively, the inputs of the indication of the backside of the read and write operand of the device; the inverse output of the ninth trigger is connected to the second input of the fourth stage. And, the forward output of the ninth trigger is connected to the first 50 inputs of the fifth and sixth elements And, the synchronization input of the ninth trigger is connected to the input of the reset attribute of the device requests, the information input of the ninth trigger is connected to the bus of the unit potential of the device, the installation input of the ninth trigger is connected to the third synchronization input of the device, direct the output of the sixth trigger is connected to thirty 35 40 55 the first input of the seventh And element, the second input of which is connected to the third synchronization input of the device, the inverse output of the sixth trigger is connected to the third input of the third And element, the input of the installation in the Oh fifth trigger and the first inputs of the eighth and ninth And elements, the forward outputs of the seventh and eighth flip-flops are connected respectively with the second inputs of the eighth and ninth elements And, the third inputs of the eighth and ninth elements And connected to the second clock input device, inverse outputs of the seventh and eighth trig Geers are connected respectively to the third and fourth inputs of the seventh element I, the inverse outputs of the seventh and eighth triggers are connected and respectively to the installation inputs in About the tenth, eleventh triggers, and outputs of the eighth and ninth elements And are connected respectively to the installation inputs in the 1st tenth and eleventh flip-flops, the direct outputs of which are, respectively, outputs of the sign of requests for reading and writing the operand of the device and connected respectively to the second inputs of the fifth and sixth elements AND, the outputs of the cat respectively connected to the synchronization inputs of the seventh and eighth flip-flops, the second input of the fourth AND element is NOT connected to the device command load enable input, the output of the fourth AND element is NOT connected to the write enable input of the register block and the synchronization input of the second trigger, the inverse output of which is connected to information input of the second trigger, the direct output of which is connected to the input of the record of the register block, you-, the overflow of the counter is connected to the synchronization input of the third trigger, the inverse the output of which is connected to the information input of the third trigger, and the direct output - to the information input of the (n – H) -th register of the register group, the output of which is connected to the read enable input of the register block, the information output of the counter is connected to the information input of the decoder, the outputs of which are connected with information inputs from the first in registers of registers of registers, the synchronization inputs of all registers of the group 561073is connected to the first sync input of the device, ten 25 thirty the outputs from the first to the n-th register of the register group are connected respectively to the first inputs n of the elements of the n group, the second inputs of which are connected to (n + O input of the group n + 1 inputs of the device information read recognition, output of the 1st register of the register group i 1, ..., p) is connected to the first inputs from the 1st to the nth element of the AND-OR group, the outputs of the elements AND groups and the outputs of the elements I with AND-OR groups are connected respectively to the first and second groups of read inputs of the register block, the i-th input - the 1st element OR of the group is connected to the i-th input of the group of signs inputs 20 reading device information, the output of the 1st element OR group is connected to the (1 + 2) -th input of the AND-OR group elements, the n-th input of the device readout attribute is connected to the (n + 2) -th input from the first to the n- elements of the AND-OR group, the reset input of the device is connected to the second input of the first OR element and to the installation input in O from the sixth to the eighth flip-flops, the direct outputs of the fifth and tenth flip-flops are connected respectively to the first and second inputs of the second OR element, output which is the output of the device read mode indication, the inverse outputs with the eighth and eighth flip-flops are connected respectively to the first and second inputs of the fifth NAND element, the output of which is the output of the service request feature of the device, the direct output of the third flip-flop is connected to the information input of the (rM) th register of the register group, the output of which connected to the input mode of the unit . registers, the third group of information inputs of the device analysis node is connected to the group of inputs of the code of the indication of the information block of the device registers. 2 o The device according to claim 1, characterized in that the device analysis analysis node contains a decoder, a comparison circuit, an AND-OR element, a group of OR elements, and the output of the 1st element is connected to the i-th input of the AND element - OR, 1- the input of the first group of information inputs of the node is connected to the i-th input of the 1st element OR, the second group of information 35 40 50 55 formation inputs of the node is connected to the first group of inputs of the comparison circuit, the output of which is connected to the output of the node request, the second group of information inputs of the connection node to the group of information inputs of the decoder, the i-th output of which is connected to the 2 1 + 1) input of the AND-OR element the output of which is connected to the output of the node blocking attribute, the second group of inputs of the comparison circuit is connected to the third group of information inputs of the node, the nth input of the first group of information inputs of the node is connected to the (2 p M) th input of the AND-OR element 3 “The device according to claim 1, wherein the account control unit comprises a clock pulse generator, a counter, a decoder, an OR element, an AND-OR element, an AND-OR element, and from the first (n + 1) th informational inputs of the node group are connected to the inputs five 0 five OR, whose output and informational inputs of the node from the second to the nth are connected respectively from the first to the nth inputs of the AND-OR element, (n + 1) -th input of which is connected to the input of the blocking account of the node, the output of the AND-OR element connected to the start-up clock generator, the output of which is the node's output and connected to the summing input of the counter, whose information output is connected to the information input of the decoder, the outputs of which are connected respectively from the first to the nth inputs of the AND - OR - NOT element. The output of the OR element is connected to the n + 1 input of the element, the information inputs of the node group from the second to the nth are connected respectively to the (rH2) -th to (2n + 4) -th inputs of the AND - OR - NOT element, the output of which is connected to the inverse the installation input into the counter and the stop input of the clock generator. fig a Order 977 Circulation 576 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 Subscription