KR900005309Y1 - Memory banking circuit of computer - Google Patents
Memory banking circuit of computer Download PDFInfo
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- KR900005309Y1 KR900005309Y1 KR2019870022840U KR870022840U KR900005309Y1 KR 900005309 Y1 KR900005309 Y1 KR 900005309Y1 KR 2019870022840 U KR2019870022840 U KR 2019870022840U KR 870022840 U KR870022840 U KR 870022840U KR 900005309 Y1 KR900005309 Y1 KR 900005309Y1
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- memory
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- flip
- flop
- buffer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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Abstract
내용 없음.No content.
Description
제1도는 종래방식에 따른 메모리의 뱅킹을 설명하기 위한 도면.1 is a view for explaining the banking of the memory according to the conventional method.
제2도는 본 고안에 따른 회로도.2 is a circuit diagram according to the present invention.
제3도는 제2도의 회로동작에 따른 타이밍도.3 is a timing diagram according to the circuit operation of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10,11 : 버퍼 20, 21 : 플립플롭10,11 buffer 20, 21 flip-flop
30-32 : 논리게이트30-32: Logic Gate
본 고안은 메모리의 확장에 따른 메모리뱅킹(Banking)을 위한 컴퓨터의 메도리 뱅킹회로에 관한 것이다. 종래의 메모리 뱅킹 방식을 제1도에 기인하여 설명한다.The present invention relates to a memory banking circuit of a computer for memory banking according to expansion of memory. The conventional memory banking scheme is described with reference to FIG.
컴퓨터의 프로그램수행이 메모리의 A영역에서 수행되다가 메모리의 B영역을 A영역 대신에 수행하고자 할때, 처리루틴이 A'영역으로 들어간 다음 컴퓨터의 중앙처리장치는 A영역을 디스에이블시키고 B영역을 인에이블 시킨다.When the computer program is executed in the A area of memory and the area B of the memory is to be executed instead of the A area, the processing routine enters the A 'area, and then the central processing unit of the computer disables the A area, Enable it.
이로서, 메모리의 매핑(Mapping)은 A 영역이 OOOOH-7FFFH(H는 헥사)으로. B영역이 8OOOH-FFFFH으로 형성된다.As a result, the mapping of the memory is performed by the A area being OOOOH-7FFFH (H is hexa). The B region is formed of 8OOOH-FFFFH.
그리고 컴퓨터의 프로그램수행이 A'영역대신에 C영역을 이용하려면 처리루틴이 B영역으로 들어간 다음 A'영역을 디스에이블시키고 C영역을 인에이블 시킨다.If the program execution of the computer uses the C area instead of the A 'area, the processing routine enters the B area, then disables the A' area and enables the C area.
이때, OOOOH-7FFFH는 C영역이 8OOOH-FFFFH는 B영역이 차지하도록 메모리 매핑이 형성되어서 메모리영역이 A,A'영역에서 C,B영역으로 뱅킹된다.At this time, the memory mapping is formed so that the C area is occupied by the C area in the OOOOH-7FFFH area and the B area is occupied by the B area in the memory area.
이러한 종래방식은, 메모리의 A영역에서 B영역을 직접 이용하고자 할 때, 메모리의 A영역에서 프로그램을 수행중인 컴퓨터가 A영역을 디스에이블시키고 B영역을 인에이블시키면 데이터 충돌현상이 일어나거나 또는 메모리의 공백이 발생되어 프로그램의 수행이 중단되는 결점이 있었다.In the conventional method, when a region B of the memory is to be used directly, a computer executing a program in the region A of the memory disables the region A and enables the region B, thereby causing a data collision or the memory. There was a flaw in the execution of the program due to a space in the.
따라서 본 고안의 목적은, 상기한 결점을 해결하기 위해, 인터럽트 신호를 이용하여 메모리의 A,A′영역에서, B,C영역으로 직접 이용할 수 있도록 한 컴퓨터의 메모리 뱅킹회로를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a memory banking circuit of a computer that can be used directly from the A, A 'region of the memory, to the B, C region by using an interrupt signal.
다음은 제2도와 제3도를 참조하여 본 고안의 실시예를 상세히 설명한다.Next, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.
제2도는 본 고안의 회로도로서, 컴퓨터의 데이터버스를 통해 입력되는 데이터는 버퍼(10)를 통해 플립플롭(20)에 저장되고, 플립플롭(20)의 출력은 버퍼(11)를 통해 다시 데이터버스에 실리도록 연결되어 있다.2 is a circuit diagram of the present invention, in which data input through a data bus of a computer is stored in the flip-flop 20 through the buffer 10, and the output of the flip-flop 20 is returned through the buffer 11 again. It is connected to the bus.
컴퓨터의 중앙처리장치에서 출력되는 제어신호로서, 입출력 기입신호와 어드레스의 디코딩신호인 뱅킹신호는 오아게이트(30) 에 의해 논리합되어서 이 논리합신호로 상기 플립플롭(20)과 메모리의 뱅킹에 따른 제어신호인 메모리선택신호를 출력하는 플립플롭(2l)를 동기시키고, 상기의 뱅킹신호는 중앙처리장치의 인터럽트신호로 이용됨과 아울러 상기 버퍼(10)의 인에이블단자 및 앤드게이트(32)의 한 입력단에 제공된다.Input / output write signal as a control signal output from the central processing unit of the computer Banking signal which is a decoding signal of Is a logical selection signal, which is a control signal according to the banking of the flip-flop 20 and the memory. To synchronize the flip-flop (2l) and output the banking signal Is the interrupt signal of the CPU In addition to being used as an input to the enable terminal of the buffer 10 and the input terminal of the end gate 32.
컴퓨터의 중앙처리장치에서 출력되는 제어신호로서, 제어신호와 입출력요구신호는 오아게이트(31)에 의해 논리합되어서 이 논리합신호가 사이 앤드게이트(32)의 다른 입력단 및 상기 버퍼(11)의 인에이블단자에 제공된다.Control signal output from the central processing unit of the computer, the control signal And I / O request signal Is ORed by the OR gate 31 so that this OR signal is provided to the other input terminal of the AND gate 32 and the enable terminal of the buffer 11.
상기 플립플롭(21)은 동기신호가 인가될 때 마다 토글링되어 메모리선택신호를 출력하고, 상기 데이터버스에서 버퍼(10)로 제공되는 데이터는 프로그램의 수행정보인 인터럽트 벡터(Interrupt Vector)이다.The flip-flop 21 is toggled each time a sync signal is applied to the memory selection signal. The data provided to the buffer 10 in the data bus is an interrupt vector, which is execution information of a program.
이와같은 회로 구성에 있어, 컴퓨터가 메모리의 A영역에서 프로그램 수행중에 확장 메모리의 B영역으로 뱅킹하고자 할 때, 중앙처리장치는 제3도 (b)에 도시되어 있는 바와같이 로우레벨의 뱅킹신호를 앤드게이트(32)로 제공하여 버퍼(10)및 플립플롭(20)을 인에이블시키고 또한 이 뱅킹신호가 중앙처리장치의 인터럽트단자로 제공된다.In such a circuit configuration, when the computer attempts to bank from the area A of the memory to the area B of the expansion memory while the program is being executed, the central processing unit may display a low level banking signal as shown in FIG. Is provided to the AND gate 32 to enable the buffer 10 and the flip-flop 20 and also to provide this banking signal. Is provided as the interrupt terminal of the central processing unit.
이와동시에, 입출력기입신호 IOWR가 제3도 (c)와 같이 로우레벨로 되어 오아게이트(30)를 거쳐 플립플롭(20)(21)의 동기단자로 제공된다.At the same time, the input / output write signal IOWR goes low as shown in FIG. 3 (c) and is provided to the synchronization terminal of the flip flops 20 and 21 via the ora gate 30.
이때, 데이터버스에서 전송되는 인터럽트 벡터의 데이터는 버퍼(10)를 거쳐 플립플롭(20)에 인가되어 래치되고, 아울러 플립플롭(21)은 토글링(Toggling) 되어서 메모리선택신호를 출력하여 메모리의 영역을 A영역에서 B영역으로 바꾼다.At this time, the data of the interrupt vector transmitted from the data bus is applied to the flip-flop 20 through the buffer 10 and latched, and the flip-flop 21 is toggled to the memory selection signal. To change the area of memory from area A to area B.
그리고, 컴퓨터의 동기펄스(제3도의 a)에서 T3의 상승엣지(RisingEdge)일 때 인터럽트신호를 입력한 중앙처리장치에서는 제어신호(제3도의 E)와 입출력 요구신호(제3도의 F)를 출력하여 버퍼(11)를 인에이블시킨다.In the central processing unit that inputs the interrupt signal when the rising edge of T 3 is increased in the synchronization pulse of the computer (a in FIG. 3 ), the control signal is controlled. The buffer 11 is enabled by outputting (E in FIG. 3) and an input / output request signal (F in FIG. 3).
이로서, 상기 플립플롭(20)에 일시 저장되어 있던 인터럽트 벡터가 버퍼(11)를 거쳐 데이터 버스로 제공되어서 컴퓨터의 중앙처리장치는 데이터버스를 통해 입력된 인터럽트 벡터에 의해 프로그램을 수행한다.Thus, the interrupt vector temporarily stored in the flip-flop 20 is provided to the data bus via the buffer 11 so that the central processing unit of the computer executes the program by the interrupt vector input through the data bus.
이상에서 설명한 바와같이 본 발명에 의하면, 컴퓨터의 확장된 메모리로의 프로그램수행을 직접 가능케하여 메모리확장에 의한 뱅킹문제를 해결한 이점이 있다.As described above, according to the present invention, it is possible to directly execute a program to an expanded memory of a computer, thereby solving the banking problem due to memory expansion.
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KR2019870022840U KR900005309Y1 (en) | 1987-12-23 | 1987-12-23 | Memory banking circuit of computer |
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KR2019870022840U KR900005309Y1 (en) | 1987-12-23 | 1987-12-23 | Memory banking circuit of computer |
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KR890014248U KR890014248U (en) | 1989-08-10 |
KR900005309Y1 true KR900005309Y1 (en) | 1990-06-15 |
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KR2019870022840U KR900005309Y1 (en) | 1987-12-23 | 1987-12-23 | Memory banking circuit of computer |
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