KR890014248U - Computer memory banking circuit - Google Patents
Computer memory banking circuitInfo
- Publication number
- KR890014248U KR890014248U KR2019870022840U KR870022840U KR890014248U KR 890014248 U KR890014248 U KR 890014248U KR 2019870022840 U KR2019870022840 U KR 2019870022840U KR 870022840 U KR870022840 U KR 870022840U KR 890014248 U KR890014248 U KR 890014248U
- Authority
- KR
- South Korea
- Prior art keywords
- computer memory
- memory banking
- banking circuit
- circuit
- computer
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019870022840U KR900005309Y1 (en) | 1987-12-23 | 1987-12-23 | Memory banking circuit of computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019870022840U KR900005309Y1 (en) | 1987-12-23 | 1987-12-23 | Memory banking circuit of computer |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890014248U true KR890014248U (en) | 1989-08-10 |
KR900005309Y1 KR900005309Y1 (en) | 1990-06-15 |
Family
ID=19270643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019870022840U KR900005309Y1 (en) | 1987-12-23 | 1987-12-23 | Memory banking circuit of computer |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR900005309Y1 (en) |
-
1987
- 1987-12-23 KR KR2019870022840U patent/KR900005309Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR900005309Y1 (en) | 1990-06-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20020530 Year of fee payment: 13 |
|
EXPY | Expiration of term |