JPH052875A - Video memory - Google Patents

Abstract

PURPOSE:To miniaturize the video memory by unnecessitating an external circuit generating a pseudo light transfer cycle at the time of executing serial light only one time at first like screen clear after a power source is applied. CONSTITUTION:A flip-flop 2 at the head of a pointer 7 is set by a signal generated from a power source application detecting circuit 9 after the power source is applied and also the other flip-flops 2 are reset. Since the bit position of a serial data register 6 constituted by latches 1 is set at the head, serial data is successively read by a serial clock without executing the pseudo light transfer cycle for setting the bit position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a video memory used as an image frame memory in an information device such as a personal computer or a workstation.

[0002]

2. Description of the Related Art In recent years, a video memory has been used as an image frame memory for personal computers, workstations and the like.

A conventional video memory is generally constructed as shown in FIG. In FIG. 2, 5 is a data storage unit called a RAM having a random access function, and 6
Is a serial data register which has a storage element of 1 line bit width of the RAM 5 and sequentially stores serial input data. 7 is a pointer for designating a bit position of the serial data register 6 in which serial input data is stored, 8
Is a decoder for giving an initial value of a bit position to the pointer 7 by an address signal.

The pointer 7 receives the initial value of the bit position of the data register 6 by the decoder 8 and sequentially shifts to the upper bit by the serial clock. As a result, serial input data that is continuously given is
In the serial data register 6, the data is first stored in the bit position indicated by the decoder 8 and then sequentially stored in the upper bits. The serial input data stored in the serial data register 6 is transferred to one line of the RAM 5 in response to a data transfer cycle request to the RAM 5.

FIG. 3 shows the serial data register 6 of FIG.
3 is a concrete circuit configuration example of the pointer 7 and the pointer 7. This will be described below.

The serial data register 6 is composed of a latch circuit 1 which stores serial input data of a number corresponding to the number of 1 line bits of the RAM 5. Pointer 7
Is composed of a shift register composed of a flip-flop 10 for storing pointer data for selecting a bit position of the serial data register 6 and a multiplexer 3. WDT and WDT 'are data transfer control signals indicating that the cycle for the RAM 5 is a data transfer cycle, and WDT' is a signal slightly delayed from WDT. During the transfer cycle, the flip-flop 10 is supplied with the signal from the decoder 8 via the multiplexer 3.

In response to the data transfer control signal WDT indicating the data transfer cycle, the signal of the decoder 8 which is the initial value of the bit position is stored in the flip-flop 10 via the multiplexer 3 during the data transfer cycle. After the end of this data transfer cycle, the serial clock sequentially shifts to the upper bits.
The serial input data continuously given by this is
First, the data is stored in the latch circuit 1 at the bit position indicated by the decoder 8, and thereafter sequentially stored in the upper bits. The serial input data stored in the latch circuit 1 of the serial data register 6 is transferred to one line of the RAM 5 in a data transfer cycle to the RAM 5.

[0008]

In such a conventional video memory as described above, the initial address of the serial data register 6 is set when the serial write is performed only once at the first time such as when the screen is cleared after the power is turned on. It is necessary to perform a pseudo write transfer cycle in order to perform serial input with the register as the head of the register, and an external circuit for generating a pseudo data transfer control signal is required. As a result, an extra control signal generation circuit is required in a graphics system for miniaturization, which hinders miniaturization.

In order to reduce the above problems, it is an object of the present invention to provide a serial write without providing an extra control signal generating circuit and without performing a pseudo write transfer cycle.

[0010]

In order to achieve the above object, the present invention provides a memory having a random access function, a data register for storing serial input data,
A shift register for storing bit position designation data of the data register is provided, and power-on detection means for generating a signal for a certain period at power-on and output from the power-on detection means are stored in the shift register. Bit position designation data setting means for setting the bit position designation data to be the head of the data register is provided.

[0011]

According to the present invention, the bit position designation data is turned on in the shift register for storing the bit position designation data in the data register when serial input for clearing the screen is performed after the power is turned on. It is set at the head of the data register by the output of the detecting means. As a result, since the initial address of the data register is set at the head of the data register, serial write can be performed without performing the pseudo write transfer cycle, and the external circuit for generating the pseudo write transfer control signal can be It becomes unnecessary.

[0012]

1 is a circuit diagram of a serial data register called SAM of a video memory showing an embodiment of the present invention. An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 5 is a data storage unit having a random access function called a RAM, 6 is a serial data register configured by a storage element having a 1-line bit width, and serially input data is stored, and 7 is serial input data. Is a pointer for designating the bit position of the serial data register 6 for storing the shift register and the multiplexer 3 composed of the flip-flop 2.
Composed of and. Further, 8 is a decoder for generating initial data of a bit position, WDT and WDT 'are signals generated during a write transfer cycle, and WDT' is W
It is delayed a little more than DT.

Reference numeral 9 is a power-on detection circuit that generates a signal when the power is turned on. The signal from the power-on detection circuit 9 is input to the set terminal of the flip-flop 2 of the first bit of the pointer 7 and the reset terminal of the other flip-flops 2. With this configuration, when the power is turned on, the flip-flop 2 of the first bit is set by the signal from the power-on detection circuit 9,
Bit position designation data setting means 11 for setting the other flip flops to set the bit position designation data stored in the shift register (flip flop) 2 to the head of the serial data register 6 is configured. is doing.

Therefore, when the power is turned on, the bit position designation data setting means 11 sets the bit position of the serial data register 6 at the head. Then, after that, the bit position is shifted to higher bits by the serial clock. Therefore, serial input data sequentially input is stored from the beginning of the serial data register 6, and the serial input data stored in the serial data register 6 is transferred to one line of the RAM 5 in response to a write transfer cycle request. The setting of the initial bit position of the serial data register 6 after the data transfer to the RAM 5 is output from the decoder 8 in the write transfer cycle, and the output of the decoder 8 is the WDT signal output in the write transfer cycle. Is stored in the flip-flop 2 via the multiplexer 3 by
The initial value of the bit position is set. The operation after this is
The above serial input → write transfer cycle is repeated.

Therefore, when the serial write is performed with the initial address of the data as the head of the data register after the power is turned on, the serial write can be performed without performing the pseudo write transfer cycle.

[0016]

As is apparent from the above embodiments, according to the present invention, when serial writing is performed from the head of the serial data register as in the case of clearing the screen after power-on, the serial data register For the shift register that controls the bit position, after the power is turned on, the initial address of the serial data register was set to the beginning by the signal generated when the power was turned on, so the video memory can be cleared without performing the first pseudo write transfer cycle. Therefore, an external circuit for generating the pseudo write transfer cycle is not required, and it is possible to miniaturize a graphics system for miniaturization. The screen clear may be performed on all bits of the video memory.

[Brief description of drawings]

FIG. 1 is a specific circuit configuration of a serial input register of a video memory showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a video memory.

FIG. 3 is a specific circuit configuration of a serial input register of a conventional video memory.

[Explanation of symbols]

 1 Latch 2 Flip Flop 3 Multiplexer 5 RAM 6 Serial Data Register 7 Pointer 9 Power Supply Detection Circuit 11 Bit Position Designation Data Setting Means

Claims (1)

What is claimed is: 1. A memory having a random access function,
A data register for storing serial input data, a shift register for storing bit position designation data of the data register, a power-on detection means for generating a signal for a certain period at power-on, and an output of the power-on detection means A video memory, comprising: bit position designation data setting means for setting the bit position designation data stored in the shift register to be the head of the data register.