JPS61273640A - Logical simulator - Google Patents

Abstract

PURPOSE:To simulate a filmed pseudo circuit at a high speed by reading out the inter-gate connection data corresponding to the type data on the block to be simulated as well as the gate type data for simulation of each component of the block. CONSTITUTION:Plural block type storing circuits 103 sort and store the type data on plural blocks, and the gate connection circuits 105 corresponding to the circuits 103 store plural inter-gate connection data. Then the gate type storing circuits 106 store plural gate types in response to the circuits 105. Furthermore the arithmetic circuits 108 execute simultaneously the simulation of the gates of plural blocks. Thus the gate type data corresponding to the type data on the blocks to be simulated are read out according to the order desided previously to the test pattern data. Then the gates constituting the blocks are simulated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation device for simulating logic circuits.

[Conventional technology]

Logic simulation is the opening Q of LSI and large-scale systems.
K is an indispensable tool. Today, as the scale of systems continues to grow, it is becoming increasingly difficult to discover errors introduced during design. Friend, the existence of errors after the LSI is completed increases the cost of remanufacturing the chip and prolongs the development period. Therefore, it is necessary to eliminate design errors as early as possible in device development. Traditionally, logical simulations were performed sequentially by software using large-scale calculations [e.g.
f Sasaki, et al [A Mixed Level Simulator
"For Large Digital System Logic Verification" 17th DA Conference, pp. 626-633 (19801J (8asaki).

T,et al “A Mixed Level S
imulator for Large Digit
al 8system Logic Verificat
ion, 17th DA Conf, p 6
267633 (1980') l.

[Problem that the invention seeks to solve]

Since the conventional logic simulator described above is created using software, it has the disadvantage that the larger the device to be simulated, the fewer the number of verification patterns that can be executed within a certain period of time.

[Means for solving problems]

The apparatus of the present invention includes a block configured of a data input means for inputting at least logical design file data and verification test pattern data, a test pattern data storage means for storing the test pattern data, and a gate that is a simulation execution unit. a plurality of block type storage means for storing type data of a plurality of blocks in groups so as to be read out simultaneously according to the order of logical operations of each block in the entire simulated logic circuit; and gates in the blocks; inter-gate connection data is stored in correspondence with the plurality of block type storage means, and is grouped so that the inter-gate connection data of the plurality of gates can be read out simultaneously according to the order of logical operations of the gates in the block. a plurality of inter-gate connection storage means for storing for each gate; a gate type storage means for storing the gate type data in correspondence with the plurality of inter-gate connection storage means; and state values of input pins of the block. and intermediate logic value storage means for storing state values of gates during simulation in correspondence with the plurality of block type storage means;
a plurality of arithmetic means for simultaneously performing shimmy calculations of a plurality of gates of the plurality of blocks read at the same time; and storing output state values of the blocks in correspondence with the plurality of block type storage means. a plurality of block output value storage means, an inter-block connection storage means for storing connection data between the plurality of blocks constituting the simulated logic circuit, and output state values of the blocks during simulation and the simulated logic circuit. and a means for storing and outputting a simulation result value of the test pattern data, and reading inter-gate connection data and gate type data t-reading the block corresponding to the type data of the block to be simulated according to a predetermined order with respect to the test pattern data. A simulator of the logic circuit to be simulated by simulating each constituent gate of the logic circuit.

configuration.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The logic simulation device in FIG. 1 includes an input section 5 into which logic design files, verification test data, etc. are input.
0, a simulation section 100 that simulates the target circuit, and an output section 200 that outputs the simulation results.

The shimmy lace and f section 100 is a pattern storage memory 101.
:, Type data of the block to be simulated (1
For example, there is a gate connection memory group 105, a block type storage memory group 103 that stores the start address for the gate type storage memory group 106, and an intermediate block type storage memory group 103 that stores the block input pin values and state values during simulation. A logic value storage memory group 104, a gate connection memory group 105 that stores data indicating which gate in the block is connected to which gate in the previous stage, and the type of gate to be simulated (AND, OR, EXO).
A gate type storage memory group 106 in which data of gates (R, etc.) is stored, an arithmetic circuit group 108 that simultaneously executes simulations of multiple gates in a block, and a block output value in which values of output pins of the block are stored. It is composed of a storage memory group 107, an inter-block connection storage memory 109 containing data indicating which block in the previous stage the simulated block is connected to, and a control circuit 102 that controls the entire system. Reference numbers 150 to 160 are signal line groups connecting each circuit.

FIG. 2 is a partial block diagram of the arithmetic circuit in FIG. 1 and its surroundings, and FIG. 3 is a partial block diagram of the arithmetic circuit in FIG.
FIG. 4 is a partial block diagram of the arithmetic circuit shown in FIG. 3.

Further, FIG. 5 is an example of a circuit to be simulated. Simulated circuit 10
00 is the input terminal 1001, the output terminal 1002, and the simulation unit blocks 1100 and 1200°13
00, 1400, and 1, and block 1100 consists of game blocks 1101 to 1107. Reference number 2000 is test pattern data for verification.

Next, how the circuit to be simulated is simulated will be explained with reference to FIGS. 1 to 5.

(1) Logical design file load blocks 1100, 1200, 1300 and 1400
The design data related to the gate-connected memory group 105 . The gate type storage memory group 106 is stored in the intra-block connection storage memory 109.

At this time, an operation order level is assigned to each block from the input terminal to the output terminal according to the order of the logical operation of each block of the circuit to be simulated. Each block is assigned to a gate connection memory group 105 and a gate type storage memory group 106 in this level unit. In FIG. 5, blocks 1100 and 1200 operate before blocks 1300 and 1400, so blocks 1100 and 1200 are at level 1, and blocks 1300 and 1
400 is set to level 2 (■ and ■ in FIG. 5 indicate this).

The storage pattern of these data is shown in the gate connection memory group 105 and gate type storage memory group 106 in FIG. That is, one memory 105-1 in the gate connection memory 9 group 105 has blocks 1100 and 1300.
However, blocks 1200 and 1400 are stored in another memory 105-2. Also, gate type storage memory group 1
In 06, the gate types corresponding to those blocks are memo 17106-1 and 9 respectively.
and 106-2. By storing these data, simulation can be executed on blocks 1100 and 1200 at the same time and on blocks 1300 and 1400 at the same time.

Furthermore, the gate simulations within a block are stored in groups that can be executed simultaneously in sequence corresponding to the data flow within the block (according to the order of logic operations within the block) so that a plurality of gates can be executed simultaneously. Memory 105-1 in FIG. 3 shows the storage status of the constituent gates in block 1100 in FIG. 5. That is, gates 1104 and 1105 are gates) 1101, 1102
．． Gate 110 operates based on the operation result of 1103.
They are arranged in a different group from the group 1,1102.1103.

In the configuration shown in FIG. 3, gates 1101, 1102, 1103
The configuration is such that it can be executed simultaneously. Gate 106-
1 represents the type of those gates in the memory 105-
It is stored corresponding to 1. For example, the gate 1101 is an AND gate, and the gate 1107 is a NAND gate.

(2) The test pattern data 2000 for test data load verification is input to the input section 50t.
- is stored in the pattern storage memory 101 through.

(3) A simulation execution start signal is sent from the simulation execution input section 50 and supplied to the control circuit 102. The control circuit 102 controls the block 11 based on the information in the inter-block connection storage memory 109.
00.1200 is first simulated. Since the blocks 1100 and 1200 are directly connected from the input terminals, the data of the terminals connected to both blocks is stored in the pattern storage memory 101 at 104-1.1 in FIG.
Set each to 04-2. Now that the conditions for simulating the blocks are in place, the gate start addresses of both blocks are stored in the block type storage memory 10.
Read from 3. The gate connection memory 105 and gate type storage memory 106 are read using these addresses. @2 In figure 2, memory 105-1, 105-2゜106-
1.106-2 is read. In Figure 5, gate 11
01, 1102, 1103, 1201, 1202.

1203 is read at the same time. At this point, the conditions for simulating the gates in both blocks have been set, so the arithmetic circuit group 108 (108-1, tos) is performed.

The arithmetic circuit 108-1 includes a plurality of partial circuits 108-a (
FIG. 3 shows an example of a detailed circuit of the partial circuit 10H (four in the illustrated example).

The partial circuit in Figure 3 is OR gate simulation circuit 1
08-a-1 and AND Gut Simulation.

an EXOFL gate simulation circuit 108-a-3; three circuits 108-a-4 for selecting true or negative values of the outputs of the three circuits; Selection circuit 1 that selects one of the outputs
08-a-5. The connection information supplied from the memory 105-1 via the signal line 15B is logic "1" when connected, and logic "1" when not connected.
0'' is supplied to the memory 104 via the signal line 156.
The logic value supplied from -1 is the test pattern data or the output value of the preceding gate after simulation. The information supplied from the memory 106-1 through the signal line 159t consists of 3 bits and is set to "0" to the OR gate.
0”.

01” for AND gate, ul for EXOR gate
o'' is supplied, and the remaining 1 bit is supplied with '1' for the true value and '0' for the negative value, respectively.

As an example, assume that the partial circuit 10t1 operates with 7 bits, and when simulating the game 1101t in FIG. 2, the values supplied to the signal line 15B are '11oooooo',
"1111101" for signal line 156, signal line 159
becomes “ioi” and outputs 1 to the signal line 157.
1” is output.

Then, based on these values, the game of block 1100)
1104, 1105, gate 120 of block 1200
4°1205 is calculated. Block 1200 has obtained the block output at this point, but block 1100
There are still gates left, so the remaining gate 1106
and 1107 are performed to determine the block output value. Once these values are determined, they are stored in the block output value storage memory group 107 (107-1, 107-2). Blocks 1300 and 1400 are then subjected to simulation. The input pins of these blocks are pre-locked 1100.1 by the inter-block connection storage memory 109.
The values of the pins connected to the blocks 1300 and 1400 with the output pins 200 are stored in the intermediate logic value storage memory group 104.
(104-1, 104-2). block 1
The simulation within 300.1400 is performed in a similar manner as described above. When blocks 1300 and 1400 are completed, it means that all blocks have been completed, so their output values are displayed on the output section 200, and the simulation of the next pattern is started. When all the patterns are completed, the simulation of the circuit to be simulated is completed.

As described above, according to this embodiment, a plurality of blocks can be simultaneously simulated and a circuit to be simulated can be simulated at high speed.

〔Effect of the invention〕

By realizing logic circuit simulation in hardware, the present invention reduces the time required for one gate simulation to several hundred nanoseconds, compared to the tens of microseconds required by conventional software simulators. This has the effect of dramatically increasing the number of test pattern data that can be simulated within a unit of time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Figures 2 and 3 are partial block diagrams of the arithmetic circuit in Figure 1 and its surroundings, Figure 4 is a partial block diagram of the arithmetic circuit in Figure 3, and Figure 5 is an example of a simulated circuit. It is a diagram. 50...Input i, 100...Simulation section. 200...Output unit, 101...Pattern storage memory. 102... Control circuit, 103... Block type storage memory group, 104... Intermediate logic value storage memory group, 105... Gate connection memory group, 106 ...Gate type storage memory group, 107
...Block output value storage memory group, 108...
...Arithmetic circuit group, 109...Block connection storage memory, 150-160...Signal line,
1000... Simulated circuit, 1001...
...Input terminal, 1002...Output terminal, 110
0~1400...Burotsukyu 1101~110
7...Gate, 2000...Test pattern data.

Claims (1)

[Scope of Claims] A block comprising: data input means for inputting at least logic design file data and verification test pattern data; test pattern data storage means for storing the test pattern data; and a gate as a simulation execution unit. a plurality of block type storage means for storing type data of a plurality of blocks in groups according to the order of logical operations of each block in a simulated logic circuit so that the type data of a plurality of blocks are read out simultaneously; inter-gate connection data of the plurality of blocks are stored in correspondence with the plurality of block type storage means, and are grouped so that the inter-gate connection data of the plurality of gates are read out simultaneously according to the order of the logical operations of the gates in the block. a plurality of gate-to-gate connection storage means for storing data for each gate; gate type storage means for storing the gate type data in correspondence with the plurality of gate-to-gate connection storage means; intermediate logic value storage means for storing state values and state values of gates under simulation in correspondence with the plurality of block type storage means; and simultaneous simulation of the plurality of gates of the plurality of blocks read simultaneously. a plurality of block output value storage means for storing the output state value of the block in correspondence with the plurality of block type storage means; and a plurality of the block output value storage means constituting the simulated logic circuit. an inter-block connection storage means for storing inter-block connection data; and an output means for storing and outputting an output state value of the block during simulation and a simulation result value of the simulated logic circuit; The logic circuit to be simulated is simulated by reading inter-gate connection data and gate type data corresponding to the block type data to be simulated in a predetermined order and simulating each constituent gate of the block. A logic simulation device for