JPS59119595A - Logical lsi incorporating ram - Google Patents

Abstract

PURPOSE:To take an excellent test by transferring test data set in a write register and writing it in an RAM by the same clock when an RAM test mode is specified externally, and outputting the contents of the RAM read out to a read register by the same clock. CONSTITUTION:The basic pattern of write data from a data pin 20 to the RAM is set in a register 4 in normal mode and then a test mode is set to supply microinstructions, one after another, from a pin 23, taking a test of the RAM. Output data outputted from the RAM2 to the data pin 20 by four bytes at a time is compared with an expected value to test whether the RAM is normal or not. Thus, the test mode is provided and data pins of an LSI correspond to read/ write registers in the RAM, one to one, in said test mode; and data is inputted and outputted by using a clock in normal mode, so the influence of variance in signal delay time among peripheral logical circuits is reduced greatly to take the severse RAM test easily.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to RAM (Random Access Memory)
This is related to the RAM test of a logic LSI with a built-in.

[Prior art]

With advances in semiconductor technology, the scale of L and 8I has become larger, and very large scale integrated circuits (VLSIs) have recently been developed.

With this increase in scale, testing to determine the quality of LSIs has become increasingly difficult.

In particular, when RAM and logic circuits are included in the same LSI, W
Testing becomes more difficult as more logic is added between the RAM and the LSI's output bins.

Conventionally, when an LSI is formed from a single RAM, that is, when the LSI has no logic circuit or only contains simple circuits such as an address decoder, the RAM test is performed using the LSI0 input/output bin. Since there is a one-to-one correspondence between the RAM address bin, data pin, etc.
It was sufficient to supply test data (for example, data for testing gearropping, marching, etc., addresses, etc.) to this LSI pin. Therefore, the test data creation and testing methods were very simple and efficient.

However, as LSIs become larger and have a RAM surrounded by logic circuits, it becomes difficult to test the RAM. That is, as the logical scale of the RAM and the LSI output bin becomes larger, it becomes difficult to establish a one-to-one correspondence between the address bin and data pin of the LSI output bin AM. Also, suppose that such a state can be set, for example, by applying a level signal to the clock signal of a flip-flop between the LSiSi output pin and the AM pin, and treating the flip-flop as a gate. Also, LS1 output pin and l'1. Variations in the signal delay time of the logic circuit with the AM are also tested, making it impossible to perform a strict RAM test.

[Purpose of the invention]

An object of the present invention is to realize a good test in such a logic LSI with a built-in RAM that solves the above-mentioned problem of the built-in RAM.

[Summary of the invention]

The present invention provides a write register in which write data to R and AM is set at a predetermined clock and transferred to the RAM at a predetermined clock; a read register in which read data from the RAM is set at a predetermined clock;
A logic LSI that has a logic operation unit that performs operations using human data supplied from outside the SI and from R and AM, and is configured so that the operation results are taken out outside the LSI or stored in the RAM. Assuming that.

The present invention provides such a logic], in an SI, when a RAM test mode is specified from outside the LSI, the test data set in the write register is set to the same clock as the above clock. 11-It is characterized by a logic LSI with a built-in RAM, which has a control means for controlling the contents of R and AM, which are transferred to the RAM, written therein, and read out to the read register at the same clock as described above, to be taken out to the outside. .

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained using the drawings.

FIG. 1 is an internal block diagram of the LSI. In the diagram, thick arrows indicate data flow and its direction, and thin arrows indicate control systems. In the figure, 1 is a logical operation unit (hereinafter abbreviated as ALU) in 4 bytes that has functions such as addition, subtraction, and shifting, and 2
is 4/item x 256 words of RAM, 5 and 4 are ALU
5 is a register for outputting the result of ALU 1, and 6 and 7 are manual data selection circuits (selectors) for registers 3 and 4, respectively.

20 is a data pin for transmitting and receiving human output data to and from this LSI, and its transfer path has a bus structure with a width of 4 wires, and is connected to an internal bus 60 under the control of gate 8. .The internal bus 30 is connected to the selector 6.
7 and is taken into the telesistor 34. Also, the data in registers 3, 4.5 are 9, 10.
The signal is output to the internal bus 30 under the control of 11. - The data in register 5 returns to register 6.4 and also becomes write data in RAM2.

Address register 12 is a register that stores the address of RAM2, and register 5, C'rL14
.

The 8-bit address information entered manually in the address bin 22 is also selected by the selector 16 and taken in.

The entire LSI is controlled by the CTLla, but the control lines from the CTL 14 are omitted in FIG.

Microinstructions supplied to this LSI from the outside enter the CTL 14 through the bin 23. Although the clock is not shown, the four phases of To, Ti, T2, and T5 are LS
Supplied from an internal clock generation source. Register 6.
TO is supplied to register 4, T3 is supplied to register 5, and TO and T2 are supplied to address register 12.

An example of the operation will be explained below with reference to FIG.

First, the operation in normal mode will be described. Normal mode is the mode when the signal supplied from pin 21 is 0''.], manual data from data pin 2o of SI, A
The data in the register 5 to which the LU1 processing result is output, or the read data from the RAM 2, is selected by the selector 6.7 under the control of the CTLl 4 in accordance with a microinstruction manually inputted from the pin 23, and then sent to the register 6.
．． Set sale for 4. This data is processed by ALU1, and the result is taken into register 5 at clock T6.

The data in this register 5 is not inputted into the register 6.4 again, is not taken out from the LSI through the data pin 2o, or is written to the RAM 2. The address register 12 of RAM 2 is set within one machine cycle.

The write address and the read address are set twice, T2 and T2, respectively. In other words, within one machine cycle, RAM2 can perform two readings and one writing at maximum.
Access is possible.

FIG. 6 shows the operation when reading is performed to an address to which writing to RAM 2 is attempted. That is, in FIG. 6, the processing result of ALU1 in cycle
When attempting to write to B +, if a read command is received at the same address 'B' in read stage 1, if the data at address l B + is read as is in read stage 1, incorrect data (i.e. old data before rewriting) will be generated. ).Therefore, a monitoring circuit (not shown) constantly monitors whether the addresses of read stage 1 and write stage 20 match, and when both addresses match, register 5, which is write data, is read. The data is transferred to register 4 as is.

This process is called wraparound process.

Next, the operation in RAM test mode will be explained. R
The AM test mode is a mode when the signal supplied from pin 21 is +1+. The internal structure of the LSI when it is in this mode appears as shown in Figure 4 when viewed from the outside. Conversely, the only microinstructions that operate in this configuration are those that can be specified in this mode.

The RAM test is performed using the following procedure. First, set the normal mode (that is, the input signal of the bin 210 is °0"), and set the basic pattern of write data to the RAM from the data pin 20 to the register 4. Set the microinstruction to the pin 26.
give to Next, the test mode (i.e. bin 210
The W test is performed by setting the input signal to 1°) and giving microinstructions one after another from pin 25. At this time, change the addresses of R and AM2 through the address manual pin 22, and
Perform M write and read tests. The data to be written to R and AM is the result of processing the basic pattern already set in register 4 in ALU1 at clock T5.
What is set in register 5 is supplied. Processing is, for example, shifting the basic pattern one bit to the left or right. The RAM address is set and supplied to the address register 12 from the address input pin 22 using clocks TO and T2. On the other hand, R, AM 2
After the data read from the register 3 is set with TO, it is sent from the gate 9 to the bus 30. Four bytes are simultaneously output to the data bin 20 via the gate 8. A tester external to the LSI tests the quality of the RAM by comparing this output data with expected values.

This series of operations is controlled by microinstructions from pin 26. However, under the RAM test mode, as shown in FIG. A
The old data before M is rewritten is read into the register 6.

This allows gearropping and marching tests.

In addition, a test to check the margin of the RAM can be made possible by shifting the phases of the clock T5 of the register 5, the clocks To and T2 of the address register 12, and the clock TO of the register B which becomes a read register.

With the above method, the W write data is precisely aligned in phase with the clock T3 of the register 5, the read data is also taken in with the clock TO of the register 6, and the R
, AM2 are taken into the address register 12 with the phases of TO and T2 aligned, so that ALU1, gate 9. Bus 30. Gate 8, address human selector 1
It is not affected by variations in signal delay time due to gates such as No. 3 and wiring patterns.

In this embodiment, in the Fl and AM test modes, the level signal is directly supplied from the outside of the LSI through the dedicated bin 21, but this may be held by having a flip-flop inside the LSI.

Also, the address for RAM test is address manual bin 22.
Although this is directly supplied from the LSI, this may also be generated inside the LSI if possible.

Furthermore, although this LSI is controlled externally using microinstructions, it may also be controlled using built-in microinstructions, and it is clear that it can also be applied to LSIs that perform external control other than microinstructions. It is.

Although the data bin 20 of the MATA LSI is a human output pin (that is, depending on the bus configuration), it may have separate human/output bins. Furthermore, it is clear that the inside of the LSI does not need to have a bus configuration.

Further, by separating the RAM write data register clock, read data register clock, and address register clock from other in-phase clock signals and LSI bins, it is possible to perform a RAM margin test with more freedom.

〔Effect of the invention〕

As described above, in the present invention, a RAM test mode is provided, and under this mode, the data pins of the LSI and the RAM
The state is set such that there is a one-to-one correspondence between the read/write registers and the data output to these read/write registers is normally performed at the same clock as in the case of Always avoids the influence of variations in signal delay time of RAM peripheral logic circuits.
You can easily perform detailed and rigorous RAM tests.

[Brief explanation of the drawing]

Fig. 1 is an internal block diagram of an LSI that is an embodiment of the present invention, Figs. 2 and 6 &1 Time chart in normal mode, Fig. 4 1-1 LSI effective in R, AM client mode A block diagram showing the configuration, and FIG. 5 is a time chart in B and AM test modes. Explanation of codes 1...ALU, 2...Monk W, 5,
4.5...Register, 12...Address register, 20...Chip Bin, 22.
・・・・・・Address human power bin, 21.25・・・・・・
Pin Representative Patent Attorney Susuda 1・”: Fraud゛j Saildentome@- @

Claims (1)

[Claims] 1. A logic LSI with a built-in RAM, the RAM
A write register in which write data to M is set at a predetermined clock and transferred to the RAM at a predetermined clock; a read register in which read data from the RAM is set at a predetermined clock; It has a logic operation unit that performs calculations based on human data supplied from the RAM, and the calculation results are sent to the LS.
In a logic LSI that is configured to be taken out to the outside of the I or stored in the RAM, when a RAM test mode is instructed from outside the LSI, the test data set in the write register is read by the clock. (above) (The contents of the RAM are transferred to the RAM and written, and the contents of the RAM read to the read register with the clock are read out to the outside.
R, AM built-in logic LSI characterized by having a control means for controlling