JPH0763827A - Memory testing method - Google Patents

Abstract

PURPOSE:To make it possible test a memory under test in real time by outputting the mutually different partial basic-memory testing pattern data from basic memory-test pattern data stored beforehand, respectively converting the data into logic pattern data in parallel, temporally storing the data, and sequentially outputting the data into testing steps. CONSTITUTION:A host computer 1 controls a basic memory-test-pattern memory part 2 and outputs the different partial memory-test patterns into memory-test- pattern converting circuits 31-35 from the stored basic-memory patterns. The circuits 31-35 convert the partial memory-test patterns into memory logic patterns and store the patterns into temporal memory registers 41-45. The data are inputted into a logic-pattern generator 8 through a selecting circuit 6. Test logic pattern data are formed based on the basic clock of a master timing generator 7. A test signal output circuit 9 forms the test signals based on the data, applies the signals into an LSI under test 11 through a test head 10 and performs the memory test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test method, and more particularly to a memory test method for testing a memory circuit in a semiconductor integrated circuit incorporating the memory circuit.

In recent years, LSIs have changed from LSIs, which are a set of simple logic circuits, to general-purpose LSIs including peripheral circuits such as memory circuits and analog circuits. Along with this, various optional devices have been added in order to correspond to the individual circuits built in the LSI, and the price of the test device has become very expensive.

Therefore, there is a demand for a memory test method capable of handling a large amount of test data in real time and easily configuring it without lowering the test capability.

[0004]

2. Description of the Related Art Conventionally, an algorithm pattern generator (ALPG; ALPG) has been used as a device for carrying out a memory test.
A device having a golithmic test pattern generator) is common.

FIG. 4 shows a schematic block diagram of a conventional memory test apparatus having an ALPG. Memory test equipment
An ALPG 20 for generating and outputting test algorithm pattern data, a terminal conversion device 21 for allocating an output signal of the ALPG 20 to a terminal of an actual LSI under test, and a logic pattern generator 22 for generating logic pattern data for a logic circuit. , An OR circuit 23 that synthesizes test algorithm pattern data and logic pattern data and outputs as test pattern data, and sets actual signal output timing, signal level, etc. based on the test pattern data and outputs as a test signal. The test signal output circuit 24 and a test head 25 for applying a test signal to the LSI under test 26 are provided.

Next, the general operation will be described. First, ALPG
20 generates a test algorithm pattern for the memory circuit based on the written program and outputs it to the terminal conversion device 21. As a result, the terminal conversion device 21 sends the test algorithm pattern data to the actual LSI 2 under test.
It is output to the logical sum circuit 23 in a state corresponding to the terminal of No. 6.

On the other hand, the logic pattern generator 22 generates logic pattern data for peripheral logic circuits in order to access the memory circuit and outputs it to the OR circuit 23. As a result, the logical sum circuit 23 synthesizes the logic pattern data for accessing the memory circuit built in the LSI under test 26 and the test algorithm pattern data for testing the memory circuit to synthesize a test signal as test pattern data. Output to the output circuit 24.

The test signal output circuit 24 sets the signal voltage level, the signal inversion timing, etc., and shapes the waveform based on the test pattern data, and outputs the result to the test head 25.

As a result, a test signal is applied to the LSI under test 26 via the test head 25, and the LSI under test 26 is tested.
A test of the memory circuit built in is performed. by the way,
Since ALPG is expensive, there is also established a technique of converting a memory pattern into a logic pattern by a logic pattern generator by software without the ALPG, developing the logic pattern, and testing.

FIG. 5 shows a schematic block diagram of a conventional memory test apparatus for performing a memory test using a logic pattern generator without ALPG. The memory test apparatus includes a host computer 30 that controls a logic pattern generator.
And a logic pattern generator 31 for generating a test logic pattern for a memory circuit and a logic circuit built in the LSI under test 34, and setting an actual signal output timing, a signal level, etc. based on the test logic pattern as a test signal. A test signal output circuit 32 for outputting and a test head 33 for applying a test signal to the LSI under test 34 are provided.

Next, the general operation will be described. First, the host computer 30 outputs various data and control data for generating a test logic pattern corresponding to the LSI under test 34 to the logic pattern generator 31.

As a result, the logic pattern generator 31
Is a test signal output circuit 32 for a test logic pattern for a memory circuit and a logic circuit built in the LSI under test 34.
Output to.

The test signal output circuit 32 sets the signal voltage level, the signal inversion timing, etc., and shapes the waveform based on the test logic pattern, and outputs it to the test head 33.

As a result, from the test head 33 to the L to be tested.
A test signal is applied to SI 34, and the memory circuit of LSI 34 is tested.

[0015]

L having a memory circuit
For testing SI memory circuits, it is common to use a memory test method having ALPG as a memory test method. However, there has been a problem that it becomes very expensive to configure the device so that a high-speed real-time test can be performed due to high integration and high speed of the LSI under test.

On the other hand, when a memory pattern is converted into a logic pattern by software and developed for testing, the memory area size of the logic pattern generator, the capacity of the external storage device, etc. are limited, and a huge capacity is required. There is a problem that the test cannot be performed using the pattern.

Therefore, an object of the present invention is to provide a memory test method capable of handling a large amount of test pattern data in real time without using ALPG.

[0018]

[Means for Solving the Problems]
Therefore, the present invention stores basic memory test pattern data.
The basic memory test pattern data
Partial memory test pattern data
Basic memory to output data Test pattern data storage output
The partial basic memory test pattern different from the step (2)
Parallel to each logic pattern data
A plurality of test pattern conversion steps for converting and outputting (3_-1~
Three_-n) And the corresponding test pattern conversion step (3_-1~
Three_-n) Output the logic pattern data
Multiple temporary storage steps (4_-1~ 4_-n, 13_-1
~ 13_-n) And a plurality of the temporary storage steps (4_-1~ 4_-n，
Thirteen _-1~ 13_-n) The logic pattern data stored in
Output step (6, 14) for sequentially outputting the data, and the output
Logic pattern data output by process (6, 14)
Test process (7) for testing the device under test based on the data
10 to 10) are provided.

[0019]

According to the present invention, the basic memory test pattern data storage / output step (2) stores the basic memory test pattern data and converts the partial basic memory test pattern data into each test pattern conversion step (3 _-1 to 3 _{-3). -n} ).

As a result, each test pattern conversion step (3 _-1
3 _-n ) converts the input partial basic memory test pattern data into logic pattern data and outputs the logic pattern data in parallel.

Each temporary storage step (4 _-1 to 4 _-n , 13 _-1 to 1)
3 _-n ) is the corresponding test pattern conversion process (3 _{-1 to} 3 _-n ).
The logic pattern data output by is stored.

As a result, a plurality of output steps (6, 14) are performed.
Temporary storage process (4_-1~ 4_-n, 13 _-1~ 13_-n) Remember
Test patterns (7
10 to 10), and the test process (7 to 10)
Of the device under test based on the logic pattern data
Perform the test.

Therefore, if the post-conversion capacity of the partial basic memory test pattern data given to each test pattern conversion step is set to a capacity that is sufficiently smaller than the storage capacity of each test pattern conversion step, the parallel processing will result in ALPG. It is possible to perform a memory test in real time without using.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 shows a schematic block diagram of a memory test apparatus according to the first embodiment.

The memory test apparatus stores a host computer 1 for controlling the entire apparatus and a basic memory test pattern which is the content to be tested, and a partial basic memory which is a part of the basic memory test pattern under the control of the host computer 1. A basic memory test pattern storage unit 2 for outputting a test pattern, a data conversion unit 5 for logically expanding the basic memory test pattern stored in the basic memory test pattern storage unit 2 and outputting it as memory test logic pattern data, and data. The LSI under test 11 to which the memory test logic pattern data output by the conversion unit 5 should be supplied
, A master timing generator 7 for generating a basic clock signal for timing various processes, a test logic pattern of the LSI under test 11 based on the basic clock signal and the memory test logic pattern data. A logic pattern generator 8 for generating data, a test signal output circuit 9 for setting actual signal output timing, signal level, etc. based on the test logic pattern data and outputting as a test signal, and applying the test signal to the LSI under test 11. And a test head 10 for performing the test.

The data converter 5 converts the first to nth memory test pattern conversion circuits 3 _-1 to 3 to convert the memory logic pattern data based on the partial basic memory test pattern which is a part of the input basic memory test pattern. _-n ,
A memory logic pattern data which is a conversion result of each partial basic memory test pattern is stored, and the first to nth temporary storage registers 4 _-1 to 4 _-n functioning as a shift register as a whole are provided. Has been done.

First to nth temporary storage registers 4 _-1 to 4
_-n is provided with a pattern number confirmation register 4A for storing information indicating which part of the original basic memory test pattern the memory logic pattern data stored in the temporary storage register corresponds to. .

Next, the operation will be described. In the following, 4
Description will be made assuming that a k-word memory circuit is tested with a galloping pattern.

In this case, the capacity of the memory test logic pattern to be finally output is about 50 M patterns. Therefore, in this embodiment, the memory capacity for processing in each memory test pattern conversion circuit is 1 M pattern memory. The test logic pattern is set to be processable, and the memory capacity of the temporary storage register is set to a capacity of about 1M pattern in terms of the memory test logic pattern.

When five combinations of the memory test pattern conversion circuit and the corresponding temporary storage registers are provided (n = 5), that is, the first to fifth memory test pattern conversion circuits 3 _-1 to 3 _{-3. -5} and first to fifth temporary storage registers 4 _-1 to 4 _-5 .

First, the host computer 1 and the basic memory test pattern storage unit 2 are controlled to convert (expand) about 1 of the stored basic memory test patterns.
Different partial memory test patterns corresponding to the M pattern are respectively provided in the first to fifth memory test pattern conversion circuits 3 _-1.
Output to ~ _3-5 .

First to fifth memory test pattern conversion circuits 3
_{-1 to} 3 _-5 respectively convert the input partial basic memory test patterns into memory logic pattern data in parallel and sequentially store them in the corresponding temporary storage registers 4 _-1 to 4 _-5 . At this time, in which pattern number confirmation register 4A of each temporary storage register 4 _-1 to 4 _-5 corresponds to which part of the original basic memory test pattern the memory logic pattern data stored in the temporary storage register corresponds to. Is stored.

More specifically, a partial basic memory test pattern corresponding to the first part of the basic memory test pattern is input to the first memory test pattern conversion circuit 3 _-1 ,
The second partial memory test pattern conversion circuit 3-2 receives the next partial basic memory test pattern that is continuous with the partial basic memory test pattern input to the first memory test pattern conversion circuit 3-1 of the basic memory test pattern. It In the same manner, the sequential partial basic memory test patterns are similarly input to the respective memory test pattern conversion circuits 3 _{-3 to} 3 _-5 .

When the conversion in the first memory test pattern conversion circuit 3 _-1 is completed and the 1M pattern memory logic pattern data is stored in the first temporary storage register 4 _-1 , this memory logic pattern data is selected. Is output to.

[0035] Thus selection circuit is configured to select the terminal to be tested to be supplied with memory logic pattern data LSI 11, the memory logic pattern data input from the first temporary storage register _4-1 to the logic pattern generator 8 Output.

As a result, the logic pattern generator 8
Generates peripheral logic pattern data corresponding to various conditions for the peripheral logic circuit for accessing the memory circuit to be tested of the LSI under test 11 based on the basic clock signal of the master timing generator 7.
The test logic pattern data is output to the test signal output circuit 9 after being combined with the input memory logic pattern data.

The test signal output circuit 9 sets the actual signal output timing, signal level, etc. based on the test logic pattern data and outputs it to the test head 10 as a test signal.

As a result, a test signal is applied to the LSI under test 11 via the test head 10 and the LS under test is tested.
The test corresponding to the first part of the basic memory test pattern of the memory circuit built in I11 is performed.

On the other hand, by the first temporary register _4-1 has finished output all memory logic pattern data to the selecting circuit 6, the second to fifth memory test pattern conversion circuit 3 _-2 -3 _-5 The processing is also completed, and since the converted memory logic patterns are already stored in the second to fifth temporary storage registers _4-2 to _4-5 , the memory logic pattern data of the second temporary storage register _4-2 is stored. It is transferred to the first temporary storage register 4 _-1 .

Similarly, the memory logic pattern data in the third temporary storage register 4 _-3 is transferred to the second temporary storage register 4 _-2, and the memory logic pattern data in the fourth temporary storage register 4 _-4 is stored in the third temporary storage register 4 _-4. It is transferred to the storage register 4 _-3, and the memory logic pattern data of the fifth temporary storage register 4 _-5 is transferred to the fourth temporary storage register 4 _-4 .

In parallel with this, the first to fifth memory test pattern conversion circuits 3 _{-1 to} 3 _-5, which have completed the processing, are each provided with five partial basic memory test patterns to be processed next. It is transferred from the pattern storage unit 2.

As a result, the first to fifth memory test pattern conversion circuits 3 _{-1 to} 3 _-5 again convert the partial basic memory test pattern into the memory logic pattern data, and the corresponding temporary storage registers 4 _-1 to 4 -4 in sequence. _-Remember at _-5 .

Similarly, the first to fifth memory test pattern conversion circuits 3 _{-1 to} 3 _-5 perform data conversion processing 10 times each, and perform data conversion for a total of 50 M patterns.

As described above, according to the present embodiment, each memory test pattern conversion circuit converts the partial memory test pattern in parallel. Therefore, even if the ALPG is not provided, a large capacity memory test pattern is used. , Tested in real time L
It is possible to test the memory circuit built in the SI. Second Embodiment In the first embodiment, the first to nth temporary storage registers 4 _-1 to 4- _n are made to function as a shift register as a whole, but in the second embodiment, the first embodiment is used. The nth temporary storage registers operate in parallel, and the selection circuit sequentially selects the temporary storage registers to transfer the memory logic pattern data.

FIG. 3 shows a schematic block diagram of the memory test apparatus of the second embodiment. In FIG. 3, the same parts as those in the first embodiment of FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 3, the point different from the first embodiment of FIG. 2 is that in the data conversion section 12, the first to fifth memory test pattern conversion circuits 3 _{-1 to} 3 _-5 are serially connected respectively. First to nth temporary storage registers 13 _{-1 to} 13 _-5 are provided, and further, first to nth temporary storage registers 13 _{-1 to} 13 are provided.
_-5 , a selection circuit 14 for selecting any one of the temporary storage registers and selecting a terminal of the LSI under test to which the memory logic pattern data stored in the temporary storage register is to be supplied. .

Next, the operation will be described. In the following description, a case will be described in which a 4k word memory circuit is tested with a galloping pattern as in the first embodiment. Therefore, also in the second embodiment, the memory capacity for processing in each of the memory test pattern conversion circuits 3 _{-1 to} 3 _-5 is set to the extent that a 1 M pattern of memory test logic pattern can be processed, and each temporary storage register 13 _-1
A capacity of about 1M pattern -13 _-5 memory capacity in the logic pattern conversion memory test.

First, by controlling the host computer 1 and the basic memory test pattern storage unit 2 and converting (developing) the stored basic memory test patterns, approximately 1M patterns of different partial memory test patterns are obtained. 1 to 5 memory test pattern conversion circuit 3
Output to -1 to 3-5.

First to fifth memory test pattern conversion circuits 3
_{-1 to} 3 _-5 respectively convert the input partial basic memory test patterns into memory logic pattern data in parallel and sequentially store them in the corresponding temporary storage registers 13 _{-1 to} 13 _-5 . At this time, which part of the original basic memory test pattern the memory logic pattern data stored in the temporary storage register corresponds to in each pattern number confirmation register 4A of each temporary storage register 13 _{-1 to} 13 _-5 . Is stored.

More specifically, a partial basic memory test pattern corresponding to the first part of the basic memory test pattern is input to the first memory test pattern conversion circuit _3-1 ,
The second partial memory test pattern conversion circuit 3 _-2 receives the next partial basic memory test pattern that is continuous with the partial basic memory test pattern input to the first memory test pattern conversion circuit 3 _-1 of the basic memory test pattern. It In the same manner, the sequential partial basic memory test patterns are similarly input to the respective memory test pattern conversion circuits 3 _{-3 to} 3 _-5 .

The conversion in the first memory test pattern conversion circuit 3-1 is completed, and the memory logic pattern data of the 1M pattern is stored in the first temporary storage register 13 _-1 . Selection circuit 14 by Re here, first select the temporary register 13 _-1 to output the memory logic pattern data in the first temporary register 13 _-1.

When the memory logic pattern data is input, the selection circuit 14 causes the first temporary storage register 1
The terminal of the LSI under test 11 to which the memory logic pattern data of 3 ₋₁ is to be supplied is selected, and the memory logic pattern data input from the first temporary storage register 4 ₋₁ is output to the logic pattern generator 8.

As a result, the logic pattern generator 8
Generates peripheral logic pattern data corresponding to various conditions for the peripheral logic circuit for accessing the memory circuit to be tested of the LSI under test 11 based on the basic clock signal of the master timing generator 7.
The test logic pattern data is output to the test signal output circuit 9 after being combined with the input memory logic pattern data.

The test signal output circuit 9 sets the actual signal output timing, signal level, etc. based on the test logic pattern data and outputs it to the test head 10 as a test signal.

As a result, the test signal is applied to the LSI 11 under test via the test head 10, and the LS under test is tested.
The test corresponding to the first part of the basic memory test pattern of the memory circuit built in I11 is performed.

Meanwhile, by the first temporary register _4-1 has finished output all memory logic pattern data to the selecting circuit 6, the second to fifth memory test pattern conversion circuit 3 _-2 -3 _-5 The processing is also completed, and the converted memory logic pattern is stored in the second to fifth temporary storage registers 13 _{-2 to} 13 _-5 .

Then, the selection circuit 14 next selects the second temporary storage register 13 _-2 , and the second temporary storage register 13 _-2.
The memory logic pattern data of is output. When the memory logic pattern data is input, the selection circuit 14 is configured to select the terminal to be tested LSI11 to be supplied with memory logic pattern data in the second temporary register 13 _-2 second temporary register 13 _{- The} memory logic pattern data input from ₁ is output to the logic pattern generator 8.

Thereafter, the selection circuit 14 sequentially selects the temporary storage registers to output the memory logic pattern. In parallel with this, the first to fifth memory test pattern conversion circuits 3-1 to 3-5, which have completed the processing, respectively include five partial basic memory test patterns to be processed next, in the basic memory test pattern storage unit. Transferred from 2.

As a result, the first to fifth memory test pattern conversion circuits 3 _{-1 to} 3 _-5 again convert the partial basic memory test pattern into the memory logic pattern data, and the corresponding temporary storage registers 13 _{-1 to} 13 _{-1 in} order. _-Remember at _-5 .

Similarly, the first to fifth memory test pattern conversion circuits 3 _{-1 to} 3 _-5 perform data conversion processing 10 times each, and perform data conversion for a total of 50 M patterns.

As described above, according to the second embodiment, each memory test pattern conversion circuit converts the partial memory test pattern in parallel, and the selection circuit 14 sequentially outputs the necessary memory logic pattern data. So AL
Even if the PG is not provided, it is possible to test the memory circuit built in the LSI under test in real time using a large capacity memory test pattern.

[0062]

According to the present invention, the capacity after the conversion of the partial basic memory test pattern data given to each test pattern conversion step is made sufficiently smaller than the storage capacity of each test pattern conversion step, By performing the parallel processing, it is possible to test the memory circuit built in the LSI under test in real time using a large-capacity memory test pattern without using ALPG.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment.

FIG. 2 is a block diagram showing a more specific configuration of the first embodiment.

FIG. 3 is a block diagram showing a specific configuration of the second embodiment.

FIG. 4 is a block diagram showing a schematic configuration of a conventional memory test apparatus having an ALPG.

FIG. 5 is a block diagram showing a schematic configuration of a conventional memory test apparatus having no ALPG.

[Explanation of symbols]

1 ... Host computer 2 ... Basic memory test pattern storage unit 3 _{-1 to} 3 _-n ... Memory test pattern conversion circuit 4 _-1 to 4- _n ... Temporary storage register 4A ... Pattern number confirmation register 5, 5 '... Data conversion unit 6 ... selection circuit 7 ... master timing circuit 8 ... logic pattern generator 9 ... test signal output circuit 10 ... test head 11 ... tested LSI 13 _-1 to 13 _-5 ... temporary storage register 14 ... selection circuit

Claims (3)

[Claims] 1. A basic memory test pattern data storing and outputting step (2) of storing basic memory test pattern data and outputting partial basic memory test pattern data which are different parts of the basic memory test pattern data. A plurality of test pattern conversion steps (3 _{-1 to} 3 _-n ) of converting the different partial basic memory test pattern data into logic pattern data in parallel and outputting the same, and the corresponding test pattern conversion step. A plurality of temporary storage steps (4 _-1 to 4 _-n , 13 _{-1 to} 13 _-n ) for respectively storing the logic pattern data and the logic pattern data stored in the plurality of temporary storage steps are sequentially output. Output step (6, 14) and logic pattern data output by the output step (6, 14) Based on the memory testing method characterized by comprising a test step of testing the device under test (7-10), a. 2. The memory test method according to claim 1,
And the plurality of temporary storage steps are connected to the output step.
First temporary storage step (4 _-1), And a second to a second serially connected to the first temporary storage step.
Nth temporary storage step (4 _-2~ 4_-n), And the second to n-th temporary storage steps (4_-2~ 4_-n) Is the front stage
Outputs the logic pattern data of the temporary storage process of
Temporary transferred to (6) or connected to the previous stage
Stored in the temporary storage process when transferred to the storage process
The logic pattern data that is being connected to the previous stage
Memory test characterized by transferring to a temporary storage process
Test method. 3. The memory test method according to claim 1, wherein the output step (14) includes the temporary storage steps (1).
3 _{-1 to} 13 _-n ) are sequentially selected to sequentially output the logic pattern data stored in the selected temporary storage step.