JPH1010195A - Tester and test method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the circuitry of a semiconductor integrated circuit comprising logic elements and memory elements while reducing the cost. SOLUTION: At the time of testing a memory element in a semiconductor device 45 to be tested, the semiconductor device 45 is fed with a logic test pattern generated from a logic pattern generating section 41 and a memory test pattern delivered from a host computer 32 and a comparison circuit decides whether the semiconductor device 45 is acceptable or not based on the output state thereof. The decision result is selected by an output signal selection circuit 49 and an address selection circuit 46 stores the decision result in a memory circuit 47 based on an address signal extracted from a memory test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test method and a test apparatus for testing a semiconductor integrated circuit having a logic element and a memory element. In recent years, test devices for semiconductor integrated circuits have been subdivided into dedicated logic devices and dedicated memory devices. However, integration of devices under test has progressed, and for example, a cache RAM (Random Access Memory) has been developed.
Logic elements and memory elements are mixed in the form of y). In this case, in testing the memory element, it is necessary to generate a test pattern including an address, and the circuit configuration is complicated and expensive. Therefore, a low-cost test apparatus is desired.

[0002]

2. Description of the Related Art Conventionally, in order to test a memory circuit in which a logic element and a memory element are mixed, a method of performing a test together with a failure analysis in a test apparatus having a test pattern generator dedicated to a memory test is generally used. It is a target.

FIG. 4 is a block diagram of a conventional semiconductor integrated circuit test apparatus. Test apparatus 11 shown in FIG.
Is an external storage device (DISK) 13 that stores a test program in a host computer 12, for example, on a disk medium.
An external input device (CRT) 14 for creating, changing, and executing a test program, and an external storage device (M) for storing the test program on a magnetic tape, for example.
T) 15 and an output device (LP) 16 for displaying a test result and a test program by, for example, a line printer.
7 is connected. A keyboard 18 is connected to the external input device (CRT) 14, and a mouse 19 is connected to the keyboard 18 as appropriate.

The host computer 12 has a timing generator (TG) 20, a logic pattern generator (PG) 21, a waveform shaping circuit (FC) 22, and a voltage generator / generator.
A comparison circuit (VI / VO) 23, a test head 24, a test pattern generator (ALPG) 25 dedicated to memory test, a memory test signal connection switch (PDS) 26, a storage circuit 27, a write control circuit 28, and an output signal selection circuit 29 Are connected by a bus 17 respectively.

In this case, a timing generator (TG) 20
Is connected so as to supply a timing signal to the logic pattern generator 21 and the waveform shaping circuit 22, and the output signal of the logic pattern generator (PG) 21 and the output signal of the memory test signal connection switch (PDS) 26 are ORed. Circuit 3
Connected to be input to 0. Then, the output signal of the OR circuit 30 is used to generate a voltage through the waveform shaping circuit 22.
It is connected so as to be inputted to the comparison circuit (VI / VO) 23 and the voltage generation / comparison circuit (VI / VO) 23
And a test head 24 on which a semiconductor device in which a logic element and a memory element as test objects are mixed is mounted.

A test pattern generator dedicated to the memory test
(ALPG) 25 is a row (ROW) address calculation circuit
25a₁, Row address generation circuit 25a_Two,
Column address calculation circuit 26a₁, Column address calculation
Circuit 26b₁, Extension address calculation circuit 26c₁, Extension
Dress generation circuit 26c_Two, Data signal calculation circuit 27
d ₁, Data signal calculation circuit 27d_Two, Control signal calculation circuit
28e₁, Control signal generation circuit 28e_TwoIs provided.

[0007] The test pattern generator (ALPG) 25 dedicated to the memory test converts a memory test pattern including the generated address into a memory test signal connection switch (PD).
S) Output to the storage circuit 27 at the same time.
The memory test signal connection switch (PDS) 26 outputs the input memory test pattern to the OR circuit 30 for writing to the memory element to be tested, and outputs it to the voltage generation / comparison circuit 23 for comparison by reading. .

On the other hand, the storage circuit 27 and the write control circuit 2
8. The output signal selection circuit 29 is composed of a circuit for each bit, and a voltage generation / comparison circuit (VI / VO) 2
The comparison result from the comparison circuit No. 3 is output to the output signal selection circuit 29 for each bit, and the output of the output signal selection circuit 29 is stored in the storage circuit 27 under the write control by the write control circuit 28.

FIG. 5 is an explanatory diagram of a signal flow of the memory test pattern shown in FIG. The memory test signal connection switch (PDS) 26 shown in FIG. 5 has a selection signal distribution circuit 26a and a selection circuit 26b, and also has an ALPG signal distribution circuit 25f of a memory test dedicated test pattern generator (ALPG) 25. 5 generated in the test pattern generator (ALPG) 25 dedicated to the memory test.
The control signals from the host computer 12 are input to the selection signal distribution circuit 26a of the memory test signal connection switch (PDS) 26 via the ALPG signal distribution circuit 25f. Is input to the corresponding selection circuit 26b. And
The selected signal is input to the corresponding OR circuit 30, and the OR circuit 30 outputs a signal (1 to n) for each tester channel.

The above-described test apparatus 11 is provided with a logic pattern generator 21 for testing only a logic element on a semiconductor device (mixed with logic elements and memory elements) mounted on a test head 24. The generated logic pattern is the logical sum circuit 30, the waveform shaping circuit (F
C) A logic pattern is input to the logic element from the test head 24 via the voltage generation / comparison circuit (VI / VO) 23 and the voltage generation / comparison circuit (VI / VO) 23 compares the logic pattern in its output state. Pass / fail is determined by the circuit.

[0011] When a memory element is tested,
A logic pattern from a logic pattern generator (PG) 21 is input to a logic element around the memory element via a logical sum circuit 30 and the like, and a memory test dedicated test pattern generator 25 generates a memory element. The obtained memory test pattern is input (stored) via a memory test signal connection switch (PDS) 26, an OR circuit 30, and the like. Then, the content stored in the memory element is read out, input to the voltage generation / comparison circuit 23, and compared with the expected value (write memory test pattern) input from the memory test signal connection switch (PDS) 26. The comparison result is input to the output signal selection circuit 29 for each channel (1 to n).

Then, for example, only the defective bit selected by the output signal selection circuit 29 is selected, and the memory control circuit area is assigned to the corresponding channel area (1 to n) of the storage circuit 27 via the write control circuit 28. It is stored in accordance with the address signal from the test pattern generator 25. By reading the storage circuit 27, it is possible to determine the defect of the memory element of the semiconductor device under test.

[0013]

However, the test apparatus 11 as described above includes various circuits 25a for the test pattern generator 25 for memory test to generate test patterns.
Since comprise _1, 25a _2, etc., together with a circuit configuration is complicated, and expensive there test pattern calculation process from having to operate in the memory device and the same cycle must be performed in the middle pattern generator There is a problem.

On the other hand, a test apparatus having only a logic-only test pattern generator (for example, Japanese Patent Application Laid-Open No. 61-1424)
No. 76), it is possible to execute a memory element test by generating a logic test pattern corresponding to a memory from a soft memory test pattern generation tool, but it is not possible to execute a failure analysis in real time. That is, since the address is not included in the data signal of the memory test pattern, a failure analysis process for extracting only the address, input, and output data related to the memory test from the failure information in the 0/1 format after the completion of the memory test is performed. Therefore, there is a problem that the failure analysis processing time becomes enormous, and the memory test can be performed substantially, but the failure analysis cannot be performed, and the defective memory element cannot be specified and the rescue information cannot be output.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a test method and a test apparatus for a semiconductor integrated circuit which can simplify the circuit configuration and reduce the cost.

[0016]

According to a first aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit having a logic element and a memory element to be tested, wherein the logic element or the logic element and the logic element are tested. A logic test pattern for testing a memory element is generated, a control signal for generating the logic test pattern is transmitted, and a memory corresponding logic test pattern including address data corresponding to the memory element is supplied. The logic element, the logic test pattern supplied to the memory element, the logic test pattern corresponding to the memory, the logic element and the output state of the memory element are used to determine pass / fail of the logic element. Stored in the storage means according to a predetermined address for each memory unit of It extracts the address from the memory corresponding logic test pattern, when said storage means stores a judgment result, constitute a method of testing a semiconductor integrated circuit to the address supplied to the memory means.

According to a second aspect of the present invention, in the semiconductor integrated circuit test device including a logic element and a memory element to be tested, a logic for generating the logic element or a logic test pattern for testing the logic element and the memory element is provided. Main control means for transmitting a control signal for generating the logic test pattern to the logic pattern generation means and supplying a memory-compatible logic test pattern including address data corresponding to the memory element; The logic element, the logic test pattern supplied to the memory element, the logic element with respect to the memory-corresponding logic test pattern, judgment means for judging pass / fail from the output state of the memory element, and a judgment result for the memory element, For each predetermined memory unit of the memory element, A memory unit that stores the address in accordance with the address of the memory control logic test pattern supplied from the main control unit, and when the storage unit stores the determination result, the address is stored in the storage unit. And a supply address extracting means for configuring a test apparatus for a semiconductor integrated circuit.

According to a third aspect of the present invention, there is provided a test result integrated storage unit according to the second embodiment, wherein the storage contents stored in the storage unit are integrated and stored in the same structure as the memory element. As described above, according to the first and second aspects of the present invention, when testing a memory element, the logic test pattern generated by the logic pattern generation means and the memory-compatible logic test pattern supplied by the main control means are compared with the logic element and the logic element. The data is supplied to the memory element, and the determination means determines pass / fail based on the output state, and the address extraction means stores the determination result in the storage means at the address extracted from the logic test pattern corresponding to the memory. As a result, the test can be performed without using the pattern generator dedicated to the memory test, and the determination result is specified and stored in the address, so that the failure analysis can be performed in real time, thereby simplifying the circuit configuration and reducing the cost. Can be achieved.

According to the third aspect of the present invention, the storage contents of the determination result of the memory element are integrated and stored by the test result integration storage means having the same structure as the memory element. As a result, it is possible to facilitate failure analysis and failure relief.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a configuration diagram of an embodiment of the present invention. FIG. 1 shows a block diagram of a test device 31 for a semiconductor integrated circuit. A host computer 32 serving as a main control means has an external storage device (DISK) 33, an external input device (CRT) 34, and an external storage device (magnet). Tape: MT) 35, output device (line printer: LP)
36 are connected by a bus 37 and an external input device (CRT) 3
4 is connected to a keyboard 38 and a mouse 39 as appropriate.

An external storage device (DISK) 33 stores a test program, and an external input device (CRT) 34
Is for creating and changing a test program using the keyboard 38 and the mouse 39. An external storage device (magnet tape: MT) 35 is for storing the created and changed test programs, and an output device (line printer: LP) 36 is for displaying test results and test programs. is there.

These configurations are the same as the above-described conventional one (FIG. 4), except that the host computer 32 of the present invention has a function of generating a memory-corresponding logic test pattern for memory test (hereinafter referred to as a memory test pattern). The memory test pattern has a function of including an address and address data for defining a weight of the address (selection order of the memory element) for defining a memory configuration of a storage circuit described later.

The host computer 32 has a timing generator (TG) 40, a logic pattern generator (PG) 41 as a logic pattern generating means, a waveform shaping circuit (FC) 42, a voltage generation / comparison circuit (VI / VO)
43, a test head 44 is connected by a bus 37.

The logic pattern generator (PG) 41
A logic test pattern is generated by a control signal from the host computer 12 and output to the waveform shaping circuit (FC) 42, and a memory element test pattern supplied from the host computer 12 is output to the waveform shaping circuit (FC) 42. The logic pattern generator (PG) 41 and the waveform shaping circuit (FC) 42 include a timing generator (TG) 4
Synchronization is achieved by a timing signal from 0.

Voltage generation / comparison circuit (VI / VO) 43
Means that the voltage generation circuit is a waveform shaping circuit (FC) 4
The test pattern outputted from the test pattern 2 is output to the test head 44 at a voltage level corresponding to the semiconductor device 45 to be tested, and the comparison circuit operates as a judging means to determine the output state and expected value of the semiconductor device 45 after input of the test pattern. (An output value that would normally be output in accordance with the input test pattern) and output a comparison determination result.

The test head 44 is mounted with a semiconductor device 45 on which a semiconductor integrated circuit having a logic element to be tested and a memory element is formed. Further, the host computer 12 is connected to an address selection unit 46 as an address extraction unit, a storage circuit 47, a write control circuit 48, an output signal selection circuit 49, and an integrated storage circuit 50 as a test result integrated storage unit via a bus 37. . In this case, the storage circuit 47, the write control circuit 48,
The output signal selection circuit 49 forms a storage unit.

The address selection circuit 46 extracts address data in units of individual steps from the memory test pattern sent from the host computer 32 via the logic pattern generator (PG) 41, and extracts the test object from the weight of each address. Rearrange in the selection order of the memory elements of
An address signal corresponding to the memory test pattern is output to the storage circuit 47 in response to a control signal from the host computer 32.

The address selection circuit 46, the output signal selection circuit 49, the write control circuit 48, and the storage circuit 47 are respectively arranged from the first pin to the nth pin corresponding to the device channel number. It corresponds to a unit (1 bit to n bits). In this case, the channel numbers can be freely changed by changing the matrix arrangement in the address selection circuit 46 and the output signal selection circuit 49. That is, the host computer 32 determines the correspondence between the output signal arrangement of the semiconductor device 45 via the comparison circuit of the voltage generation / comparison circuit (VI / VO) 43 and the input signal to the write control circuit 48 by the output signal selection circuit 49. It is controlled by the state.

The output signal selection circuit 49 generates a voltage
The comparison determination results of all the channels in the comparison circuit of the comparison circuit (VI / VO) 43 are the first to n-th circuits 49 _1, respectively.
To 49 _n to select whether or not to write them into the storage circuit 47. For example, the storage circuit 47 (47) only outputs the comparison result of the comparison circuit determined to be defective.
Output to ₁ to 47 _n) are selected to be stored in the write control circuit 48 (48 ₁ ~48 _n). Then, the write control circuit 48 (48 _{1 to} 48 _n ) converts the input output signal from the output signal selection circuit 49 (49 ₁ to 49 _n ) from the corresponding write control circuit 48 _{1 to} 48 _n to the storage circuit 47 (47). _{1 to} 47 _n ). At this time, the memory circuit 47 (47 ₁ ) is written by the address selection circuit 46.
47 _n ) is supplied from the address selection circuit 46 and the above-described failure determination result is stored at the specified address.

On the other hand, in the integrated storage circuit 50, the counting and editing methods are specified by the host computer 32, and the storage circuit 47 (47 _{1 to} 47 _n ) is stipulated in accordance with these rules.
And totals and stores the memory defect information for each output unit. By reading out the storage content of the integrated storage circuit 50, it can be used for determination of redundant information and the like, and relief can be easily performed.

As described above, the test apparatus 31 enables the signal selectivity of the address selection circuit 46 and the output signal selection circuit 49 to be connected to any signal channel under the control of the host computer 32. Tests can be easily performed on a semiconductor device 45 having various types of memory elements with a simple configuration, and a real-time memory test and its failure analysis processing can be performed at low cost without having a dedicated memory test pattern generator. It can be realized in.

Here, FIG. 2 is an explanatory diagram of writing to the storage circuit of FIG. FIG. 3 is an explanatory diagram of an address signal supply to the storage circuit in FIG. First, FIGS. 2 and 3
In FIG. 2, the comparison circuit of the voltage generation / comparison circuit (VI / VO) 43 in FIG. 2 outputs the comparison determination result for each of the channels 1 to N (pins 1 to n of the semiconductor device) of the device and selects the output signal The circuit section 49 (49 ₁ to 4
9 _n ) is input to each output signal selection circuit unit 51, and each selection signal distribution circuit unit 52 receives one output signal (defective result signal) D <b> 0 to Dn in the output signal selection circuit unit 51 by a control signal from the host computer 32. select those to be output to the write control circuit 48 (48 ₁ ~48 _n). The output signal selection circuit 51 has a non-determination terminal.

In FIG. 3, a logic pattern generator 41 outputs an address signal of a memory test pattern for each of channels 1 to N of the device to an address selection circuit 4.
6, and the selection signal distribution circuit 54 outputs one address signal (X0) in the address signal selection circuit 53 to the storage circuit 47 according to a control signal from the host computer 32. The address signals (X1-X
n, Y0 to Yn, Z0 to Zn) are stored in the storage circuit 47 (47 ₁
To 47 _n ). Note that the address signal selection circuit unit 53 has a zero fixed terminal.

The operation of the test apparatus 31 will now be described. First, an external storage device (magnet tape: M
T) 35 stores the logic test information for the memory test provided from the CAD information, and is loaded into the external storage device (DISK) 33 from this. The external storage device (DISK) 33 sends a CAD to the host computer 32.
The host computer 32 starts an array conversion program for changing the arrangement of memory signals for information.
Causes an executable memory test pattern to be generated.

That is, the host computer 32 causes the logic pattern generator (PG) 41 to execute the test program main body which is previously input from the external input device (CRT) 34 and stored in the external storage device (DISK) 33. While transferring the pattern, the address selection circuit 46
Transfer the test conditions to each unit. At this time, the logic pattern generator (PG) 41 generates a logic test pattern corresponding to the logic element around the memory element.

As described above, the external storage device (DISK) 33
Is executed, the input signal is supplied to the memory element of the semiconductor device 45 to be tested and the peripheral logic elements in units of individual steps of the logic test pattern and the memory test pattern.
The output signals from the five memory elements are input to the comparison circuit of the voltage generation / comparison circuit (VI / VO) 43. Further, an address signal in the input signal of each step of the memory test pattern supplied to the semiconductor device 45 is extracted by the address selection circuit 46 as shown in FIG.

On the other hand, by executing the test program itself,
The output signal output from the semiconductor device 45 is compared with the expected value in a comparison circuit of a voltage generation / comparison circuit (VI / VO), and the quality of the output signal is determined for each output signal unit, as shown in FIG. Output signal selection circuit 49 (49 ₁ to 49
49 _n ) pass / fail result of each output signal unit (comparison judgment result)
Is delivered. The output signal selection circuit 49 (49 ₁ to 49
In _n), quality results of each output signal units are input becomes the write input control signal to the memory circuit 47 (47 ₁ ~47 _n) in the write control circuit 48 (48 ₁ ~48 _n), is determined to be defective Storage circuit 4 only for output signals
7 (47 _{1 to} 47 _n ) to write a signal (for example, “1”) indicating a defect to the address selection address.

Then, the storage circuit 47 (47 _{1 to} 47 _n )
In the integrated storage circuit 50, the memory failure information stored for each output unit is tabulated, edited, calculated, and stored.
The storage in the integrated storage circuit 50 is performed by the semiconductor device 45.
The same arrangement as that of the memory element of the above is performed, whereby it is possible to easily determine redundant information and the like, and to perform relief.

As a method for realizing the freedom of changing the matrix circuit arrangement in the address selection circuit 46 and the output signal selection circuit 49, the matrix arrangement definition section is detachable and exchangeable with the test apparatus 31 as a specific manual wiring board. Circuit configuration. In this case, the pin arrangement of the memory test pattern in the logic pattern format provided by the CAD information or the like by the array conversion software is additionally converted into the memory test pattern in the logic pattern format converted into a signal arrangement executable by the test apparatus 31. And use it. Thereby, the cost can be further reduced.

[0040]

As described above, according to the first and second aspects of the present invention, when a memory element is tested, a logic test pattern generated by the logic pattern generating means and a memory corresponding logic supplied by the main control means. The test pattern is supplied to the logic element and the memory element, and the determination means determines pass / fail based on the output state, and the determination result is stored in the storage means by the address extraction means at the address extracted from the logic test pattern corresponding to the memory. A test is performed without using a pattern generator dedicated to a memory test, and a determination result is specified by an address and stored. Therefore, a failure analysis can be performed in real time, thereby simplifying a circuit configuration and reducing costs. be able to.

According to the third aspect of the present invention, the storage contents of the determination result of the memory element are integrated and stored by the test result integration storage means having the same structure as the memory element, thereby facilitating the failure analysis and the defect relief. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of writing to a storage circuit in FIG. 1;

FIG. 3 is an explanatory diagram of an address signal supply to the storage circuit of FIG. 1;

FIG. 4 is a block diagram of a conventional semiconductor integrated circuit test apparatus.

FIG. 5 is an explanatory diagram of a signal flow of the memory test pattern of FIG. 4;

[Explanation of symbols]

 31 Test Apparatus 32 Host Computer 33 External Storage Device 34 External Input Device 35 Magnet Tape 36 Line Printer 40 Timing Generator 41 Logic Pattern Generator 42 Waveform Shaping Circuit 43 Voltage Generation / Comparison Circuit 44 Test Head 45 Semiconductor Device 46 Address Selection Circuit 47 Storage circuit 48 Write control circuit 49 Output signal selection circuit 50 Integrated storage circuit

Claims (3)

[Claims] 1. A method for testing a semiconductor integrated circuit having a logic element and a memory element to be tested, comprising: generating a logic test pattern for testing the logic element or the logic element and the memory element; A control signal for generating a pattern is transmitted, and a memory-corresponding logic test pattern including address data corresponding to the memory element is supplied. The logic element, the logic test pattern supplied to the memory element, and the memory correspondence Determining whether or not the logic element with respect to the logic test pattern is good or bad based on the output state of the memory element; storing the determination result for the memory element in storage means in accordance with a predetermined address for each predetermined memory unit of the memory element; Address from the logic test pattern corresponding to the memory When the storage means stores the determination result, a method of testing a semiconductor integrated circuit and supplying said address to said storing means. 2. A test apparatus for a semiconductor integrated circuit including a logic element and a memory element to be tested, wherein: a logic pattern generating means for generating a logic test pattern for testing the logic element or the logic element and the memory element Main control means for sending a control signal for generating the logic test pattern to the logic pattern generation means and supplying a memory-compatible logic test pattern including address data corresponding to the memory element; Determining means for determining whether or not the logic test pattern supplied to the memory element, the logic test pattern corresponding to the memory, and the output state of the memory element are good or bad; A specific address for each specific memory unit And an address extracted from the memory-corresponding logic test pattern supplied from the main control means, and supplies the address to the storage means when the storage means stores a determination result. A test apparatus for a semiconductor integrated circuit, comprising: an address extracting unit. 3. The test of a semiconductor integrated circuit according to claim 2, further comprising a test result integrated storage unit that integrates and stores the storage contents stored in the storage unit with the same structure of the memory element. apparatus.