JPH04346082A - Tester - Google Patents

Abstract

PURPOSE:To shorten the time required for setting test conditions for each pin, by grouping pins according to the test conditions and by setting data for an internal control register at once for each pin group. CONSTITUTION:Using a control bus 1, an address bus 2 and a data bus 3, control CPU 9 controls each PIN part 10. Each PIN part 10 comprises an address control element 4 conducting an address control, a test timing signal generator TG part 5, etc. The address control element 4 receives an input from the address bus 2, analyzes the content thereof and judges whether the element itself is selected. When it is selected, it makes an address inside the PIN part 10 and supplies it to the TG part 5 etc., so that the content of the data bus 3 can be taken in. When a group address is once set for all pins, accordingly, it is needed then only to set or alter test conditions for each group.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device having a plurality of pins, and more particularly to a test device having a per-pin architecture, in which each pin has a timing generator.

0002

[Prior Art] A conventional testing device is disclosed in U.S. Pat.
No. 6,852 “AUTOMATIC TEST SYS
TEM WITH ENHANCED PERFORM
ANCE OF TIMING GENERATORS
”, the Timing Gener, which is a component of each pin, is connected to the CPU bus that controls the device.
ators, Vector Memory, Pin E
electronics are directly connected. Each of these components has a plurality of registers for setting test conditions, and the conditions can be set directly for each register from the CPU. For this purpose, the CPU bus has addresses for pin selection and register selection, data, and control signals.
U controls this bus to set test conditions.

0003

In a conventional test device, when setting test conditions, each pin has a setting location, so it is necessary to set the test conditions for each pin.

[0004] In a system with a small number of pins, the time required for this setting is small and does not pose a problem, but in a system with a large number of pins, the setting time is large, and the ratio of the condition setting time to the total test time becomes large. This will reduce the throughput of the test equipment. An object of the present invention is to provide a test device that can significantly shorten the time required to set test conditions for each pin of the test device, and further shorten the test time of a test object.

[0005]

[Means for Solving the Problems] In order to achieve the above object, a test device according to the present invention has a plurality of pins connected to a test object, and has a control device that sets test conditions for each pin. A test device having a register in each pin, comprising: a CPU for controlling the test device; a group address setting means for each pin for setting a common group address for each pin under the same test conditions; Group address determination means for each pin that determines whether or not a group to which the own pin belongs is specified based on an address output from the CPU, and the group address determination means determines that the group to which the own pin belongs is specified. When the CPU
The device is equipped with register writing means for each pin, which writes data representing the test conditions from the pin into the control register.

[0006] The address from the CPU preferably includes a group address indicating that the test conditions are the same;
Contains a register address that specifies the pin's internal control register.

[0007] The address from the CPU may further include a pin address specifying a pin number, and a pin address determining means may be provided for each pin to determine whether the pin address specifies the own pin. .

[0008] It is also possible to provide a dedicated bit in the group address to indicate the implementation of grouping, and to switch between pin designation using the group address and pin designation using the pin address, depending on the value of the dedicated bit. .

It is also possible to select pin designation using the pin address when the group address is a predetermined specific pattern, and to select pin designation using the group address when the group address is not a specific pattern.

[0010] A dedicated bit may be provided in the pin address to indicate that all pins are designated simultaneously. or,
When the pin address has a predetermined specific pattern, the pin address may designate all pins simultaneously. These front pin designations can also be employed independently of the group designation.

[0011]

[Operation] In actual testing, the test conditions are rarely different for each pin except in special cases, and when the pins are grouped according to the test conditions, there are from several types to more than ten types. In view of these circumstances, the present invention allows data setting of the internal control register to be performed at once for each of one or more pin groups for which the same test conditions are to be set.

Specifically, in order to determine whether the address specification from the CPU specifies the group to which each pin belongs, a register (group address setting means) is used to set the group address to which the own pin belongs. A group address is set in this register in advance, and the group address sent from the CPU and
The contents of this register are compared, and if they match, it is determined that the own pin is selected.

[0013] All pins perform this operation, and a plurality of selected pins simultaneously capture data on the CPU bus into the internal control register.

[0014] In this way, from the CPU side, once group addresses are set for all pins, the test conditions can be set and changed for each group.

[0015] By making it possible to selectively perform group designation and individual pin designation, individual pin designation can be performed in the same way as in the prior art. This individual pin designation can also be used for group address designation from the CPU to each pin.

[0016]

Embodiment FIG. 1 shows the configuration of an embodiment of the test apparatus according to the present invention. The control CPU 9 controls each PIN section 10 using the control bus 1, address bus 2, and data bus 3. The PIN unit 10 has PIN #0 to PI
There are a plurality of buses up to N#n, all of which are connected to the control bus 1, address bus 2, and data bus 3. Each P
The IN section 10 includes an ADRCNT (address control) section 4 that performs address control, a test timing signal generator TG section 5,
FORM (format) section 6 that forms test waveforms, LM (local memory) that stores test data, FM (fail memory) section 7 that stores test results, and test object DU
PE (pin electronics) that performs input/output with T11
Consisting of 8 parts.

The ADRCNT unit 4 receives the address bus 2 as input, analyzes its contents, and determines whether it is selected. If it is selected, create the address 41 inside the PIN section 10 and send it to the TG section 5, FORM section 6, LM/FM
7 and the PE section 8 so that the contents of the data bus 3 can be taken in.

FIG. 2 shows the bit configuration of address bus 2. A GS (GROUPSEL) section 201 that indicates grouping based on test specifications (test conditions) from the upper bits.
, GA (GROUPAD) indicating the group number of the test specification
R) section 202, AP (ALLPIN) section 203 indicating that all pins are selected simultaneously, and PA(ALLPIN) section indicating the pin number.
PINADR) section 204, and RA (REGADR) section 205 indicating the register number within each pin. In this example, the number of bits of each part is as shown in parentheses in the figure.
The section 201 is 1 bit, the GA section 202 is 4 bits, the AP section 203 is 1 bit, the PA section 204 is 12 bits, and the RA section 205 is 16 bits. In this way, GROUPS
Except for the EL section 201 and the ALLPIN section 203, there are multiple bits, multiple groups, multiple pins, and multiple registers can be selected.

An ADRCNT unit 4 analyzes the bit configuration of the address bus 2 and creates the internal address 41.
A block diagram of this is shown in FIG.

The internal address 41 consists of a signal PINENn414 indicating that it is selected, and a signal REGADR205 indicating the register number. PINEN
n414 is '1' when the group to which the own pin belongs is specified based on grouping according to the test specifications, and when the own pin is specified by pin number without grouping. . Whether the designation is based on grouping or not is indicated by a signal GROUPSEL201 indicating grouping based on test specifications; when it is '1', it is group selection, and when it is '0', it is pin selection. For both selections, the selection circuit 401 outputs the group selection signal 407 and the pin selection signal 4 in response to the signal GROUPSEL201.
The output signal of this selection circuit 401 becomes PINENn414. Further, the signal REGADR205 indicating the register number inputted to the ADRCNT section 4 is outputted into the pin as it is.

Group selection signal 407 includes GROUP ADR 202 indicating the group number specified by the address and signal GROUP # 40 indicating the group to which the own pin belongs.
6 and is compared in a comparison circuit 402, and outputs if they are equal. As the signal GRPUP#406, the one stored in the register 409 is used.

[0022] The pin selection signal 408 is a pin number indicating a pin number.
The comparison circuit 404 compares INADR204 and the pin number 'n'405 of the own pin, and the OR circuit 403 uses the match output and the signal ALLPIN203 indicating simultaneous designation of all pins.
It is created by ORing with. The pin number 'n' 405 of the own pin can be given by setting a DIP switch (not shown) or the like. The pin selection signal 408 becomes '1' when the all pin simultaneous selection signal ALLPIN203 is '1', or when the pin number PINADR204 and the pin number 'n'
This is a case where 405 matches.

A signal G indicating the group to which the own pin belongs
ROUP #406 is set in the register 409 in advance before group selection. The settings for this register are for control bus 1 and address bus 2 shown in Figure 1.
Then, using the data bus 3, the control CPU 9 performs the following operations.

The control bus 1 includes a WE signal 101 indicating that writing is possible, a write clock CLK 102,
The data bus 3 consists of an RE signal 103 indicating readability, and the data bus 3 consists of write data WD301 and read data RD302. At the time of signal setting, the pin number and register number for writing are output to the address bus 2, the WE signal 101 indicating write enable is set to '1', and the write clock CLK102 is output. When setting the same group number to all pins, the all pin simultaneous selection signal 203 is set to '1'. ALLPIN203 or PINADR204 in the address bus as described above.
As a result, a pin selection signal 408 is generated, and it becomes clear that the own pin is selected. This pin selection signal 408 and
REGADR 205 indicating the register number is ANDed by an AND circuit 412, and the output thereof is decoded by a decoding circuit 411 to create a register selection signal 415 indicating that the register 409 with pin number 'n' is selected. This register selection signal 415, WE101, CLK1
02 are ANDed by an AND circuit 410 to create a write signal for the register 409, and the contents of the WD 301 are written as
Write to register 409.

The data written in this way is the group number to which the own pin belongs, and is stored in this register 409.
The output of GROU is a signal indicating the group to which the own pin belongs.
It becomes P#406. In order for the control CPU 9 to confirm the contents of this register 409, the address is output to the address bus 2, and the RE signal 10 indicating readability is output.
Just set 3 to '1'. As in the case of writing, a register selection signal 415 indicating that the register 409 is selected is generated from this address. By ANDing the register selection signal 415, the RE signal 103 indicating that reading is possible, and the output of the register 409 in an AND circuit 413, read data RD302 is created.

The control CPU 9 reads this read data RD.
By looking at 302, the contents of register 409 can be confirmed.

Next, the TG section 5, the FORM section 6, the LM/F
FIG. 4 shows how buses are connected to each register in the M section 7 and the PE section 8. The figure shows the configuration common to each part 5 to 8, and register 5 for setting data according to test specifications.
Only one 05 is shown for convenience. This configuration and operation are similar to those related to the registers inside ADRCNT4 (elements 409 to 413), but the pin selection signal 40
8, PIN which is the output signal of ADRCNT4
The difference is that ENn414 is input.

That is, in each register, PINENn
Signal 414 and REGADR 205 indicating the register number
are ANDed in an AND circuit 501, and the output is decoded in a decoding circuit 502 to generate a register selection signal 503.
make. Writing to the register 505 is performed using this register selection signal 503 and a signal WE101 indicating that writing is possible.
And write clock CLK102, AND circuit 5
A write clock to the register 505 is created by ANDing with 04. The write data WD301 is written to the register 505 using this write clock.

When reading a register, the register selection signal 503, the signal RE103 indicating readability, and the output of the register 505 are ANDed by an AND circuit 506, and read data RD302 is output.

FIG. 5 shows another embodiment of the ADRCNT section. In this example, the bit configuration of the address bus 2 is changed, and the address bus 2 is divided into a signal GROUPADR202 indicating a group number and a signal PI indicating a pin number.
NADR204 and REGADR2 indicating the register number
05. Instead of omitting the signal GROUPSEL201 indicating group selection, the signal GROUPADR202 indicating the group number is all '1'.
', the GROUPSEL signal indicates the same meaning as '1'. In addition, all pin simultaneous selection signal ALLP
Instead of omitting IN203, a signal P indicating the pin number is used.
When all INADRs 204 are '1', the ALLPIN signal has the same meaning as '1'.

Of the configuration shown in FIG. 5, the comparison circuit 417,
Everything other than 419 is the same as in FIG. In the comparison circuit 417,
a signal GROUPADR202 indicating the group number;
ll'1' signal 416, and if there is a mismatch, '1'
Output. This output causes the group selection signal 407
, selects the pin selection signal 408 and generates the PINENn signal 414. When the output of the comparison circuit 417 is '1', the group selection signal 407 is selected, and when it is '0', the pin selection signal 408 is selected. The group selection signal 407 is a signal GRO indicating a group number, as in the previous embodiment.
A comparison circuit 402 compares UPADR 202 with a signal GROUP #406 indicating the group to which the pin belongs.

The comparison circuit 419 compares the signal PINADR 204 indicating the pin number with the all'1' signal 418 to generate an all-pin simultaneous selection signal. On the other hand, PINADR
204 and a signal 'n' 405 indicating the pin number of the own pin are compared in a comparator circuit 404, and the output and the all pin simultaneous selection signal are ORed in an OR circuit 403 to obtain a pin selection signal 4.
Create 08.

Signal GRO indicating the group to which the own pin belongs
Writing and reading to and from the register 409 that outputs UP#406 is the same as in the previous embodiment.

FIG. 6 shows an example of grouping of test specifications. The TG section is divided into groups #1 to #4 at each timing 1 to 4. Regarding the FORM section, please refer to NRZ (
Non-Return to Zero) waveform and RZ (
Group # with the Return to Zero) waveform
Divide into #1 and #2. The PE section is divided into groups #1 and #2 based on driver comparator level 1 (ECL) and level 2 (TTL). In this way, by once grouping, when the test conditions are changed frequently for each group, data settings for all 7 pins of the TG section can be set four times for each change. can be done. Similarly,
It is sufficient to set data twice for the FORM section and twice for the PE section. In FIG. 6, seven pins are shown as an example for convenience, but the effect becomes even more remarkable when the number of pins is tens or hundreds.

[0035]

Effects of the Invention: By grouping according to the test conditions of the present invention, the time required to set the conditions for each pin of the test device is significantly shortened compared to the conventional setting of each pin individually, and it is possible to test the test object. Time is reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an apparatus according to an embodiment of the present invention.

FIG. 2 is an address bit configuration diagram of the embodiment.

FIG. 3 is a block diagram of an address control unit.

FIG. 4 is a bus connection configuration diagram of registers controlled by an address control unit.

FIG. 5 is a block diagram of another embodiment of the address control section.

FIG. 6 is an explanatory diagram of grouping of pins for each test condition.

[Explanation of symbols]

4...ADRCNT (address control unit), 201...GRO
UPSEL (bit indicating group selection),
202...GROUPADR (bit indicating group number), 203...ALLPIN (bit indicating simultaneous designation of all pins), 204...PINADR (bit indicating pin number)
, 205...REGADR (bit indicating register number)
.

Claims (9)

[Claims] 1. A test device having a plurality of pins connected to a device under test, each pin having a control register for setting test conditions for each pin, the CPU controlling the test device. and group address setting means for each pin, which sets a common group address for each pin under the same test conditions, and whether the group to which the own pin belongs is specified based on the address output from the CPU. a group address determination means for each pin, which determines whether or not the pin belongs; and when the group address determination means determines that the group to which the own pin belongs is designated, writes data representing the test conditions from the CPU to the control register. , and register writing means for each pin. 2. The test device according to claim 1, wherein the address from the CPU includes a group address indicating that the test conditions are the same and a register address specifying a control register inside the pin. . 3. The address from the CPU further includes a pin address for specifying a pin number, and a pin address determination means is provided for each pin for determining whether or not the pin address specifies the own pin. The test device according to claim 2, characterized in that: 4. A dedicated bit indicating execution of grouping is provided in the group address, and pin designation by the group address and pin designation by the pin address are switched according to the value of the dedicated bit. The test device according to item 3. 5. When the group address is a predetermined specific pattern, pin designation using the pin address is selected, and when the group address is not a specific pattern, pin designation using the group address is selected. test equipment. 6. The test device according to claim 3, wherein a dedicated bit is provided in the pin address to indicate that all pins are designated simultaneously. 7. The test device according to claim 3, wherein when the pin address has a predetermined specific pattern, the pin address specifies all pins simultaneously. 8. A test device having a plurality of pins connected to a device under test, each pin having a control register for setting test conditions for each pin, the CPU controlling the test device. and a pin address determination means for each pin that determines whether or not the pin address included in the address of the CPU designates the own pin, and when the pin address determination means determines that the own pin is designated. , register writing means for each pin for writing data representing test conditions from the CPU into the control register, a dedicated bit indicating that all pins are to be designated simultaneously in the pin address, and the dedicated bit A test device characterized in that all of the pin address determining means determine that its own pin has been designated in accordance with the value of . 9. A test device having a plurality of pins connected to a device under test, each pin having a control register for setting test conditions for each pin, the CPU controlling the test device. and a pin address determination means for each pin that determines whether or not the pin address included in the address of the CPU designates the own pin, and when the pin address determination means determines that the own pin is designated. , and register writing means for each pin for writing data representing test conditions from the CPU into the control register, and all the pin address determination means automatically write data when the pin address is a predetermined specific pattern. A test device characterized by determining that a pin is designated.