JP2002099446A - Register test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a register test circuit to test a register in an integrated circuit automatically and at high speed with a few input/output from/to outside. SOLUTION: The test circuit comprises an address generator 2 to specify a register address of a target of writing or reading of data among more than one register into the integrated circuit, a data generator 1 to generate data should be written into the register having the specified address, a read/write timing generator 3 to generate read/write timing into/from the register and switching circuits 4, 5 and 6 to switch an access signal to the register responding at a time of a test or an actual operation, so that the test is attained by performing read/write to all registers in the integrated circuit automatically along with updating the address and the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a register test circuit, and more particularly to a register test circuit provided in an integrated circuit for testing a register in the integrated circuit.

[0002]

2. Description of the Related Art Conventionally, there has been reported a register test circuit for testing a register in an integrated circuit by inputting data from outside the integrated circuit. For example,
The register test circuit device disclosed in Japanese Patent Application Laid-Open No. 2-031239 is provided in an integrated circuit including a test register for storing data, and the test register in the integrated circuit is directly provided with data from outside the integrated circuit. Can be input, and the register can be easily and rapidly tested in the integrated circuit by using this.

However, an arbitrary register is directly accessed from outside the integrated circuit, and each bit of the accessed register is set to “H” or “L”, and the result of writing and the result of reading are compared. In the conventional method of inspecting for abnormalities, it is necessary to specify an address to be written and data to be written each time, so that a simple but long test pattern is required. For this reason, when there is an abnormality, when debugging is performed by looking at the test pattern, there is a risk that a simple but confusing other similar information may give an incorrect result.

[0004] Further, with the recent increase in circuit size and functions, the number of registers for storing data provided in an integrated circuit has rapidly increased. When testing many of these registers, it is necessary to at least write and read both levels of "H" and "L" signals at high speed to each register. In an actual test, an improvement in processing speed is required, and the effect of test pattern selection becomes noticeable, and there is a problem that conventional register test circuits are not always sufficient.

[0005]

As described above, in the conventional register test circuit, it is necessary to input data each time from the outside, so that there is a problem that it is troublesome and an error easily occurs. Furthermore, there is a problem that the processing speed cannot be said to be sufficient for testing a recent integrated circuit having many registers. The present invention solves this problem in a relatively simple manner, and addresses,
By preparing a generation circuit for generating data and read / write timing, data, addresses and read / write timing are generated, and by switching those signal lines, data input / output to the outside is reduced.
An object of the present invention is to realize a register test circuit for automatically and quickly testing a register in an integrated circuit.

[0006]

In order to achieve the above object, the present invention provides a register test circuit for testing the operation of each register in an integrated circuit having a plurality of registers. Address generating means for designating the address of a register from which data is to be written or from which data is to be read; data generating means for generating data to be written to the register at the address designated by the address generating means; Read / write timing generating means for generating timing for writing and reading the generated data to the register at the address specified by the address generating means;
Switching means for switching a signal for accessing a register between a test and an actual operation, and automatically updating all addresses in the integrated circuit while updating addresses and data using the address generating means and the data generating means. A test is performed by reading / writing to / from a register. This makes it possible to realize a register test circuit that can automatically write and read data to and from each register in the integrated circuit and perform a register test easily and at high speed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a register test circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a basic configuration of an embodiment of a register test circuit according to the present invention. In FIG. 1, reference numeral 1 denotes a data generator for generating data to be written to a register. Reference numeral 2 denotes an address generator for generating an address for deciding which register to write to. Reference numeral 3 denotes a timing generator for generating timing for writing and reading data to and from a register. Reference numerals 4, 5, and 6 denote switching circuits for switching between a data signal, an address signal, and a read / write signal in an actual operation, and a data signal, an address signal, and a read / write signal output from a test circuit. Reference numeral 7 is a data signal during actual operation,
Reference numeral 8 denotes an address signal during actual operation, and reference numeral 9 denotes a read / write signal during actual operation. Reference numeral 10 denotes a register mounted on the integrated circuit and used for different functions.

The operation of this embodiment will be described with reference to FIG. For simplicity, the data width is set to 8 as an example.
Description will be made as bits. FIG. 6 and FIG. 7 show the waveforms of each part. 6 (a) and 7 (a) are clocks, FIG.
7 (b) and 7 (b) are write data, FIGS. 6 (c) and 7 (c) are register addresses, and FIGS. 6 (d) and 7
(D) is a read / write signal, FIGS. 6 (e) and 7 (e)
Is output data of the register. When the address (c) of the target register is set to the address bus, the write data (b) is set to the data bus, and the read / write signal (d) is set high, the data (b) is written to the target register by the clock (a). It is. When the address (c) of the target register is set on the address bus and the read / write signal (d) is set to low, data (e) is read from the target register to the data bus by the clock (a).

Here, for example, as shown in FIG. 6, 01h is written to 8 bits of a register at the same address.
Next, the written data 01h is read from this register. Further, 02h is written to the register at the same address. Next, the written data 02h is read from the register. As described above, "H" is sequentially set for each data bit of the register, and the "H" set at the next timing is read. Thus, all bits of the target register can be tested. Alternatively, as shown in FIG. 7, 00h is written to all data bits of the same address, the data is read out at the next timing, and fh is written at the next timing.
fh may be written and the written data ffh may be read. A test of the register is performed by reading the data written in the register from the register. The test method is not limited to the methods shown in FIGS.

As described above, circuits for generating addresses, data, and read / write timings are prepared in the integrated circuit, and signal lines from these circuits are switched to signal lines for normal operation during a test. An address, data, and read / write timing are automatically generated to test a register in the integrated circuit. As a result, necessary information can be automatically written to the register without inputting a signal from outside the integrated circuit, and the register in the integrated circuit can be tested by reading the information, thereby facilitating the test. Can be done.

FIG. 2 is a block diagram showing a basic configuration of another embodiment of the register test circuit of the present invention. FIG.
, Reference numerals 1 to 10 indicate the same components as those in FIG.
Numeral 11 denotes data comparing means for comparing read data and written data, and the data (b) written to the register and the read data (e) in FIGS.
Compare with As a result of the comparison, the register is tested based on a signal for determining whether the register matches or is incorrect. In this case, since the generation circuit itself automatically generates addresses and data, it is known which data is written to which address. Therefore, since information on what is actually written and what is being read is closed inside the integrated circuit, it is not necessary to read more information than necessary outside the integrated circuit, and the register test can be performed at high speed. It can be performed.

FIG. 3 is a block diagram showing a basic configuration of another embodiment of the register test circuit of the present invention. FIG.
, Reference numerals 1 to 10 indicate the same components as those in FIG.
Reference numeral 12 in FIG. 3 is a data register for arbitrarily determining data. For example, 00h, ff in FIG.
h, as in the test for writing
First, a test pattern consisting only of an operation of writing 0h and writing only 00h to the register to be tested and reading is prepared. Next, a test pattern for only the operation of writing ffh to the data register 12 and writing only ffh to the register to be tested and reading is prepared. Thus, the length of one test pattern can be simply controlled by arbitrarily setting the data to be written to the register. In addition, it is possible to increase the degree of freedom in pattern creation, for example, by devising test patterns for each application, for example, creating test patterns in which all "H" s are written.

FIG. 4 is a block diagram showing a basic configuration of another embodiment of the register test circuit of the present invention. FIG.
, Reference numerals 1 to 10 indicate the same components as those in FIG.
Reference numeral 13 denotes data bit length detecting means for detecting the empty state of the register bits, that is, the data bit length. Reference numeral 14 denotes an information signal line for inputting the information of the register to the data bit length detecting means 13. Reference numeral 15 sends a detection signal from the data bit length detecting means 13 to the data generator 1, and how much data and how. This is an information feedback line for feeding back information as to whether or not to generate important data. Each register generally has its own data length. Therefore, most addresses do not require all data widths,
Also, the data valid bit length of the register of the address varies depending on the integrated circuit. Therefore, it is sufficient to write a data width corresponding to the data effective bit length. That is, the data bit length detecting means 13 detects the vacancy of a bit. For example, in the case of a register in which only 4 bits out of 8 bits are used, when data is generated by the data generator 1, When 0 is written, that is, when 0fh is written, "H" is set in all the bits, thereby facilitating the test of the register.

FIG. 5 is a block diagram showing a basic configuration of another embodiment of the register test circuit of the present invention. FIG.
, Reference numerals 1 to 10 indicate the same components as those in FIG.
Reference numeral 11 is the same as the data comparison unit shown in FIG. 2, reference numeral 13 is a data bit length detection unit, reference numeral 14 is an information signal line, reference numeral 15 is an information feedback line,
These are the same as those shown in FIG. Every integrated circuit has multiple registers to control its function. In order to test this register, usually, a register test circuit corresponding to the function of the integrated circuit is provided. However, as shown in FIG. 5, by providing the register test circuit with the data bit length detecting means 13 and the data comparing means 11, the same register test circuit can be integrated with different types of integrated circuits regardless of the function of the integrated circuit. This allows the circuit to be used in common for the circuits, and the number of steps for designing the register test circuit can be reduced.

[0016]

As described above, according to the first aspect of the present invention, there is provided a register test circuit for testing the operation of each register in an integrated circuit having a plurality of registers. Address generation means for designating the address of a register to which data is to be written or data to be read from among the registers, data generation means for generating data to be written to the register at the address designated by the address generation means, and data generation means Read / write timing generating means for generating a timing for writing and reading timing of the data generated at the address specified by the address generating means and a switching means for switching a signal for accessing the register between a test and an actual operation. And using address generation means and data generation means And performing test and read / write all registers in the automatic integrated circuit while updating address and data. As described above, the generation circuit for generating the address, data, and read / write timing is prepared in the integrated circuit, and the address, data, and read / write timing are automatically generated by switching those signal lines, and Tests the registers automatically. By automatically writing necessary information to the register and reading the information without inputting a signal from the outside of the integrated circuit, the register in the integrated circuit can be automatically tested. It can be carried out.

According to a second aspect of the present invention, the data generated by the data generating means provided inside the integrated circuit and written in the register at the address designated by the address generating means is compared with the data read from the register. And comparing the written data and the read data inside the integrated circuit. As a result, the generation circuit itself automatically generates the address and data, and since the address and data information are closed inside the integrated circuit, there is no need to output data to the outside of the integrated circuit. A register test can be performed at high speed without reading out to the outside of the integrated circuit.

According to a third aspect of the present invention, there is provided a data value storing means provided in an integrated circuit for storing an arbitrary data value, and the data generating means comprises a data value storing means for storing the data value stored in the data value storing means. Is read and data is generated accordingly. Thus, the data to be written to the register can be set arbitrarily, and the length of one test pattern can be controlled. Also,
The degree of freedom regarding pattern creation can be increased, such as creating test patterns for each application.

According to a fourth aspect of the present invention, there is provided a data bit length detecting means for detecting an effective bit length of data which can be stored in a register provided in an integrated circuit, and a data validity length detected by the bit detecting means. Feedback means for feeding back the bit length information to the data generation means, wherein the data generation means generates data in accordance with the effective bit length information detected by the bit detection means. This allows
Data according to the data length of the register can be generated by the data generation means, and it is possible to cope with the case where the effective data bit length differs for each register or the case where the effective data bit length differs due to the difference of the integrated circuit. A register tester circuit can be realized.

According to a fifth aspect of the present invention, the data which is provided in an integrated circuit and which is generated by a data generating means and written into a register at an address designated by an address generating means is compared with data read from the register. Data comparing means, a bit detecting means for detecting an effective bit length of data that can be stored in the register, and a feedback means for feeding back the data effective bit length information detected by the bit detecting means to the data generating means, It is characterized in that it can be commonly used for different types of integrated circuits. This allows
Regardless of the function of the integrated circuit, a register test circuit that can be commonly used for different types of integrated circuits can be realized, and the number of steps for designing the register test circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of a register test circuit of the present invention.

FIG. 2 is a block diagram showing a basic configuration of another embodiment of the register test circuit of the present invention.

FIG. 3 is a block diagram showing a basic configuration of still another embodiment of the register test circuit of the present invention.

FIG. 4 is a block diagram showing a basic configuration of still another embodiment of the register test circuit of the present invention.

FIG. 5 is a block diagram showing a basic configuration of still another embodiment of the register test circuit of the present invention.

FIG. 6 is a waveform chart showing waveforms at various parts of the register test circuit of the present invention.

FIG. 7 is a waveform chart showing waveforms at various parts of the register test circuit of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data generator 2 Address generator 3 Timing generator 4, 5, 6 Switching circuit 7 Data signal at the time of actual operation 8 Address signal at the time of actual operation 9 Read / write signal at the time of actual operation 10 Register 11 Data comparison means 12 Data Register 13 Data bit length detecting means 14 Information signal line 15 Information feedback line

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Claims (5)

[Claims] 1. A register test circuit for testing an operation of each register in an integrated circuit having a plurality of registers, wherein: a data write destination or a data read destination from the plurality of registers provided in the integrated circuit. Address generating means for designating an address of a register of the following; data generating means for generating data to be written to a register at an address specified by the address generating means; and an address designated by the address generating means for data generated by the data generating means. Read / write timing generating means for generating a write timing and a read timing for the register, and switching means for switching a signal for accessing the register between a test time and an actual operation time, wherein the address generating means and the data generating means Update address and data using A register test circuit which automatically reads / writes all registers in the integrated circuit and performs a test. 2. A data comparing means for comparing data generated in the data generating means provided in the integrated circuit and written in a register at an address designated by the address generating means with data read from the register. 2. The register test circuit according to claim 1, further comprising: comparing the written data with the read data inside an integrated circuit. 3. A data value storing means provided in the integrated circuit for storing an arbitrary data value, wherein the data generating means reads data stored in the data value storing means and responds accordingly. The register test circuit according to claim 1, wherein the register test circuit generates data. 4. A data bit length detecting means for detecting an effective bit length of data which can be stored in a register provided inside the integrated circuit, and data effective bit length information detected by the bit detecting means is generated by the data generation means. 2. The register test circuit according to claim 1, further comprising feedback means for feeding back to said means, wherein said data generation means generates data in accordance with the effective bit length information detected by said bit detection means. 5. A data comparing means provided inside the integrated circuit, for comparing data generated in the data generating means and written in a register at an address designated by the address generating means with data read from the register. ,
A bit detection means for detecting an effective bit length of data that can be stored in the register; and feedback means for feeding back the data effective bit length information detected by the bit detection means to the data generation means. The register test circuit according to claim 1, wherein the register test circuit can be commonly used for the circuits.