JPH0821869A - Ic tester - Google Patents

Abstract

PURPOSE:To store pattern data in parallel at a high speed from memory sections into a pattern memory with controllers provided for individual memory sections. CONSTITUTION:A test system controller TSC 1 opens buffers 81-8i and closes buffers 91-9i. Selectors 61-6i select hard disks HDD 41-4i, and direct memory access controllers DMA 51-5i read the pattern data of the HDD 41-4i. The DMA 51 outputs a trigger signal to the HDD 41, and the HDD 41 outputs the pattern data and a strobe signal. The strobe signal is inputted to an address generation section 71, and an address and a strobe signal are outputted. The pattern data are written at the position corresponding to the address of a pattern memory 31. The next pattern data outputted from the HDD 41 by the trigger signal from the DMA 51 are likewise stored in a pattern memory 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an object to be tested, such as I
The present invention relates to an IC tester for testing C, LSI, etc., and an IC tester capable of downloading pattern data from a storage unit such as a hard disk, a floppy disk, or a memory to a pattern memory at high speed.

[0002]

2. Description of the Related Art An IC tester inputs an input pattern to an object to be tested, compares an output pattern from the object to be tested with an expected pattern, and judges pass / fail of the object to be tested. The input pattern and the expected value pattern are stored in the pattern memory, read from the pattern memory, and used for the test of the test object. Such a conventional IC tester is shown in FIG. In the figure, 11 is a test system controller (hereinafter abbreviated as TSC), which controls the entire apparatus. A pattern memory 12 stores pattern data that is an input pattern and an expected pattern.
A hard disk (hereinafter abbreviated as HDD) 13 is a storage unit that stores pattern data stored in the pattern memory 12.

The operation of such a device will be described below.
The TSC 11 reads the pattern data stored in the HDD 13 before the test of the object to be tested, and the pattern memory 1
2 is stored. Then, the TSC 11 uses the pattern data stored in the pattern memory 12 to perform the test of the test target. A conventional example of such an IC tester is described in Japanese Utility Model Laid-Open No. 2-675.

[0004]

In such a structure, there are the following problems. TSC11 is HDD
When reading from 13 and storing the pattern data in the pattern memory 12, since the data amount of the pattern data is hundreds of MBytes, it takes several hours to store the data. Therefore, when performing tests on different types of test objects, or even for test objects having the same function, if the IC type is different, the pin positions will differ, and the pattern data will be stored in the pattern memory 1.
2 had to be stored again, and it took a lot of time to carry out the next test.

An object of the present invention is to realize an IC tester capable of downloading pattern data from a storage unit to a pattern memory at high speed.

[0006]

According to the present invention, in an IC tester for testing a test object, a pattern memory provided for each pin of the test object and pattern data used for the test of the test object are stored. It is characterized in that it has the above-mentioned storage unit and a controller which is provided for each storage unit and which reads pattern data from the storage unit and stores it in the pattern memory.

[0007]

In the present invention as described above, the pattern data is stored in the pattern memory in parallel by the controller provided for each storage unit.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure,
A TSC 1 controls the entire apparatus. Reference numerals 21 to 2n are pin electronics boards (hereinafter abbreviated as PE), which are provided for each pin of the test object (not shown), and in which elements for applying signals and receiving the output of the test object are incorporated. There is. Pattern memories 31 to 3n are provided for the PEs 21 to 2n, respectively. HDDs 41 to 4i are storage units, and the TSC 1 stores the pattern data to be used in the test of the test object in advance for the data amount of two pattern memories. Here, the HDD has a portion that receives the trigger signal, outputs the pattern data, and outputs the strobe signal, in addition to the portion that stores the pattern data. Direct memory access controllers (hereinafter referred to as DMA) 51 to 5i are controllers.
Is provided for each of the HDDs 41 to 4i, and the pattern data is read from the HDDs 41 to 4i and stored in the pattern memories 31 to 3n, respectively. 61-
A selector 6i is a selector, which is connected to all the HDDs 41 to 4i and selects a desired HDD. Address generators 71 to 7i are provided for the selectors 61 to 6i, respectively, and the HDDs 41 to 41 selected by the selectors 61 to 6i.
An address is output by a signal from 4n, here a strobe signal. Reference numerals 81 to 8i denote buffers, and signals from the selectors 61 to 6i and the address generators 71 to 7i, respectively.
Signal is input and the signal is output to each of PEs 21 to 2n. The buffers 91 to 9i are TSC1 and PE2.
The signal from TSC1 is input and output to PE21 to 2n, respectively. The opening and closing of the buffers 81 to 8i and 91 to 9i are controlled by the TSC1.

The operation of such a device will be described below.
TSC1 opens buffers 81-8i and
Close 1-9i. And HD to the selectors 61 to 6i
Select D41 to 4i and make DMA 51 to 5i HD
The pattern data of D41 to 4i is read.

Next, in the following, the HDD is selected by the selector 61.
A case where 41 is selected and pattern data is stored in the pattern memories 31 and 32 will be described. FIG. 2 is a timing chart showing the operation of the device of FIG.
(A) is a trigger signal from the DMA 51 to the HDD 41,
(B) is pattern data output from the HDD 41, (c)
Is a strobe signal output from the HDD 41, (d) is an address output from the address generator 71, and (e) is a strobe signal output from the address generator 71.

The DMA 51 outputs a trigger signal to the HDD 41, and the HDD 41 outputs the pattern A data A and the strobe signal (). This strobe signal is input to the address generation unit 71, and the address "N
(N: integer) "and a strobe signal are output ().
Then, the data A is written in the location corresponding to the address “N” of the pattern memory 31 via the selector 61 and the buffer 81. Again, the DMA 51 outputs the trigger signal, and the HDD 41 outputs the data B which is the next pattern data and the strobe signal (). With this strobe signal, the address generator 71 receives the address "N + 1".
And a strobe signal are output (). Then, the data B is written to the location corresponding to the address “N + 1” of the pattern memory 31 via the selector 61 and the buffer 81. The above operation is repeated to store the pattern data in the pattern memory 31, and then store the pattern data in the pattern memory 32.

During the above operation, for example, H
In order to store the pattern data from the DD 42 to the pattern memories 33 and 34, the same operation as the above operation is performed,
Pattern data is stored in the pattern memories 33 and 34. That is, the pattern data is stored in the pattern memories 31 and 32, and at the same time, the pattern data 33 and 34 are stored. Further, the operations of storing the other HDDs 43 to 4i in the pattern memories 35 to 3n are performed in the same manner as described above, and at the same time when the pattern data is stored in the pattern memories 31 and 32, the pattern memories 35 to 3n are stored.
The operation of storing the pattern data in n is also completed.

When conducting the test of the test object,
The TSC 1 closes the buffers 81 to 8i and
Open 1-9i. And TSC1 is PE21-2
Indication of the voltage of the driver mounted on the n, turning on the relay,
The entire device is controlled by sending data, an address, and a control signal (R / W signal, strobe signal) for instructing to turn off.

In this way, i for storing the pattern data
Since each HDD is provided and the pattern data is stored in parallel in the pattern memory by DMA for each HDD, the pattern data can be stored at high speed. Further, since the HDDs 41 to 4i are selected by the selectors 61 to 6i, the pattern data of the HDDs 41 to 4i can be stored in any of the pattern memories 31 to 3n.

The present invention is not limited to this, and PEs include those corresponding to several pins to be tested. That is, a PE having two or more pattern memories mounted therein or a PE provided at another location is also included. Further, although the switching between the TSC 1 and the HDD 42 is performed by the buffers 81 to 8i and the buffers 91 to 9i, it may be configured by a bus changeover switch or the like. The address generators 71 to 7i are not provided after the selectors 61 to 6i but are provided in front of the selectors 61 to 6i or the HDDs 41 to 4i are configured to store the addresses corresponding to the pattern data. 71
7i may not be provided. Further, in the embodiment, the relationship of the data amount between the HDD and the pattern memory is shown as 2: 1, but any ratio may be used.

[0016]

The present invention has the following effects. According to the first aspect, since two or more storage units for storing the pattern data are provided and the controller for each storage unit stores the pattern data in parallel in the pattern memory, the pattern data can be stored at high speed. it can. According to the second aspect, since the storage unit is selected by the selection unit, the pattern data of the storage unit can be stored in any pattern memory.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the device of FIG.

FIG. 3 is a diagram showing a configuration of a conventional IC tester.

[Explanation of symbols]

 31-3n pattern memory 41-4i HDD 51-5i DMA 61-6i selector

Claims (2)

[Claims] 1. An IC tester for testing a device under test, a pattern memory provided for each pin of the device under test, two or more storage units for storing pattern data used for the test for the device under test, and this memory. An IC tester comprising: a controller that is provided for each unit and that reads pattern data from a storage unit and stores the pattern data in the pattern memory. 2. The IC tester according to claim 1, wherein a selection unit is provided between the storage unit and the pattern memory, and the pattern data of the hard disk can be stored in any pattern memory.