JP3341506B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a built-in test circuit.

[0002]

2. Description of the Related Art FIG . 7 is a circuit diagram showing a main part of an example of a conventional semiconductor integrated circuit . In FIG. 7 , reference numeral 1 denotes an address generation unit for generating 32-bit addresses A31 to A0;
A data output unit that outputs bit data D31 to D0,
Reference numeral 3 denotes a data input unit for inputting 32-bit data D31 to D0.

Reference numeral 4 denotes an address output terminal group consisting of 32 address output terminals provided corresponding to addresses A31 to A0, and 5 denotes 32 data output terminals provided corresponding to data D31 to D0. This is a data input / output terminal group including input / output terminals.

Here, a test of a semiconductor integrated circuit such as a microprocessor or a microcontroller is performed by using a test device for the semiconductor integrated circuit, a so-called LSI tester . FIG. It is a conceptual diagram showing a test method.

In FIG . 8 , reference numeral 7 denotes a semiconductor integrated circuit to be tested, for example, the conventional semiconductor integrated circuit shown in FIG. 7, and 8 denotes an LSI tester.

Further, in the LSI tester 8, reference numeral 9 denotes an input value to be given to the semiconductor integrated circuit 7 and the input value to be given to the semiconductor integrated circuit 7.
The test pattern signal generating circuit 10 for generating an expected value to be compared with the output value output from the semiconductor integrated circuit 7 compares the output value output from the semiconductor integrated circuit 7 with the expected value output from the test pattern signal generating circuit 9. This is a comparison circuit.

In the test of the semiconductor integrated circuit 7, a test pattern covering test items to be checked is provided to the LSI tester 8, and a test pattern signal generation circuit 9
Is input to the semiconductor integrated circuit 7 and the output value output from the semiconductor integrated circuit 7 is compared with the expected value output from the test pattern signal generation circuit 9 in the comparison circuit 10. Then, it is performed by verifying whether or not the operation is as expected.

[0008]

The conventional semiconductor device shown in FIG .
In the integrated circuit , even in the test mode, the address output terminal is used as the address output terminal and the data input / output terminal is used as the data input / output terminal, as in the case of the normal mode.

For this reason, the conventional semiconductor integrated circuit shown in FIG.
In the case of performing a circuit test, the LSI tester 8 shown in FIG. 8 corresponds to 32 address output terminals, 32 data input / output terminals and control signal terminals of the conventional semiconductor integrated circuit shown in FIG. An LSI tester provided with a terminal to be used is required.

However, an LSI tester with a large number of terminals is more expensive than an LSI tester with a small number of terminals.
There is a problem that the price of the semiconductor integrated circuit increases.

[0011] Figure 9 is a timing chart for explaining another problems of the conventional semiconductor integrated circuit shown in FIG. 7, if FIG. 9 (A) is switched to input cycle from the output cycle, FIG. 9 (B ) Shows a case where the input cycle is switched to the output cycle.

That is, in the conventional semiconductor integrated circuit shown in FIG. 7, since data is input / output via a data input / output terminal, as shown in FIG. When switching from the cycle to the input cycle, when the output signal is delayed, or as shown in FIG.
In the case of switching from the input cycle to the output cycle, if the input timing of the input signal is shifted, signals having different logical values may overlap on the data bus, so-called bus fight may occur.

Accordingly, the conventional semiconductor integrated circuit shown in FIG.
In the circuit , a special test pattern must be created to avoid the bus fight, and there is a problem that the test cannot be easily performed.

Here, when an idle cycle is inserted at the time of switching from the output cycle to the input cycle or at the time of switching from the input cycle to the output cycle, bus fight can be easily avoided. In this case, there is a problem that the test time becomes longer.

In view of the above, the present invention provides a semiconductor integrated circuit having a plurality of address output terminals and a plurality of data input / output terminals, and performs a test using a low-cost LSI tester. It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the cost of the semiconductor integrated circuit and facilitating the test by avoiding the bus fight without requiring a special test pattern.

[0016]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having a plurality of address output terminals and a plurality of data input / output terminals. Means as an address output terminal or a data output terminal, and a data input / output terminal other than the data input / output terminal used as the address output terminal or the data output terminal. A second means for collectively supplying data of all bits input to the data input / output terminal used as a data input terminal in a time-sharing manner to the data input unit; And third means for use as an output terminal.

[0017]

In the present invention , a first means for using a part of the plurality of data input / output terminals as an address output terminal or a data output terminal is provided.

Therefore, a part of the address output terminal,
By using a data input / output terminal that can be used as an address output terminal, all bits of the address can be output.

Further, data input / output terminals other than the data input / output terminals used as the address output terminal or the data output terminal are used as the data input terminals, and the data input / output terminals used as the data input terminals are time-divided. Second means is provided for collectively supplying input data of all bits to a data input unit.

Therefore, by inputting all bits of data to the data input / output terminals other than the data input / output terminals used as the address output terminal or the data output terminal in a time division manner, all the bits of the data are input to the data input section. Can be supplied.

A third means for using a part of the plurality of address output terminals as a data output terminal is provided.

Therefore, all bits of data can be output by using an address output terminal used as a data output terminal and a data input / output terminal used as a data output terminal.

As described above, according to the present invention , the output of all bits of the address signal and the input of all bits of the data can be performed without using an address output terminal other than the address output terminal used as the data output terminal. Since all bits of data can be output, a test using an inexpensive LSI tester with a small number of terminals can be performed, and test costs can be reduced.

According to the present invention , the used address output terminals are used exclusively for output, and the data input / output terminals are used by being divided into output-only terminals and input-only terminals. Basfighting can be avoided without creating a special test pattern.

[0025]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention . In FIG. 1, reference numeral 24 denotes a 32-bit address A31 to A31.
An address generation unit that generates A0, 25 is a data output unit that outputs 32-bit data D31 to D0, and 26 is 32
This is a data input unit for inputting bit data D31 to D0.

Reference numeral 27 denotes an upper 16-bit address A.
An address output terminal group consisting of 16 address output terminals provided corresponding to 31 to A16,
An address output terminal group including 16 address output terminals provided corresponding to the 6-bit addresses A15 to A0.

29 is the upper 16 bits of data D3
A data input / output terminal group consisting of 16 data input / output terminals provided corresponding to 1 to D16,
This is a data input / output terminal group including 16 data input / output terminals provided corresponding to the bit data D15 to D0.

Reference numeral 31 denotes a connection between the output terminals of the addresses A15 to A0 of the address generation unit 24 and the address output terminal group 28 or a connection between the output terminals of the data D15 to D0 of the data output unit 25 and the address output terminal group 28. Is selectively performed by the selector.

Reference numeral 32 denotes a connection between the output terminals of the addresses A31 to A16 of the address generation unit 24 and the data input / output terminal group 29 or an output terminal of the data D31 to D16 of the data output unit 25 and the data input / output terminal group 29. Is a selector for selectively performing the connection.

A latch circuit 33 latches data D15 to D0 input through the data input / output terminal group 30.

Reference numeral 34 denotes a connection between the output terminal of the latch circuit 33 and the input terminals of the data D31 to D16 of the data input unit 26 or the data input / output terminal group 29 and the input terminals of the data D31 to D16 of the data input unit 26. Is a selector for selectively performing the connection.

Reference numeral 35 denotes a test signal input terminal to which the test signal TEST is input, and reference numeral 36 denotes a test mode setting circuit for setting a test mode by the test signal TEST.

FIG . 2 shows a case where one embodiment of the present invention is set to a normal mode.
With respect to addresses A15 to A0 of the address generation unit 24.
Is selected between the output terminal and the address output terminal group 28.

The selector 32 selects the connection between the output terminals of the data D31 to D16 of the data output unit 25 and the data input / output terminal group 29.

Further, the data input / output terminal group 29 and the data D31 to D1 of the data input section 26 are supplied to the selector 34.
6 is selected to be connected to the input terminal.

In this case, the addresses A31 to A16 output from the address generation unit 24 are output from the address output terminal group 27, and the addresses A15 to A0 output from the address generation unit 24 are Output can be made from the output terminal group 28.

The data D31 to D16 output from the data output unit 25 are output from the data input / output terminal group 29, and the data D15 to D16 output from the data output unit 25 are output.
To D0 can be output from the data input / output terminal group 30.

The data D31 to D16 input to the data input / output terminal group 29 are input to the input terminals of the data D31 to D16 of the data input unit 26, and the data D15 to D16 input to the data input / output terminal group 30 are input. D0 can be input to the input terminals of the data D15 to D0 of the data input unit 26.

FIG . 3 is a timing chart for explaining the operation when the test mode is set according to one embodiment of the present invention.
3A is a test clock, FIG. 3B is a signal state of the address output terminal group 27, FIG. 3C is a signal state of the address output terminal group 28, and FIG. 3D is a data input / output terminal group. 2
FIG. 3E shows the signal state of the data input / output terminal group 30.

FIGS. 4 to 6 also show one embodiment of the present invention.
FIG. 4 is a circuit diagram for explaining an operation when a test mode is set in the embodiment .

The test mode is set by activating the test mode setting circuit 36 in response to the test signal TEST. In this case, first, as shown in FIG. 24 addresses A1
The connection between the output terminals 5 to A0 and the address output terminal group 28 is selected.

Further, the selector 32 is caused to select the connection between the output terminals of the addresses A31 to A16 of the address generation unit 24 and the data input / output terminal group 29.

Also, for the selector 34, the output terminal of the latch circuit 33 and the data D31 to D1 of the data input section 26 are provided.
6 is selected to be connected to the input terminal.

The selectors 31, 32 and 34 are set as described above, and the addresses A31 to A0 are output from the address generator 24.
Output.

In this case, as shown in FIG.
Addresses A31 to A output from address generation unit 24
16 are the addresses A15 to A15 which are output from the data input / output terminal group 29 and are also output from the address generator 24.
0 can be output from the address output terminal group 28.

In response to this, from the LSI tester,
First, among the data D31 to D0 to be input to the embodiment of the present invention , first, the data D31 to D16 are input to the data input / output terminal group 30.

In one embodiment of the present invention , the latch circuit 33 latches the data D31 to D16 input from the LSI tester to the data input / output terminal group 30.

Next, as shown in FIG. 5, the selector 31 is caused to select the connection between the output terminals of the addresses A15 to A0 of the address generator 24 and the address output terminal group 28.

The selector 32 selects the connection between the output terminals of the addresses A31 to A16 of the address generator 24 and the data input / output terminal group 29.

Also, the selector 34 is provided with the output terminal of the latch circuit 33 and the data D31 to D1 of the data input unit 26.
6 is selected to be connected to the input terminal.

The selectors 31, 32 and 34 are set as described above, and the addresses A31 to A0 are output from the address generator 24.
Output.

In this way, as shown in FIG.
Addresses A31 to A output from address generation unit 24
16 are the addresses A15 to A15 which are output from the data input / output terminal group 29 and are also output from the address generator 24.
0 can be output from the address output terminal group 28.

In response to this, from the LSI tester,
Among the data D31 to D0 to be input to one embodiment of the present invention, the data D15 to D0 are input to the data input / output terminal group 30, and are latched by the latch circuit 33 in one embodiment of the present invention . The data D31 to D16 are output.

As a result, the data D31 to D16 output from the latch circuit 33 are the data D31 of the data input unit 26.
The data D15 to D0 input to the input terminals 31 to D16 and input to the data input / output terminal group 30 can be input to the input terminals of the data D15 to D0 of the data input unit 26.

Next, as shown in FIG. 6, the selector 31 is caused to select the connection between the output terminals of the data D15 to D0 of the data output unit 25 and the address output terminal group 28.

The selector 32 selects the connection between the output terminals of the data D31 to D16 of the data output unit 25 and the data input / output terminal group 29.

Further, the selector 34 outputs the data D31 to D1 of the data input unit 26 to the output terminal of the latch circuit 33.
6 is selected to be connected to the input terminal.

The selectors 31, 32 and 34 are set as described above, and the data output unit 25 outputs data D31 to D0.

In this case, as shown in FIG.
Data D31 to D16 output from data output unit 25
Can be output from the data input / output terminal group 29, and the data D15 to D0 also output from the data output unit 25 can be output from the address output terminal group 28.

As described above, in one embodiment of the present invention , in the first data input cycle, addresses A31-A
0 is output and data D31 to D16 are input. In the next data input cycle, addresses A31 to A0 are output and data D15 to D0 are input. In the subsequent data output cycle, data D31 to D0 are output. , Test can be done.

When the data input from the LSI tester is 16 bits or 8 bits, only the first data input cycle is required for data input.

Here, in the embodiment of the present invention, since the selectors 31, 32, and 34 and the latch circuit 33 are provided, the 16 address output terminals of the address output terminal group 27 are set when the test mode is set. No need to use.

Therefore, according to one embodiment of the present invention ,
32 address output terminals, 32
It is not necessary to prepare an LSI tester having terminals corresponding to the data input / output terminals and the control signal terminals, and it is sufficient to prepare an LSI tester having 16 terminals less than this.

In one embodiment of the present invention, when the test mode is set, the address output terminal group 28 outputs the addresses A15 to A0 in the first data input cycle, and outputs the address A15 in the next data input cycle. ~ A0
Are output, and in a data output cycle, data D15 to D15 are output.
0 is output and no signal is input.

That is, since the address output terminal group 28 is exclusively used for output, no bus fight occurs on the address bus to which the address output terminal group 28 is connected.

In the data input / output terminal group 29, during the first data input cycle, addresses A31-A
In the next data input cycle, addresses A31 to A16 are output, and in the data output cycle, data D31 to D16 are output, and no signal is input.

That is, since the data input / output terminal group 29 is dedicated to output, bus fight does not occur in the data bus connected to the data input / output terminal group 29.

In data input / output terminal group 30, data D31 to D16 are input in the first data input cycle, and data D15 to D0 are input in the next data input cycle.
Is input and no signal is output.

That is, since the data input / output terminal group 30 is dedicated to input, bus fight does not occur in the data bus connected to the data input / output terminal group 30.

As a result, in one embodiment of the present invention ,
There is no need to create special test patterns to avoid bus fights.

Thus, according to one embodiment of the present invention ,
Since the test can be performed using an inexpensive LSI tester with a small number of terminals, the cost can be reduced by reducing the test cost, and the bus fight can be performed without the need for a special test pattern. So you can avoid
Testing can be facilitated.

[0072]

According to the present invention, it is possible to output all bits of an address signal without using an address output terminal other than an address output terminal used as a data output terminal.
Since all bits of data can be input and all bits of data can be output, an inexpensive LSI with a small number of terminals can be used.
A test using a tester can be performed, and the cost can be reduced by reducing the test cost.

According to the present invention , at the time of testing, the address output terminal used is exclusively used for output, and the data input / output terminal is divided into an output-only terminal and an input-only terminal. Since a bus fight can be avoided without requiring a special test pattern, the test can be facilitated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an operation of the embodiment of the present invention (operation when setting a normal mode).

FIG. 3 is a timing chart for explaining an operation (operation when a test mode is set) of one embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining an operation (operation when a test mode is set) of one embodiment of the present invention.

FIG. 5 is a circuit diagram for explaining an operation (operation when a test mode is set) of one embodiment of the present invention.

FIG. 6 is a circuit diagram for explaining an operation (operation when a test mode is set) of one embodiment of the present invention.

FIG. 7 is a circuit diagram showing a main part of an example of a conventional semiconductor integrated circuit .

FIG. 8 is a conceptual diagram showing a test method for a semiconductor integrated circuit.

9 is a timing chart for explaining another problem of the conventional semiconductor integrated circuit shown in FIG.

[Explanation of symbols]

 A31-A0 Address D31-D0 Data

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-57122 (JP, A) JP-A-4-69756 (JP, A) JP-A-2-104450 (JP, U) (58) Survey Field (Int.Cl. ⁷ , DB name) G06F 11/22 330 G06F 13/00 301 G11C 11/413

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit having a plurality of address output terminals and a plurality of data input / output terminals, wherein a part of the plurality of data input / output terminals is used as an address output terminal or a data output terminal. And a data input / output terminal used as a data input terminal using data input / output terminals other than the data input / output terminal used as the address output terminal or the data output terminal. A second means for collectively supplying data of all bits input in a time-division manner to a data input unit; and a third means for using a part of the plurality of address output terminals as a data output terminal. And a means for providing a semiconductor integrated circuit.