JP2000293394A - Processor with bist function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test high-speed operation and to test a combination of many instructions by making a random-number instruction generating means generate a test instruction at random according to a test signal which is inputted from outside. SOLUTION: The random-number instruction generating means is composed of an instruction storage means 71 and an instruction selecting means 72 and inputs a test mode signal 133 indicating that a self-test is conducted to an instruction selecting means 72. The instruction selecting means 72 sends information showing which test instruction stored in the instruction storage means 71 is selected as a select signal 73 to the instruction storage means 71 and also outputs the information as an instruction information signal 134. Then the instruction storage means 71 having received the select signal 73 outputs a random test instruction corresponding to the select signal to a line 140. Consequently, high-speed operation can be tested and a combination of many instructions can be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a built-in self-test (BIST) for a logic circuit incorporating a self-test function, which can achieve a high-speed test and a high fault detection rate.
About technology.

[0002]

2. Description of the Related Art As a test method for detecting a fault in a logic circuit, test data prepared in advance is externally input to a circuit to be tested, and the output response is observed to determine the presence or absence of a fault. A method of determining is generally adopted. However, as the scale of the logic circuit increases, the amount of test data increases, the test time increases, and the cost of the test increases. Therefore, a test circuit is incorporated in a logic circuit, and the logic circuit employs a BIST technique of performing a self-test using the test circuit, thereby reducing the cost for the test.

The conventional BIST technology is based on IEEE DESIGN & T
EST OF COMPUTER, March 1993, pages 73 to 8
"A Tutorial on Built-In Self-Test" described on page 2, page 69 to page 77 of the same magazine, June 1993.
Are discussed in As shown in FIG. 2, the BIST includes a test controller, a pattern generator, and a response analyzer. The signal output from the pattern generator is input to the test target circuit, the response signal is captured by the response analyzer, and the state of the response analyzer is observed to determine the presence or absence of a failure. Pattern generators can be broadly divided into two types. One is a method in which the created test data and the test program are stored in a memory such as a ROM, and are output to a test target circuit. In this method, test data must be stored in a memory, and the amount of test data that can be stored in a logic circuit is limited. For this reason, there is a problem that it is possible to detect a fault that has become the target of the test data, but it is not possible to detect other faults. Another method is to use a pseudo random number generator. By using a pseudo-random number generator, a large amount of pseudo-random numbers are output and input to a test target circuit. In the method using such a pseudo-random number, when the test target circuit is a sequential circuit, it is difficult to make a transition in all states, and even when the test target circuit is a combinational circuit, a part that is difficult to detect may occur. It is difficult to achieve high fault coverage. Also, a method of providing an additional circuit so that pseudo-random data can be directly set in an internal storage element so that a sequential circuit can be treated as a combinational circuit is often used together. Operation becomes difficult and an increase in circuit area becomes a problem. Japanese Patent Application Laid-Open No. 5-120052 discloses an example in which the two types of pattern generators are combined. In this method, a test is performed using an instruction execution function of a microprocessor. A test program is stored in a memory, and data used by the program is generated by a pseudo random number generator. When a test mode designation signal is input, the test mode is set to a self-test mode. When a test instruction stored in a program memory is executed, test data to be input to an arithmetic unit (ALU) to be tested is generated by a pseudo random number generator. And a circuit for normalizing the pseudo-random number according to the status of the status flag in the circuit to supply a large amount of valid test data to the test instruction. But,
Also in this method, since the test instructions are stored in the program memory, the number of combinations of the testable instructions is limited, and it is not sufficient for a logic circuit part whose operation differs depending on the order in which the instructions appear. In some cases, test cases cannot be executed.

[0004]

As shown in the conventional example, there is a problem that a sufficient test cannot be performed by a method of performing a self-test by storing test data in a memory or the like. In the method using only the pseudo-random number generator, the overhead of the additional circuit (reduction in operation speed and increase in area) becomes a problem. Even in the method of performing a test using the instruction execution function of the processor, which is a method of combining the above two methods, there is a problem that the number of combinations of instructions to be tested is limited. B
In order to realize a high-speed test and a high failure detection rate using the IST, it is necessary to solve these problems. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for performing a test using an instruction execution function of a processor, which is capable of testing a high-speed test and many instruction combinations.

[0005]

In order to achieve the above object, a processor according to the present invention is characterized in that it has a function of randomly generating test instructions, whereby a high-speed operation test and a combination of many instructions are performed. Test.

More specifically, a program counter for indicating an instruction to be executed by the processor, an instruction register for storing the instruction specified by the program counter, a register for storing data, and a program register for storing the instruction. An instruction for reading an instruction, reading data stored in a register based on the read instruction, executing an operation, and storing data as an operation result in the register, and a tester for executing a test based on a test signal input from the outside. Providing random number command generation means for randomly generating commands enables a test of a high-speed operation and a test of a combination of many commands.

Further, a program counter for designating an instruction to be executed by the processor, a register file having a plurality of registers for storing data, and data stored in the register file based on the instruction designated by the program counter. An arithmetic unit that reads, executes an operation, and stores data as an operation result in a register; random number instruction generation means that randomly generates a test instruction based on a test signal input from the outside; Providing random number data output means for outputting random number data to be executed and a response analyzer for storing an operation result based on the random number data enables a high-speed operation test and a test of a combination of many instructions.

An information processing system having a memory for storing a program or data for achieving the above object, and a processor connected to the memory for reading data stored in the memory or writing data to the memory. The processor reads the data stored in the data register based on an instruction, an address register storing an address for accessing the memory, a data register storing data stored in or read from the memory, and , An operation unit for executing an operation, and a response analyzer for storing an address stored in an address register based on a signal input from the outside, so that a high-speed operation test and a combination of many instructions can be performed. An information processing system that enables a test can be realized. In order to achieve the above object, an information processing system includes: a memory that stores a program or data; and a processor that is connected to the memory and that reads data stored in the memory or writes data to the memory. The processor comprises: an instruction register for outputting an instruction to be executed; a plurality of registers for storing data; an address register for storing an address for accessing the memory; and data for storing in the memory. Or a data register that stores data read from the memory, and a computing unit that performs an operation on data stored in a plurality of registers or data registers according to an instruction output from the instruction register, based on an external signal, An instruction generator that generates instructions randomly and stores them in an instruction register; A response analyzer that executes according to the instructions output from the instruction generator and captures the data stored in the data register, thereby enabling a high-speed operation test and a test of a combination of many instructions. The system can be realized.

Further, the random number instruction generating means of these processors stores a test instruction generated by the test instruction in an instruction register, or randomly generates a test instruction and outputs data conforming to the instruction from the register. Or a combination of any of these, such as the output of a signal, or the determination of a command based on a predetermined probability having a plurality of commands and outputting the command, or a combination of these. I do.

Further, the random number instruction generating means of these processors has an instruction storing means for storing instructions to be executed by the processor and an instruction selecting means for randomly selecting an instruction from the instruction storing means. Enables testing of combinations.

Further, the random number instruction generation means of these processors executes a partial instruction storage means for storing a part or the entirety of an instruction to be executed, and executes the partial instruction corresponding to the partial instruction stored by the partial instruction storage means. Instruction complement information storage means for storing information designating a missing part in order to be a possible instruction, and random selection of partial instructions from the partial instruction storage means and instruction complement information corresponding to the partial instructions from the instruction complement information means Instruction selecting means, and an instruction creating means for creating an instruction to be executed by the processor by supplementing random number data based on the selected partial instruction and the instruction complement information,
Enables testing of many instruction combinations.

Further, when the test mode signal indicates a self-test, the random number data output means outputs data instead of the register in the register file instructed to output data by the instruction, and writes the data by the instruction. The response analyzer captures data in place of the register in the designated register file to enable testing of many instruction combinations.

Further, when the test mode signal indicates a self-test, the response analyzer of these processors takes in the output signal of the program counter, the address at which the processor accesses the memory, and the output of the data register to operate at high speed. Can be tested.

[0014]

Embodiments of the present invention will be described below.

FIG. 1 shows the configuration of an LSI including a processor according to an embodiment of the present invention. 101 is a memory interface for exchanging signals with a memory via a bus 111, 102 is a program counter, 10
3 is an instruction cache, 104 is a sequencer that controls a program counter, 105 is an instruction register, 106 is a decoder that decodes the contents of the instruction register and controls an arithmetic unit, etc. 107 is 32 registers for storing data, and random number data output A register file having a random number data generator as a means and a MISR (Multiple Input Signature Register) as a response analyzer, and 108 is an ALU (Arithmetic L
ogical unit), 109 is a register for exchanging data with the memory, MDR (Memory Data Register), 1
10 is an MA for designating an address to the memory interface.
R (Memory Address Register), 123 is a random number command generating means for randomly outputting a command when performing a self-test, 125, 142 and 143 are random number data generators as random number data outputting means, 144, 126, 127 and 128 Is MISR used as a response analyzer, 129, 130 and 1
Reference numerals 31, 132, and 141 are selectors for switching the signal flow between the normal operation and the test operation. Reference numeral 133 denotes a test mode signal for instructing to perform a self-test applied from outside the LSI, and reference numeral 134 denotes an instruction information signal indicating the contents of the instruction 140 output from the random number instruction generation unit 123. Further, the random number data generator according to the present embodiment includes:
The instruction information signal 134 is input, and the random number instruction
Has a function of changing the method of generating random number data so as to output random number data that conforms to the command output by. Also,
136, 137, 138 and 139 are MISR
Output signals of 144, 126, 127, and 128 are output to the outside of the processor.

FIG. 3 is a list of instructions of the processor described in this embodiment. All basic instructions are register-to-register operations. There are four branch instructions: an unconditional branch instruction BRA, a conditional branch instruction BRAcc (cc indicates a branch condition), a branch instruction CALL to a subroutine, and a return instruction RTN from the subroutine. In addition, there are a load instruction LOAD and a store instruction STOR. The address space that can be specified in the branch instruction, the load instruction, and the store instruction is represented by 24 bits.

FIG. 4 shows an instruction format. All instructions have a fixed length of 32 bits. F, S in the basic instruction
The 1, 1, and 2 fields are a bit for indicating whether or not the operation result is reflected in the flag, a field for indicating the first source register, and a field for indicating the second source register, respectively. Also, d in the branch instruction indicates a branch destination address.

FIG. 5 shows a detailed instruction format showing the definition of the OP (opcode) portion in FIG. In the basic instruction, the 0th to 7th bits are all 0. In the branch instruction, the 4th to 7th bits are all 0s, and the 8th to 31st bits contain the branch destination address.
In the load / store instruction, the 16th bit is 1, and the value of the 0th bit distinguishes LOAD and STOR.

The processing flow of this embodiment during normal operation will be described. In the processing of the basic instruction at the time of the normal operation, first, the instruction indicated by the program counter 102 is read from the instruction cache 103 and set in the instruction register 105. The sequencer 104 receives the instruction signal 115, AL
Program counter 1 based on flag signal 116 from U108
02 is controlled. Next, from the register file 107, the data of the register indicated by the instruction is transferred to the ALU 108 via the buses 118 and 119. Next, the ALU 108 performs an operation. The finally calculated result is stored in the register in the register file 107 designated by the instruction via the bus 120.

In the processing of the branch instruction, first, the instruction indicated by the program counter 102 is read from the instruction cache and set in the instruction register. Next, in the case of BRA, the branch destination address is
04 and controls the program counter 102 through the bus 112. In the case of BRAcc, the branch destination address from the instruction signal 115 and the flag signal 116 from the ALU 108 are sent to the sequencer 104, and the program counter 10
2 is controlled. In the case of CALL, the program counter 1
02 is saved in the register 0 in the register file, and a branch destination address is sent from the instruction signal 115 to the sequencer 104 to control the program counter 102 through the bus 112. In the case of RTN, the contents of register 0 in register file 107 are set in program counter 102.

In the processing of the load / store instruction, first, the instruction indicated by the program counter 102 is read from the instruction cache and set in the instruction register. The sequencer 104 controls the program counter 102 based on the instruction signal 115 and the flag signal 116 from the ALU 108.
Next, the signal of the register specified by the instruction is transferred to the MAR 110. In the case of STOR, the signal of the register indicated by the S1 field in the instruction is transferred to the MDR 109. Next, in the case of STOR, the address signal 117 indicated by the MAR 110
And data signal 121 of MDR 109 to memory interface 1
01, and the memory interface 101 writes data to the memory at the corresponding address. MAR1 for LOAD
The address signal 117 indicated by 10 is transmitted to the memory interface 1
01, receives the data of the memory at the corresponding address from the memory interface 101 into the MDR,
The data of DR is transferred to the register indicated by the D field in the instruction.

An operation different from the normal operation during the self-test operation of this embodiment will be described. First, a test mode signal 133 instructing to perform a self test is externally applied. Based on the test mode signal 133, the selector 1
Reference numeral 41 does not output the instruction output from the instruction cache to the instruction register 105, but instead outputs the instruction 140 output from the random number instruction generation means to the instruction register 105. Based on the test mode signal 133, the selector 129 switches the signal output destination of the program counter 102 to the MISR 126. Further, based on the test mode signal 133, the selector 130 changes the output destination of the address signal 117 of the MAR 110.
Switch to MISR127. The test mode signal 13
3, the selector 131 outputs the data signal 1 of the MDR 109.
21 is switched to MISR128. Further, based on the test mode signal 133, the selector 132 does not transfer the data signal 122 from the memory interface by the MDR 109, but instead transfers the random number data output from the random number data generator 125. Further, based on the test mode signal 133, the random number data generators 142 and 143 output data instead of the registers in the register file 107 instructed to output data by the instruction, and the instruction to store the data is issued by the instruction. MISR144 takes in the data instead of the register in the register file.

A processing flow at the time of the self-test operation of the present embodiment will be described. First, the instruction 140 is output from the random number instruction generation means 123 and transferred to the instruction register 105. Further, the random number command generation means 123 outputs a command information signal 134 corresponding to the command 140. Next, when the instruction is a basic instruction, the sequencer 104 controls the program counter 102 based on the instruction signal 115 and the flag signal 116 from the ALU 108. Next, from the register file 107, the random number data generator 14 replaces the signal of the register indicated by the instruction.
2 and 143 output random number data on buses 118 and 119.
Through to the ALU 108. Next, the ALU 108 performs an operation. The result of the last operation is taken in via the bus 120 into the MISR in the register file instead of the register in the register file 107 designated by the instruction.
The output signal of the program counter 102 is MISR 126
It is taken in.

If the instruction is a branch instruction, if it is a BRA,
From the instruction signal 115, the branch destination address is
To the program counter 10 via the bus 112
2 is controlled. Next, the output signal of the program counter 102 is taken into the MISR 126. In the case of BRAcc, a branch destination address from the instruction signal 115 and a flag signal 116 from the ALU 108 are sent to the sequencer 104 to control the program counter 102. Next, the program counter 102
Is output to MISR 126. In the case of CALL, the contents of the program counter 102 are stored in the register file 10
Instead of being saved to the register 0 in the register 7, it is taken into the MISR in the register file 107. Command signal 1
From 15, the branch destination address is sent to the sequencer 104,
The program counter 102 is controlled through a bus 112. Next, the output signal of the program counter 102 is changed to MISR12.
Incorporated into 6. Register file 1 for RTN
The random number data output from the random number data generator in the register file is set in the program counter 102 instead of the contents of the register 0 in the register 07. Next, the output signal of the program counter 102 is taken into the MISR 126.

When the instruction is a load / store instruction, the sequencer 104 outputs the flag signal 1 from the instruction signal 115 and the ALU 108.
16 controls the program counter 102. Next, the output signal of the random number data generator in the register file 107 is transferred to the required MAR 110 instead of the signal of the register designated by the instruction. In the case of STOR, the output signal of the random number data generator in the register file 107 is changed to MDR1 instead of the signal of the register indicated by the S1 field in the instruction.
Transfer to 09. Next, in the case of STOR, the address signal 117 indicated by the MAR 110 is taken into the MISR 128, and the output data 121 of the MDR 109 is taken into the MISR 128. For LOAD, M
The address signal 117 indicated by the DR 110 is taken into the MISR 128, the output signal of the random number data generator is transferred to the MDR 109 instead of the memory interface 101, and the data of the MDR 109 is taken into the MISR in the register file. 0 In the self-test operation, a series of operations from the command signal output of the random number command generation means is repeated. The presence or absence of a failure is determined during the self-test or at the end of the MISR.
Observe output signals 136, 137, 138, 139 of
If the output signals 136, 137, 138, and 139 of the MISR are inconsistent with data obtained in advance when there is no failure, it is determined that a failure exists.
The data without the failure used for the determination can be obtained by simulating the self-test operation of the LSI of this embodiment using a logic simulator or a failure simulator.

As described above, in this embodiment, an instruction is randomly generated, data used in the execution of the instruction is provided by a random number data generator, and a register reflecting a result of the execution of the instruction, a program counter, a MAR and an MDR are provided. MI data
By repeating a series of processing of capturing by the SR, observing the MISR output signal, and comparing it with the MISR output in the case where there is no failure determined in advance, a large number of tests are performed to determine whether the instruction execution result is correct. The configuration is such that the instruction can be tested.

As shown in the present embodiment, by providing a function of randomly generating instructions, a test can be performed in a combination of the order of appearance of many instructions. Further, random number data suitable for a command to be executed can be generated based on the command information output from the random number command generation unit, so that a more efficient test can be performed.

FIG. 6 shows an embodiment of the random number command generation means. The random number command generation means is composed of a command storage means 71 for storing a command to be tested and a command selection means 72 for randomly selecting a command stored in the command storage means.

The operation starts when a test mode signal 133 instructing to perform a self test is input. First, the instruction selecting means 72 sends information on which instruction stored in the instruction storing means 71 to select to the instruction storing means 71 as a selection signal 73, and outputs the information as an instruction information signal 134. Next, the instruction storage means 71 having received the selection signal 73 outputs an instruction corresponding to the selection signal to 140.

The instruction storage means 71 of the embodiment is provided with a selection signal 7
3 can be realized by using a memory that inputs 3 as an address signal. FIG. 7 shows an example of the memory.
An address is assigned to the memory every 32 bits, and an instruction to be generated in the self-test operation is stored as a 32-bit code according to the instruction format of FIG. FIG.
In the example of the address 0000, the instruction ADD 0, R
32-bit code 0 meaning (1), R (19), R (4)
0000000000000010000011001100100, address n:
LOAD 32-bit code meaning R (1), R (4)
The n instructions are stored as 10000000000000001000010000000100.

The instruction selecting means 72 of the embodiment can be realized by a linear feedback shift register (LFSR) generally used as a pseudo random number generator. LFSR
Is to feed back the output of the last stage of the shift register to the first stage D flip-flop of the shift register, and at the same time, to provide feedback to the intermediate D flip-flop using exclusive OR. Accordingly, all the bit patterns except for the case where all the bits become 0 can be generated in a pseudo-random manner. FIG. 8 shows an example of a 33-bit LFSR. 91 is a D flip-flop, 900 to 932
Up to this is a 33-bit pseudo random pattern output signal. In the LFSR, one pseudo-random number is obtained by executing one shift operation on the D flip-flop 91 and outputting the signal value of the D flip-flop 91 that changes to the pseudo random number pattern output signals 900 to 932. .
In order to obtain a plurality of pseudo random pattern output signals, the shift operation is repeated as necessary. Since pseudo random numbers are not generated when the initial value of the LFSR is 0 in all bits, all the bits are set as initial values when the power of the LSI is turned on or when the test mode signal is set to the self-test mode. A flip-flop initialized with a combination of signal values other than when the bit signal value becomes 0 is D
Used as a flip prop 91.

From the LFSR shown in FIG. 8, output signals of the number of bits necessary to indicate an instruction stored in the memory are selected and connected as address signals to the memory, and the one-to-one correspondence with the instruction stored in the memory is selected. Is output as the command information signal 134 necessary for identification of the command output by the random number command generation means, the embodiment of FIG. 6 can be configured. Also, by taking advantage of the fact that storing the same instruction at a plurality of addresses in the memory increases the probability that the instruction selecting means will select the instruction, the random number instruction generating means sets the probability of occurrence of the instruction for each instruction. It is possible to keep.

FIG. 9 shows another embodiment of the random number command generation means. The random number command generation means stores a partial command storage means 10 for storing a part or the whole of the command to be tested.
02, an instruction supplementary information storage unit 1003 corresponding to the partial instruction stored by the partial instruction storage unit and storing information designating a missing part to make the partial instruction executable. An instruction selecting means 1001 for randomly selecting a partial instruction stored by the partial instruction storing means 1002 and instruction complementary information corresponding to the partial instruction stored by the instruction complementary information storing means; An instruction creating means for creating an instruction to be executed by the processor by supplementing random number data based on the instruction. The operation starts when a test mode signal 133 instructing to perform a self test is input. First, the instruction selecting means 1001
Information on which partial instruction to be selected stored in the instruction storage means 1002 is selected is sent to the partial instruction storage means 1002 as a selection signal 1005, and at the same time, the selection signal 1005 is selected to select the instruction complementary information corresponding to the selection information. It is sent to the command complement information storage means. The selection signal 1005 is output as the command information signal 134. Next, upon receiving the selection signal 1005, the partial instruction storage means 1002 selects the selection signal 1005
Is sent to the instruction creating means 1004. Further, the instruction complement information storage unit 1003 sends instruction complement information 1007 corresponding to the selection signal 1005 to the instruction creation unit 1004. Next, the instruction creator 1004 receives the partial instruction 1006 and the instruction complement information 1007, creates an executable instruction by supplementing random number data in a part to be complemented in the partial instruction, and outputs the instruction as the instruction 140.

The partial instruction storage means 1002 and the instruction complement information storage means 1003 of the embodiment can be realized by using a memory for inputting the selection signal 1005 as an address signal. FIG. 10 shows an example of a memory for realizing the partial instruction storage means. An address is assigned to the memory every 32 bits, and an instruction to be generated in the self-test is stored as a 32-bit code in accordance with the instruction format of FIG. 5. Of the instruction codes stored at this time, it is desired to supplement with random number data. The bit at the location is set to 0. In the example of FIG. 10, the address 0001 contains the instruction SUB
0 ,? ,? ,? 32-bit code 000000000
00000100000000000000000, address 0004 contains instruction B
RA? 32 bit code 0001000000000000
M partial instructions, such as 0000000000000000, are stored. Where in the meaning of the instruction? Is a symbol indicating a field complemented by random number data in the instruction code. For example, in the case of the address 0001, the 17th to 31st bits of the instruction code are complemented with random numbers, and all corresponding bits are stored as 0. FIG. 11 shows an example of a memory for realizing the instruction complement information storage means. The memory is assigned an address every 32 bits, and the instruction complement information is represented by 32 bits. Each partial instruction stored in the memory of FIG. 10 and instruction complement information corresponding to each partial instruction are stored so as to have the same address. The format of the instruction complement information corresponds to the partial instruction stored by the partial instruction storage means,
It is assumed that a bit indicating complementing by random number data in the partial instruction is set to 1 and other bits are set to 0. In the example of FIG. 11, the address 0001 corresponds to the partial instruction of FIG.
And the other bits are 0, a 32-bit code 0000
The 0000000000000111111111111111 and the address 0004 store a 32-bit code 00000000111111111111111111111111 in which the 8th to 31st bits indicating the branch destination address of the branch instruction are 1 and the 0th to 7th bits are 0.

FIG. 12 shows a detailed embodiment of the instruction creating means 1004. The instruction generating means generates a 32-bit pseudo-random number pattern which starts operation when a test mode signal 133 instructing to perform a self-test is generated.
1301 and a 32-bit A that inputs two 32-bit data, calculates a logical product for each bit, and outputs the result
It comprises an ND calculator 1302 and a 32-bit OR calculator 1303 that inputs two 32-bit data, calculates a logical sum for each bit, and outputs the result. The operation is
First, the instruction complement information 1 output by the instruction complement information storage means
The logical AND for each bit of the pseudo-random number data 007 and the pseudo-random number data output by the LFSR 1301 is calculated, and 32-bit data in which random number data is given only to bits that need to be complemented is created. Next,
The logical sum for each bit of the 2-bit data and the partial instruction 1006 output by the partial instruction storage means is calculated, random number data is obtained in a portion requiring complementation, and the instruction 140 is output.

The instruction selecting means 1001 uses the L shown in FIG.
It can be realized by FSR. From the outputs of the LFSR, outputs for the number of bits required to indicate the contents of the memory for storing the partial instruction and the memory for storing the instruction complement information are selected and connected as an address signal. The memory receiving the address signal outputs the data of the corresponding address as a partial instruction 1006 and instruction complement information 1007. If the address signal is output as the command information signal 134, the command output by the random number command generation means can be identified. In the configuration of the above embodiment, it is efficient that the number of partial instructions stored in the memory is a number represented by a power of 2 as in the embodiment of FIG. 6, but the output of the LFSR is stored in the memory. It may be normalized to a certain partial instruction number m. Also, by taking advantage of the fact that the same partial instruction is stored at a plurality of addresses in the memory, the probability that the instruction selecting means selects the partial instruction increases, the occurrence probability of the instruction generated by the random number instruction generating means is calculated for each partial instruction. Can be set to

In the embodiment shown in FIG. 9, since an instruction is created by supplementing a part of the instruction with random number data, a test can be performed with a wider variety of instruction combinations than the embodiment shown in FIG.

FIG. 13 shows a detailed embodiment of the random number data generator used in the embodiment of FIG. The random number data generator includes a plurality of 32-bit random number generators 1401 to 1403, a selector 1404 for selecting one from the output data of the random number generator and outputting the selected data as random number data 1406, and a command information signal 134. And enter
The random number data generator determines whether or not to output random number data, and if so, sends information for selecting an output of the random number generator corresponding to the command information signal to the selector, and the information is selected by the information. And a decoder 1405 having a function of outputting a signal for instructing an operation to a random number generator. In addition, the random number generators 1401 to 1403 output data corresponding to a data format necessary for enabling a test item assumed for an instruction identified by the instruction information to be testable, corresponding to the instruction information 134.

The processing flow is as follows.
3, the decoder 1405 determines whether or not the random number data generator should output random number data, and if it should, outputs random number data corresponding to the instruction information. And a decoder that outputs a random number data corresponding to the instruction information to the selector 1404.
One random number generator 1403 is instructed to output random number data. Next, the random number generator receiving the instruction outputs the random number data to the selector 1404. Next, the selector 14
04 outputs random number data output from the random number generator designated by the decoder 1405 as random number data suitable for the command information signal 134. According to the random number data generator of this embodiment, random number data corresponding to the data format necessary for enabling a test item assumed for the command identified by the command information in response to the command information signal 134 to be applied to the command Is output as random number data conforming to.

The random number generator that outputs random number data conforming to the command information signal can be easily realized by using an LFSR and a combinational circuit that receives the output of the LFSR as an input. For example, if a portion where bit data is fixed is required as data for testing a certain instruction a, a circuit for masking the output of the LFSR may be added. As a specific example, a load instruction in the processor of the embodiment of FIG. 1 is shown. Load instruction LOAD R (S1), R
(D) is an instruction to transfer data on the memory whose address is the data of the register designated by S1 to the register designated by D. In order to perform a test for executing the instruction by changing the address at random in the instruction,
When the data output by the random number data generator is used instead of the data of the register designated by 1, the data output by the random number data generator is also expressed by 24 bits because the address space is limited to 24 bits. Need to be The random number generator that outputs random number data conforming to the load instruction is shown in FIG. The random number generator includes an LFSR 1902 that outputs a 32-bit pseudo-random number and a combinational logic circuit 1903 that performs an 8-bit AND operation.

In the processing flow, when the operation instruction signal 1901 sent from the decoder 1405 is input, the LFSR outputs a 32-bit pseudo random number pattern. Next, a signal of the upper 8 bits of the 32-bit pseudo-random number pattern is sent to an AND operation circuit 1903, and the operation circuit 1903 performs an AND operation with a signal in which all 8 bits are 0, and all 8 bits are 0. Is output. Finally, data obtained by combining the data 1905 and the lower 24-bit data 1904 of the 32-bit pseudo random number pattern is output as 32-bit data 1906 suitable for the load instruction.

Further, in the case where data in which the occurrence probabilities of 0 and 1 are adjusted for each bit as data conforming to the instruction b having a data format necessary for testing a test item assumed for a certain instruction b is required, Designing a combinational circuit based on the fact that the output probability of 1 is increased if the logical sum of the outputs of a plurality of bits of the LFSR is output, and that the output probability of 0 is increased if the output is the logical product, to construct a random number generator it can. In addition, a set of bit patterns is prepared as data conforming to the instruction c, and when a pattern selected at random from the set is used as the data conforming to the instruction c, a memory storing the bit pattern is used. This can be realized by using the LFSR and using the output of the LFSR to generate a data read address of the memory.

FIG. 17 shows another embodiment of the random number data generator used in FIG.

The random number data generator receives the command information signal 134, determines whether or not the random number data generator should output random number data. If the random number data should be output, the LFSR
Signal 18 for instructing 1807 to output pseudo random number data
09, a function of sending information 1808 for selecting random number data suitable for the instruction information to the selector 1804, an LFSR 1807 for outputting 32-bit pseudo-random number data,
Instruction adapting means 1801 to 180 for changing 2-bit data to random number data adapted to the instruction identified by the instruction information signal 134 and outputting to the selector 1804
3 and a selector 1804 for selecting and outputting random number data conforming to the instruction information from the output of the instruction adaptation means based on the selection information 1808.

The processing flow is as follows.
Upon input of the command information signal 134 output from 23, the decoder 1805 determines whether or not the random number data generator should output random number data, and if it should output random number data, it outputs random number data corresponding to the command information. Information 1808 for selecting an instruction adaptation unit to be output is output to the selector 1804, and the decoder sends a signal 1809 to the LFSR 1807 to output pseudo-random number data. Next, the LFSR 1807 receiving the instruction converts the pseudo-random number data into the instruction matching means 180.
1 to 1803. The instruction adaptation means includes the LFS
The pseudo random number data obtained from R is changed to be pseudo random number data suitable for the instruction, and is output to the selector 1804. Next, the selector 1804 selects, based on the selection information 1808, pseudo-random data matched with the instruction information signal 134 from the pseudo-random data output by the instruction adaptation unit, and a random number matched with the instruction identified by the instruction information signal 134. The data is output as data 1806.

As a specific example of the instruction adapting means in this embodiment, a load instruction in the processor of the embodiment in FIG. 1 is shown. The load instructions LOAD R (S1) and R (D) are
This is an instruction to transfer data on the memory whose address is the data of the register designated by S1 to the register designated by D. In the case of using the data output by the random number data generator in place of the data of the register designated by S1 in order to perform a test for executing the instruction by changing the address at random in the instruction, the address space is 24 bytes. Since the number of bits is limited, the data output from the random number data generator must also be represented by 24 bits. LFSR18
FIG. 19 shows instruction adaptation means for changing the pseudo-random number data output from 07 so as to conform to the load instruction. The instruction adapting means includes a combinational logic circuit 2001 for performing an 8-bit AND operation and a through circuit 2002 for outputting a 24-bit signal as it is without any change.

FIG. 14 shows a detailed embodiment of the register file in the embodiment of FIG. The register file has two read ports, one write port, and 32 registers for storing data. The test mode signal switches the output signal of the register to the output signal of the random number data generator and outputs the data bus. , Output selectors 1500 and 1501, which output 32-bit data as a response analyzer, and an input switch which outputs write data to a register input from the bus 120 to the MISR by a test mode signal. In a normal operation, write data input from the bus 120 is stored in a register specified by an instruction. The data of the register selected by the instruction is output to the bus 118 and the bus 119.
In the self-test operation, write data input from the bus 120 is sent to the MISR 1505 by the input switch, and is taken into the MISR. The data of the register selected by the instruction is switched by the output selector, and the output data of the random number data generators 1503 and 1504 are output to the buses 118 and 119 instead.

In the embodiment of FIG. 1, when the test mode signal indicates the self-test mode, the sequencer 1
FIG. 15 shows an embodiment of a configuration in which the random number data output means outputs a signal instead of one or more storage elements in 04. The sequencer is a sequential circuit, and the combinational circuit unit 1601
And (i) storage elements 1604 to 1606. When the test mode signal 133 indicates a self-test, the selectors 1602 and 1603 set the memory element 160
Instead of 5 and 1606, output signals 1607 and 1608 of the random number data generator 1609 are output. The random number data generator may connect two bits from the output of the LFSR shown in FIG. In the present embodiment, two storage elements are targeted for switching by the selector. However, the present invention is not limited to this, and a configuration targeting one or more storage elements is possible. By introducing the configuration of the present embodiment, even when the random number instruction generation / generation unit generates a command other than a branch instruction, it is possible to perform a test in which the data of the program counter has diversity.

FIG. 16 shows the configuration of the MISR in the embodiment of FIG. MISR is generally used as a response analyzer in the BIST function, and LFSR
Is configured to input a signal using exclusive OR for each bit of. 171 is a D flip-flop, 1700
Reference numerals 1732 to 1732 denote data input signal lines each having a 33-bit configuration, and connect signals necessary for data to be captured to the data input signal lines. The data is fetched by taking the exclusive OR of the output of each DFF and the fetched data into each DFF when performing the shift operation. The shift operation accompanying the data fetch is repeated to compress the fetched data.

According to the present invention, by providing a function of randomly generating test instructions, a test can be performed in a combination of the order of appearance of many instructions. Also, random number data suitable for the command to be executed can be created by the command information output from the random number command generation means,
More efficient testing becomes possible. As a result, a high failure detection rate can be achieved. In addition, a high-speed test can be performed by realizing the random number instruction generation unit and the random number data output unit by hardware.

[0051]

According to the present invention, a high failure detection rate can be achieved and a high-speed test can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a processor showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional BIST.

FIG. 3 is a diagram showing instructions of the processor of FIG. 1;

FIG. 4 is a diagram showing an instruction format of the processor of FIG. 1;

FIG. 5 is a diagram showing details of an instruction format of the processor of FIG. 1;

FIG. 6 is a configuration diagram showing an embodiment of a random number instruction generation means in FIG. 1;

FIG. 7 is a diagram showing the contents of a memory that realizes an instruction storage unit in FIG. 6;

FIG. 8 is a configuration diagram of a linear feedback shift register (LFSR) that generates a pseudo random number.

FIG. 9 is a configuration diagram showing another embodiment of the random number instruction generation means in FIG. 1;

FIG. 10 is a diagram showing the contents of a memory which realizes the partial instruction storage means in FIG. 9;

FIG. 11 is a diagram showing the contents of a memory that implements the instruction complement information storage means in FIG. 9;

FIG. 12 is a block diagram showing a detailed embodiment of an instruction creating means in FIG. 9;

FIG. 13 is a configuration diagram showing an embodiment of a random number data generator in FIG. 1;

FIG. 14 is a configuration diagram showing an embodiment of a register file in FIG. 1;

FIG. 15 is a configuration diagram showing an embodiment of a sequencer according to the present invention.

FIG. 16 is a configuration diagram of a multiple input signature register (MISR).

FIG. 17 is a configuration diagram showing another embodiment of the random number data generator in FIG. 1;

FIG. 18 is a diagram illustrating a specific example of a random number generator in FIG.

FIG. 19 is a diagram showing a specific example of the instruction adapting means in FIG. 18;

[Explanation of symbols]

101: memory interface, 102: program counter (PC), 103: instruction cache, 104: sequencer, 105: instruction register, 106: decoder, 1
07: Register file, 108: ALU (Arithmetic
Logical Unit) 109 Memory data register (MD
R), 110 ... memory address register (MAR), 1
23: random number command generation means, 125: random number data generator
126, 127, 128: Multiple input signature register (MISR); 129, 130, 131, 132: Selector; 133: Test mode signal; 134: Command information signal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazumi Hatakeyama 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Takashi Hotta 7, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1-1 F term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 5B048 AA20 CC11 DD01 DD06 DD10 DD15 DD16

Claims (9)

[Claims] 1. A program counter for indicating an instruction to be executed, an instruction register for storing an instruction specified by the program counter, a register for storing data, and reading an instruction stored in the instruction register. An arithmetic unit that reads data stored in the register based on the read instruction, executes an operation, and stores data as an operation result in the register, and issues a test instruction based on a test signal input from the outside. A random number instruction generating means for randomly generating the instruction; 2. The processor according to claim 1, wherein said random number instruction generation means stores a test instruction generated based on said test signal in said instruction register. 3. The processor according to claim 1, wherein said random number instruction generation means generates a test instruction at random and outputs a signal for outputting data adapted to said instruction from said register. 4. The processor according to claim 1, wherein said random number command generation means has a plurality of commands, and determines and outputs the command based on a preset probability. 5. A program counter for designating an instruction to be executed, a register file having a plurality of registers for storing data, and a data stored in the register file based on an instruction designated by the program counter. An arithmetic unit that reads and executes an operation and stores data as an operation result in the register; a random number instruction generation unit that randomly generates a test instruction based on a test signal input from the outside; A processor comprising: random number data output means for outputting random number data for executing a calculation; and a response analyzer for storing a calculation result based on the random number data. 6. The processor according to claim 5, wherein said response analyzer captures an output signal of said program counter based on said test signal. 7. The instruction storage device according to claim 1, wherein the random number instruction generation unit stores an instruction to be executed by a processor, and an instruction selection unit that randomly selects an instruction from the instruction storage unit. And a processor. 8. The method according to claim 1, wherein
The random number command generation unit includes a partial command storage unit that stores a part or the entirety of an instruction to be executed, and a command that can execute the partial command corresponding to the partial command stored by the partial command storage unit. Command information storing means for storing information designating a missing part, and randomly selecting the partial command from the partial command storing means and the command complementary information corresponding to the partial command from the command complementary information storing means. And a command generating means for generating an instruction to be executed by the processor by supplementing random number data based on the selected partial instruction and the instruction complement information. 9. An information processing system comprising: a memory for storing a program or data; and a processor connected to the memory and for reading data stored in the memory or writing data to the memory. The processor includes: an instruction register that outputs an instruction to be executed; a plurality of registers that store data; an address register that stores an address for accessing the memory; and data that is stored in the memory. A data register for storing data read from the memory, an arithmetic unit for performing an arithmetic operation on the data stored in the plurality of registers or the data register according to an instruction output from the instruction register, and Command to randomly generate an instruction and store it in the instruction register. The information processing system comprising a generator, the computing unit is performed in accordance with the instruction output from the instruction generator and a response analyzer captures the data stored in the data register.