TW472189B - Processor with best function - Google Patents

Abstract

Self-testing can be implemented by providing random-number instruction generator 123, which generates testing instructions randomly, and random-number data generators, which generates and sends random-number data based on instruction information signals 134 created by the random-number instruction generator.

Description

472189 A7 B7 V. Description of the invention (1) Background of the invention (please read the notes on the back before filling this page) The present invention relates to a built-in self-test (BIST) technology, which can quickly perform logic circuits with self-test functions. Testing and highly accurate error detection. The test method generally used to detect errors in logic circuits is to input preset test data into the circuit from the outside and then observe the resulting output response. However, for logic circuits of ever-increasing size, the capacity of the input test data also increases, which will lengthen the test time and increase the required test cost. Therefore, it is urgent to use B I S T technology to reduce the test cost, so as to use the built-in self-test circuit to self-test the logic circuit. The conventional BIST technology department disclosed "A Tutorial on Built-In Self-Test", published in March 1993, on pages 7 3-82, and June 1993 Issued in "IEEE DESIGN & TEST 〇F COMPUTER" magazine, pages 69-77. The printed B I S T (shown in Figure 2) by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is composed of a test control section, a pattern generation section, and a response analyzer. The output signal from the graphics generator is sent to the circuit for testing, and the resulting response number is input to the response analyzer, and its status is monitored to detect errors. Graphics are produced by one of two main methods. One method is to store the preset test data and test program in ROM, etc., and transfer the data and program to the circuit to be tested. For this method, because the test data must be stored in memory, the capacity of the data to be stored in the logic circuit is limited. Therefore, although it can be detected that the test capital paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -4- 472189 A7 __ B7 V. Description of the invention (2) (Please read the precautions on the back first Fill out this page again), but no other errors were detected. Another method is to use a virtual random number generator (p s e u d 〇-r a n d 0 m n u m b βι-δ e n e r a t 〇 r). The use of the virtual random number generator can generate a large number of virtual random numbers printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and transmitted to the circuit to be tested. However, if you want to test the § tongue of a sequence circuit in order, it is not easy to cause all state changes, and even if you are testing a combination circuit, because it may produce an undetectable state, this kind of virtual random number It is difficult to achieve a high false detection rate with this method. In this case, although a circuit can be added to directly assign the virtual random number to the internal storage device so as to process the sequence circuit as a combination circuit, the added circuit will cause difficulties in fast circuit operations and / or increase the circuit Area range. An example of combining the above two patterns is disclosed in Japanese Patent Application Laid-Open No. 5-120052 (1993). In this method of using the microprocessor's instruction execution function (instruc 11 ο ne X ecuti ◦ nfunc 11 ο η) to perform the test, the test program is stored in memory, and the data used by the program uses virtual random Number generator to generate. In this circuit structure, the input of the test mode specification signal (testm odespecificati ◦ nsigna 1) is set to the self-test mode, and when the test command stored in the program memory is executed in advance, the desired input is automatically generated. The test data of the test target (ie, the arithmetic logic unit ALU), and the virtual random number is standardized according to a specific state of a status flag in the circuit. Therefore, a large amount of test data is available for the test instructions. However, because the test instructions are stored in the memory, even with this method, the number of combinations of instructions to be tested is limited 'and this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) -5- 472189 A7 B7 V. Description of the invention (3) This will also cause some logic tree circuit elements whose operation order is different from the order in which the instructions appear to have many untestable tests. (Please read the precautions on the back before filling this page) As shown in the above-mentioned conventional example, the use of conventional self-test methods will cause insufficient testing of the test data stored in the memory 'and the above only uses virtual The random number generator method will increase the burden on the circuit, that is, it will slow down the operation speed and increase the area of the circuit. Even combining the two methods described above (i.e., a test method using a processor's instruction execution function) 'may cause a problem that the number of instruction combinations is limited. In order to use B I S T to achieve fast test and high error detection rate ', the above problems must be solved. The object of the present invention is to provide a mechanism 'which can quickly test operations' and test a large number of instruction combinations. In order to achieve the above-mentioned objective, the processor of the present invention is characterized by having a function of randomly generating test instructions, thereby performing fast arithmetic testing and being able to test a large number of instruction combinations. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Yes, a processor is characterized by providing a processor with the following components to achieve fast computational tests and test a large number of instruction combinations: a program counter 'is used to specify the instructions executed by the processor; an instruction register is used to Store the instructions specified by the program counter; the register 'is used to store data; the arithmetic logic unit' is used to download the instructions from the instruction register, and then read the data from the data storage register according to the downloaded instructions, And perform arithmetic operations and store the arithmetic result data in a data storage register; and a random number instruction generator 'for randomly generating test instructions based on externally input test signals. A processor is characterized by also providing a paper size with the following components to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 6-472189 A7 V. Description of the invention (4 processors to achieve fast Operation tests and test-type counters to specify the instructions to be executed; a plurality of registers capable of storing data; instructions specified by the arithmetic program counter perform arithmetic operations from the registers, and the arithmetic results are stored in the funds; A random number instruction generator is used to randomly generate test instructions based on external data; the random number data output is transmitted to an arithmetic logic unit to perform arithmetic operations to store arithmetic results based on the random number data. In order to meet the above purpose, a large number of Instruction combination: a process register file, which has a logic unit 'for downloading data from the file, and it is expected to store the test signal input by the data register unit to' use random numbers' and a response analyzer, economically The Intellectual Property Bureau employee consumer cooperative prints memory and connects to the store, in this case , Try a large number of command combinations, which are used to access the memory and stored in the memory or the slave unit, so that they can be stored in multiple registers according to the instructions or used to instruct the temporary according to external signals. And is configured to receive data produced in the data register according to instructions in order to satisfy the above-mentioned destination memory and to connect to the storage, in which case the memory processor may additionally include an address; The memory register data is temporarily generated randomly in the arithmetic generator. The processing implementation is fast. It contains: the bit data is temporarily read and the output register is in the middle of the instruction logic. The single output refers to a temporary address register with a device to facilitate the speed. The data of the issued instruction, and the calculation tester of the order or data in the order can be used to store materials; calculate to calculate; after the instruction responds to the branch, the data is read and the data is stored. The logic of the memory of desire is stored in the parser. If it is stored, a program or data storage can be used to facilitate data reading and memory processing. Can realize fast paper size applicable to Chinese national standard (CNS> A4 specification (210 χ 297 mm) ---------.—. Installed --------- order. (Please read first Note on the back? Matters should be filled out on this page again) 472189 A7 B7 V. Description of the invention (5) (Please read the notes on the back before filling out this page) Try a large number of instruction combinations, which additionally include: instruction register To output the instruction to be executed; a plurality of registers are used to store data; an address register is capable of storing the address required to access the memory; a data register is used to store the data to be stored in Data in memory or data to be read from memory; arithmetic logic unit, which can calculate those that have been stored in multiple registers or data registers according to the instructions output by the instruction register. Data; an instruction generator for randomly generating instructions based on an external signal and storing the instructions in an instruction register; and a response analyzer provided in the arithmetic logic unit to receive those instructions based on the output instructions of the instruction generator Data stored in the data register after execution material. In addition, the random number instruction generator can store different data in the instruction register, or generate randomly different test instructions and generate the output signals required by those registers to send the instruction-related data 'or Select the instructions according to the preset probability data (P reset ρ 1: 〇bab 1111 ydata) and send them, or combine the above methods to test a large number of instruction combinations. In addition, the random number instruction generator in the above processor can test a large number of instruction combinations by the following procedures: Semi-instruction (P artia 1-instruc 11 ο η) storage mechanism printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs' It is used to store some or all of the instructions to be executed. Instruction-complementary information storage mechanism is used to store the supplementary information needed to execute the half-instructions in the half-instruction storage mechanism. The semi-instruction storage mechanism and supplementary standards are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ 472189 A7 B7 V. Description of the invention (6) The semi-instruction and corresponding supplementary instructions are randomly selected in the instruction information storage mechanism Information; and a mechanism for supplementing the random number data according to the selected half instruction and supplementary instruction information to generate an instruction that the processor wants to execute. In addition, when the required test mode signal is designated as a self-test, it can be performed by transmitting data output from the random number data output mechanism (instead of transmitting data in the register in the register file). A large number of command combination tests, in which the register in the register file is specified by the corresponding command to transmit the data: and can receive data from the response analyzer (instead of receiving the register file) The data in the register) 'Wherein the register in the register file is designated by the corresponding instruction to store these data. In addition, when the required test mode signal is specified as a self-test, 'the response analyzer of these processors can receive counts from individual programs by $ @ output signal' from the processor's memory access address and from individual data Register output for fast arithmetic testing. The drawing is a simple illustration. Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by a cooperative. Figure 1 is a block diagram showing a processor according to an embodiment of the present invention. Figure 2 shows the structure using the conventional BI ST technology. FIG. 3 is a table listing the instructions of the processor of FIG. FIG. 4 shows the instruction format of the processor of FIG. 1. Figure 5 is a detailed explanatory diagram showing the instruction format of the processor of Figure 1-9-------------- install --------- order · (Please read the back first Please pay attention to this page and fill in this page again) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 472189 Α7 --- B7 V. Description of the invention (7) Figure 6 is a block diagram showing Figure 1 An embodiment of a random number instruction generator. (Please read the precautions on the back before filling out this page) Figure 7 shows the memory content of the instruction storage mechanism in Figure 6 Figure 8 is a block diagram of a linear feedback displacement register (LSFR) 'The LSFR system Used to generate virtual random numbers. FIG. 9 is a block diagram showing another embodiment of the random number instruction generator in FIG. 1. FIG. FIG. 10 shows the memory contents of the half-command storage mechanism of FIG. 9. FIG. 11 shows the contents of the memory of the supplementary instruction information storage mechanism of FIG. 9. Fig. 12 is a block diagram showing a detailed embodiment of the instruction generator of Fig. 9. FIG. 13 is a block diagram showing an embodiment of the random number data generator of FIG. 1. FIG. Fig. 14 is a block diagram showing an embodiment of the register file of Fig. 1 Fig. 15 is a block diagram showing an embodiment of the sequencer of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 16 is a block diagram of a multiplexed input mark register (M I S R). FIG. 17 is a block diagram showing another embodiment of the random number instruction generator of FIG. 1. FIG. FIG. 18 is a diagram showing another specific embodiment of the random number instruction generator of FIG. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) _ 472 189 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) Scheme. Of the command adaptation mechanism of another specific real component 17 7 1 7 2 7 3 0 4 0 7 10 7 D-Positive and negative device instruction storage mechanism instruction selection mechanism selection signal D-Positive and negative device memory interface program Counter instruction cache memory sequencer instruction register decoder register file arithmetic logic unit memory data register memory address register bus bus bus command signal flag signal address signal (please read the back first Please pay attention to this page and fill in this page again) i «—I vt ^^ 1 UK nn -1 ° ', > nnm I-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -11-472189 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (9 0 7 0 4 3 7 3 8 3 9 4 0 4 1 4 2 Bus Bus Bus Bus Data Signal Data Signal Random Number Command Generator Random Data generator multiplexer input marker register multiplexer input marker register multiplexer input marker register selector selector selector selector test mode signal instruction information signal test mode signal output No output signal of the output signal output instruction random number selector data generator (Please read the notes and then fill in the back of this page)

BI nn 口 π I nn I ^^ 1 n In I This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -12-2 7 4 8) Λ7 B7 V. Description of the invention (10 14 3 14 4 9 0 0-9 3 2 10 0 1 10 0 2 10 0 3 10 0 4 0 0 7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 0 1 4 0 2 4 0 3 4 0 4 4 0 5 4 0 6 5 0 0 4 Random number data generator Multiplex input marker register Virtual random number pattern output signal Instruction selection mechanism Half instruction storage mechanism Supplementary instruction information Storage mechanism instruction generator selection signal Half instruction supplementary instruction information Linear feedback displacement temporarily Register and gate calculator or gate calculator random number generator random number generator random number generator selector decoder random number data output selector output selector random number data generator random number data generator multiplex input flag temporarily Register (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -13-3 2 7 4 A7 B7 V. Description of the invention (11 4 0 0 7 0 8 7 0 8 0 8 0 8 0 17 4 8 0 7 8 0 8 8 0 9 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 19 0 3 19 0 5 2 0 0 1 2 0 0 2 Selector Selector Storage Device Storage Device Storage Device Output Signal Output Signal Random Number Data Generator Data input signal line instruction adaptation mechanism instruction adaptation mechanism instruction adaptation mechanism selector decoder linear feedback displacement register output information random number data output instruction signal operation instruction signal linear feedback displacement register combination logic circuit data combination logic circuit Not competing (please read the precautions on the back before filling this page) Loading ----- Ordering-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 472189 Λ7 B7 5 (12) Description of the preferred embodiment The embodiment of the present invention will be described in detail below. Fig. 1 shows a LSI structure including a processor, which is an embodiment of the present invention. In this figure, 1 〇1 is a memory interface 'can be exchanged through the exchange ?; [lj row 1 1 1 and exchange signals with the memory billion; 1 〇 2 is a program counter; 103 is the instruction cache memory; 1 0 4 Sequencer used to control the program counter: 105 is the instruction register; 106 is the decoder 'used to decode the contents of the instruction register, and used to control the arithmetic logic unit and other components; 1 〇 7 is a temporary register file, which contains a random number data generator for random data output and a multiplexed input tag temporary register (M IRS) as a response analyzer; 108 is an arithmetic logic unit (ALU); 1 0 9 Is a memory data register (MDR) for exchanging data with the memory; 1 10 is a memory address register (MAR) for assigning an address to the memory interface; 1 2 3 is a random number The instruction generator is used to randomly output the instructions required for self-test; 1 2 5, 14 2 and 1 43 are the random number data generators to output the random number data; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ β --------- Order. (Please read the notes on the back before filling in this page) 1 2 6, '' 1 2 7, 1 2 8 And 1 4 4 are ^ 13 feet of the response analyzer; 129, 130, 131 '132 and 141 are selectors, which have been used during normal mode and test mode Exchange signal flow; In addition, 1 3 3 is the test mode signal input from outside the LSI to specify the self-test mode; 1 3 4 is the instruction information pair number, used to indicate the output instruction of the random number instruction generator 1 2 3 1 4 0 content. Except for receiving the instruction information signal 1 3 4, the paper size of the random number in this embodiment applies the Chinese National Standard (CNS) A4 specification (21 × X 297 mm). 15-472189 Λ7 B7 V. Description of the invention (13) Information The generator can also change the random number data generating method, so that the random number data output of the generator can be more consistent with the instructions transmitted by the random number instruction generator 1 2 3. The output signals from 1 4 4, 1 2 6, 1 2 7 and M I S R 1 2 8 respectively are transmitted to the outside of the processor. The processor instruction table in this embodiment is listed in FIG. 3. All basic instructions are internal register arithmetic operation instructions. This embodiment provides four types of branch instructions: unconditional branch instruction BRA, and conditional branch instruction BRA cc (& cc 分支 indicates a branch condition) 'branch-into-subroutine instruction CALL , And the return-from-subroutine instruction RTN. In addition, a load instruction LOAD and a store instruction S T 0 R E are also provided. In addition, the address spaces that can be specified in branch instructions (load instructions and store instructions) are all represented by a 24-bit pattern. Figure 4 shows its instruction format. All instructions have a fixed length of 32 bits. The `` f '' bit in the basic instruction format is used to indicate whether the operation result is to be included in the flag. And "S 1 〃 ， ， s 2 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---------- 1 -Bi -------- Xun- (Please read the back Please fill in this page again) The 〃 and w D 〃 fields indicate the first source field, the second source field, and the destination address, respectively. In addition, d 中 in the branch instruction format indicates the address of the branch destination. FIG. 5 shows a detailed instruction format used in FIG. 4 to indicate the definition of an operation code (〇 P c 〇 de e). Bits 0 to 7 in the basic instructions are all set to * 〇〃, and bit 4 to 7 in the branch instruction are also set to this paper standard applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) .- j6. 472189 A7 _ B7 V. Description of the invention (14) * 0 〃 ', and bits 8 to 3 1 enter the branch destination address. Loading (Please read the precautions on the back before filling this page) Bits 16 in the instruction and storage instructions are set to '1', and the bit of bit 〇 is used to identify L 0 AD or ST 〇RE . Next, the processing flow of the processor in this embodiment during the normal mode will be described in detail. In the basic instruction processing period of the normal mode, the instruction designated by the program counter 10 is read from the instruction cache memory 103 and set in the instruction register 105. In addition, the instruction signal 1 15 and the flag signal 1 16 from the arithmetic logic unit 1 · 08 are also transmitted to the sequencer 104 to control the program counter 1Q2. Next, the instruction specifies that the register data is transferred from the register file 1 0 7 to the arithmetic logic unit 1 0 8 through the buses 1 8 and 1 1 9, and then the arithmetic logic unit 10 8 will process the data . Finally, the obtained A L U operation result is stored in the register designated by the instruction in the register file 107 through the bus 1 2 0. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs During the processing of branch instructions, the instruction designated by the program counter 102 is first read from the instruction cache. Then, for BRA, the address of the branch destination is transferred from the command signal line 1 15 to the sequencer 104 to control the program counter 10 through the bus 1 12. For BRA cc, the address of the branch destination and the flag signal 1 1 6 from ALU 1 0 8 are transmitted to the sequencer 1 0 4 through the instruction signal line 1 1 5 to control the program counter 1 0 2 . For CALL designation, the contents of the program counter 102 are stored in the register 0 of the register file, and the address of the branch destination is transmitted from the command signal line 115 to the sequencer-17-this paper The standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472189 A7 B7 V. Description of the invention (15) 1 04, in order to control the program counter 2 through the bus 1 12. For the RTN instruction, the contents of register 0 in the register file are set in program counter 102. During the processing of the load or store instruction, the instruction designated by the program counter 102 is first read from the instruction cache memory and set in the instruction cache memory. Then, the command signal 1 15 and the flag signal 1 1 6 from the arithmetic logic unit 10 8 are also transmitted to the sequencer 1 0 4 for controlling the program counter 10 2. Then, the instruction designation register signal is transmitted to M A R 1 1 0. For S T 0 R, the register signal specified by the S 1 field in the instruction is forwarded to MDR109. Then, for STOR, the address signal 1 1 7 designated by MAR 1 1 0 and the data signal 1 2 1 from MDR 1 0 9 are transmitted to the memory interface 1 0 1, so that the data can be stored in Relative memory location. For L 0 AD, the address signal designated by MAR 1 1 0 1 1 7 is transmitted to the memory interface 1 0 1 and the memory data at the relative address IJ is transmitted from the memory interface 1 0 1 to MDR, and the MDR data is then transferred to the register specified by the D field in the instruction. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The self-test operation in this embodiment is different from that in the normal mode. First, the test mode signal 1 3 3 for specifying the self-test is input from the outside of the processor. According to the test mode signal 1 3 3 ′, the output instruction 1 4 0 from the random number instruction generator (instead of the output instruction of the instruction cache memory) is transmitted to the instruction register 1 0 5 through the selector 141. According to the test mode signal 1 3 3, the selector 1 3 0 select -18-(Please read the precautions on the back before filling this page) This paper size is applicable _ National Standard (CNS) A4 specification (210 X 297 mm> 472189 Α7 Β7 V. Description of the invention (16) MI SR1 2 7 is the output destination of the address signal 1 1 7 of MARI 1 0. Similarly, according to the test mode signal 1 3 3, the selector 1 3 1 selects Μ ISR 1 2 8 is the output destination of the MDR 1 009 data signal 1 2 1. In addition, according to the test mode signal 1 3 3, the random number data output by the random number data generator 1 2 5 (not the data from the memory interface) The signals 1 2 2) are transmitted to the MDR 1 〇 9 through the selector 丨 3 2. In addition, according to the test mode signals 1 3 3, the random number data generators 1 2 4 and 1 4 3 (instead of the register file χ 〇7 temporary storage benefits) transmission of data 'then the M ISR 1 4 4 (not the register in the register file) to receive the data. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Next, the processing flow of the processor of this embodiment during the self-test will be detailed below. First, the random number instruction generator 1 2 3 generates an output instruction 1 4 0 and transmits it to the instruction register 1 0 5. In addition, the random number command generator 1 2 3 also sends a command information signal 1 3 4 corresponding to the output command 1 40. Then, if the instruction is a basic instruction, the instruction signal 1 15 and the flag signal 1 1 6 from the arithmetic logic unit 10 8 are transmitted to the sequencer 104 to control the program counter 10 2. Next, the random number data from the random number data generators 1 2 2 and 1 4 3 (instead of the register buffer signal specified by the instruction) are obtained from the register file 1 07 through the buses 1 1 8 and 1 1 9 It is transmitted to the arithmetic logic unit 108, where the data is calculated in the arithmetic logic unit 108. Finally, the operation result is stored in the internal register of MI SR through the bus 120 (not the register specified by the instruction in the register file 107). The output signal from the program counter 1 〇2 is also input to Μ ISR -19- I --------- 丨 -I equipment ------------ order Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm) 472189 A7 ---- B7 V. Description of the invention (17) 1 2 6 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -----------.- Pack --------- Order (Please read the precautions on the back before filling this page) In the branch During the instruction processing period, for the BRA, the address of the branch destination is transmitted from the instruction signal line 1 15 to the sequencer 1 104 to control the program counter 1 2 through the bus 1 1 2. Then, the output signal of the program counter 102 is transmitted to M IS R 1 26. For the BRA cc, the address of the branch destination and the flag signal 1 1 6 from ALU 1 0 8 are transmitted to the sequencer 1 〇 4 through the command signal line 1 1 5 to control the program counter 1 〇 2 . Then, the output signal of the program counter 102 is transmitted to the MI SR126. For CALL designation, the contents of the program counter 1 ◦ 2 are stored in the internal M ISR of the register file 107 (not in the register 0 of the register file). And the address of the branch destination is also transmitted from the command signal line 1 15 to the sequencer 104, so that the program counter 1 102 can be controlled through the bus 1 12. For the R T Ν instruction, the random number data output from the random number data generator in the register file (not the content of register 0 in the register file) is set to the program counter 1 〇 2 in. Then, the output signal of the program counter 10 is transmitted to M I s R 12 6 ° During the processing of the load or store instruction, the instruction signal 1 1 5 and the flag signal from the arithmetic logic unit 10 8 1 1 6 is also transmitted to the sequencer 104 to control the program counter 102. Then, the output signal generated by the random number generator in the register file 107 (not the register signal specified by the instruction) is transmitted to MAR 1 10. The Chinese paper standard is applicable to the Chinese National Standard (CNS) A4 specification. (2i0 X 297 mm) -20-

47218B Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (19) Control M I S R output signals; and compare these signals with pre-calculated error-free M I s R output data. As shown in this embodiment, the random instruction generation function enables the test to be performed under a combination of instructions in different order of appearance. In addition, because the random number instruction generator is used to generate random number data corresponding to the executed instructions, the test performance can be improved. FIG. 6 shows an embodiment of a random number instruction generator, wherein the random number instruction generator includes: an instruction storage mechanism 7 1 ′ for storing test instructions; and an instruction selection mechanism 72 for randomly selecting the instructions stored in the instruction storage mechanism. Instructions. The entire operation is started by entering a test mode signal 1 3 3 to indicate a self-test. First, the reference information used to select the instructions stored in the instruction storage mechanism 71 is transmitted from the instruction selection mechanism 7 2 to the instruction storage mechanism 7 1 as the selection signal 7 3, and then this information is used as the instruction information signal 1. 3 4 to teleport. Next, after receiving the selection signal 73, the instruction storage mechanism 71 transmits a corresponding instruction to 140. The instruction storage mechanism 71 of this embodiment may be implemented by a memory for receiving the selection signal 73 and the address signal. Figure 7 shows an example of a memory. In this memory, the address is 32 bits, and the instructions generated during the self-test are in the 32 bit data format shown in FIG. 5. In the example of FIG. 8, 'n' is the number of instructions. For example, '3 2 digit code " 000000000000000100000 H00l100100 〃, ADD 0, R (1), R (1 9), R (4) " Instruction This paper standard applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -22- ------------.! Packing ---- * ---- Order · (Please read the precautions on the back before filling this page) 472189 A7 B7 V. Description of the invention (20)

Stored in the address '' 0 0 0 0 '', and indicated by the 32-bit code A 1000000000000000 1 0000 1 0000000 100 〃 (Please read the precautions on the back before filling this page) LOAD R (1) R (4) is stored in the address '' Π〃. The instruction selection mechanism 7 2 of this embodiment may use a linear feedback shift register (LSFR) generally used as a virtual random number generator. Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative prints LFSR to return the final state of its displacement register to the initial state of the displacement register D-flip-flop ', and at the same time uses the sum of mutually exclusive logic to provide feedback to D in the intermediate state -Flip-flop. Except for the case where all bits are w 〇〃, all bit patterns can be generated in a virtually random manner by this feedback structure. Figure 8 shows an example of 33-bit LFSR In this illustration, '9 1 is the D_ flip-flop' and 9 0 to 9 3 2 are the 33-bit virtual random number pattern output signal. In LFSR, you can perform D-forward and reverse A shift operation to get a virtual random number, and then D-The result signal data of the flip-flop is assigned to the 33-bit virtual random number pattern output signals 9 0 to 9 3 2. By repeatedly performing the above-mentioned shift operation, a plurality of virtual random number pattern output signals can be obtained. In addition, when all the bits in the initial LFSR data are " 0 〃, because 尙 does not generate a virtual random number, the flip-flop is initialized by the signal data combination; in the case where all the bits are other than 0〃 Down 'When the LS I is activated or when the test mode signal is changed to a self-test mode signal, the flip-flop will be used as a D-flip-flop. The embodiment of FIG. 6 can be implemented in the following ways: from the LFSR of FIG. 8 Select those that contain specific instructions to designate the memory. 23- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.

47218B A7 _ B7 V. Description of the invention (21) The output signal of the required bit, then connect the corresponding output signal line for the address signal line to the memory, and transmit those keystrokes at a 1: 1 ratio The address signal 'in the memory storage instruction is used as the instruction information signal 1 3 4 for identifying the random number instruction generator to send the instruction. In addition, the probability that the random number instruction generator will generate an instruction can be set by storing an instruction in multiple addresses of the memory in advance, and increasing the reason why the instruction selection mechanism repeatedly selects the instruction. FIG. 9 shows another embodiment of the random number instruction generator. The random number instruction generator includes: a half-instruction storage mechanism 1 0 2 'to store each or all of the instructions to be executed: a supplementary instruction information storage mechanism 1 0 3 to store the execution in the half-instruction storage mechanism Supplementary information required in the case of a half-instruction; the instruction selection mechanism 1 0 0 1 is used to randomly select the half-instruction and the corresponding supplementary instruction information from the half-instruction storage mechanism and the supplementary instruction information storage mechanism respectively; and an instruction generator for The random number data is supplemented according to the selected half instruction and the supplementary instruction information, so as to generate an instruction to be executed by the processor. The entire operation is started by entering a test mode signal 1 3 5 to indicate a self-test. First, the reference information used to select those half-commands stored in the command storage mechanism 1 0 0 2 is transmitted from the command selection mechanism 1 0 0 1 to the half-command storage mechanism 1 0 0 2 as a selection signal 1 0 0 5 . At the same time, the selection signal 105 is transmitted to the supplementary instruction information storage mechanism to select the supplementary instruction information corresponding to the selection information. Then the selection signal 1 0 0 5 is transmitted as the command information signal 1 3 4 to the half-command storage mechanism 1 0 2 to thereby correspond to the selection signal. ---------- Order · (Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -24-472189 A7 ___B7 V. Description of the invention (22) (Please read the precautions on the back before filling in this page) The half command 1 0 0 5 of 1 0 0 5 is transmitted to the command generator 1 0 4. In addition, the supplementary instruction information 1 0 7 corresponding to the selection signal 1 0 05 is also transmitted from the supplementary instruction information storage mechanism 1 0 3 to the instruction generating benefit 1 104. Finally, after receiving the half instruction 1006 and the supplementary instruction information 1007, the instruction generator 1104 generates executable instructions by assigning the supplementary random number data to the missing part of the half instruction, and Issue the instruction as an output instruction 1 4 0. The memory that receives the selection signal 105 as an address signal can be used to implement the semi-command storage mechanism 1 0 2 and the supplementary command information storage mechanism 1 0 3 in this embodiment. Figure 10 shows an example of the memory used to implement such a semi-command storage mechanism. In this memory, the address is 32 bits, and the instructions generated during the self-test are 32 bits + data format as shown in FIG. 5. At this time, in the entire instruction code to be stored, only those bits to be supplemented by random number data are set to `` 0 〃. In the example in FIG. 10, `` m '' instruction numbers are stored. For example, the "SUB" represented by a 32-bit code " 0000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000, and 10,000, and 〇 ,? ,? ,? The 〃 instruction is stored in the address 0001 ，, and it is stored in the address 0001 3 `` BRA? &Quot; is stored in the address '' with a 32-bit code `` printed by 001 00000000000000000000000000000 〃 0 0 4 〃, where the ''? 〃 in the instruction is a field that will be entered by random number data in each instruction code. For example, in the case of address, 0001〃, 'w? 〃 means that bits 17 to 31 of the instruction code will be entered by random number data' and the corresponding bits will be stored as " 0 〃. Figure 11 shows a paper used to implement the supplementary instruction information. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 25-472189 A7 B7 V. Description of the invention (23) Example of the memory of the storage mechanism ° The address is 32-bit 'and the supplementary instruction information is represented by 32-bit pattern. In addition, those semi-commands stored in the memory of Figure 10 and the supplementary command information corresponding to each semi-command are stored in a matching manner. The format of the supplementary instruction information is corresponding to those of the half instructions stored in the half instruction storage mechanism. 'The bit system in each half instruction that wants to enter random number data is set to 1', and the other bits are set to , '〇〃. In the example in FIG. 11 'for the address ο ο ο Γ, the bits 17 to 3 corresponding to the half instruction of FIG. 10 are set to 1, and 1 ，, and the other bits are set to Is '' 〇〃. Therefore, the '32 -bit code ', 100,000, 000, 000, 000, 000, 000, 11, 111, 111, 111, 111 111 are stored in the corresponding addresses. Similarly, 'for address 00-04', bits 8 to 21 used to indicate the branch destination of the branch instruction are set to "1" and bits 0 to 7 are set to "0" 〃. Therefore, the 32-bit code " ooooooooimimiiiimiiiiiiin 〃 is stored in the corresponding address. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 12 shows a detailed embodiment of the instruction generator 104. The instruction generator includes: LFSR 1 3 Ο 1, when a test mode signal 1 3 3 is input to indicate a self-test mode, it can be used as a 32-bit virtual random number pattern generator; a 32-bit sum gate Calculator 1 3 0 2, which receives two sets of 32-bit data, and then outputs the result after calculating the logical product of each bit; and 32-bit OR gate calculator 1 3 0 3, It receives two sets of 32-bit data, and then outputs the result after calculating the logical sum of each bit. During the calculation period, first calculate the supplementary instruction information storage institution -26------------...- post ---------- order (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472189 A7 B7____ V. Description of the invention (24) The given supplementary instruction information 1 0 0 7 And the logical product of each bit of the virtual random number data given by LFSR 1 3 0 1, and by assigning the random number data to only the bits that need to be supplemented, it is generated as an output 3 2-bit data. Then 'calculate the logical sum of the 32-bit data given by the half-instruction storage mechanism and each bit of the half-instruction 106, and assign random number data to only the bits that need to be supplemented to To generate 32-bit data for output, the LFSR shown in FIG. 8 can be used as the instruction selection mechanism 1 0 0 1. From the L F S R output, select an output signal equivalent to the number of bits required to specify the contents of both the half-command storage memory and the supplementary command information storage memory, and then connect the selected signal line to the address signal line. The memory that received the address signal treats the corresponding address data as a half command 1 0 6 and supplementary command information 1 0 7. If the address data is transmitted as the command information signal 1 3 4, the output command output by the random number command generator can be identified. In the structure of the above embodiment, in order to improve performance, the number of semi-instructions i stored in the memory is equal to an exponential multiple of 2 (as shown in the embodiment of FIG. 6). However, the output of the L F S R printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs can also be normalized to '' m 半 one and a half instruction numbers stored in memory in advance. In addition, the probability that the random number instruction generator generates an instruction can be set by the reason that "an instruction is stored in multiple addresses in memory in advance, and the instruction selection mechanism can repeatedly select the probability of the instruction". Compared to Figure 6, because the embodiment of Figure 9 can be assigned random number data -27- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472189

5. Description of the invention (25) It is expected to supplement each instruction to generate a plurality of instructions, so it is possible to test a large number of instruction combinations. FIG. 13 shows a detailed embodiment of the random number data generator of FIG. 1. Some random number data generators have: a 32-bit random number generator 1 4 0 1 to 1 4 0 3; a selector 1 4 0 4 to select a set of output data of the random number generator 'and use To send random number data 1 4 0 6; and the decoder 1 4 0 5, which can receive the instruction information signal 1 3 4 ′ and then determine whether the random number generator is to send random number data, and if it is to send data, it will send Those used to specify the output of the random number generator corresponding to the instruction information signal and those used to specify the operation to be performed by the random number generator are transmitted to the selector. The random number generator 1 4 0 1 to 1 4 0 3 transmits data in the data format required to execute the test option. During the processing period, first, when the instruction information signal 1 3 4 of the random number instruction generator 1 2 3 is input, the decoder 1 4 0 5 determines whether the random number data generator is to transmit random number data, and if it is to transmit If it is data, those random numbers that are used to specify the command information signal -----------. I -------- order_ (please read the precautions on the back before filling in this Page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative Printed Device 1 Data refers to the production of digital information ο order the data to be solved by machine 4 index-to-machine and 1 to machine-to-machine, machine-to-machine 4格 ο Production and delivery equipment, material application, 4 data transmission as actual capital, 1 opportunity to produce the equipment, and the number of equipment will be sent to the machine. The selected item will be sent to the operator for a certain number of trials during the calculation. It will be tested by the computer, and the follow-up will be followed by a message of 5. ο 4 Use the materials 4 3 Use the data 1 1 Some out of the machine 3 Do not enter the machine code ο The machine code letter, the device 4 will follow the information from the Zhongsheng Club 1 to the news ^ The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 28- 472189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (26) Information can be transmitted as a match Random number data corresponding to the instruction. A random number generator can be implemented by using a combination circuit to transmit the random number data matching the instruction information signal, wherein the combination circuit uses L F S R and its output as inputs. For example, if the part with fixed bit data is used as the data part to test the instruction '' a ，, it can be accomplished by adding an L F S R output masking circuit. The load instruction shown in the embodiment of Fig. 1 is a specific example. LOAD R (S 1), R (D) is a load instruction, in which the memory data addressed by the memory designated by S 1 will be transferred to the register designated by D. Under this instruction, when using the data output by the random number generator (not the register data specified by S 1), because the length of the address space is limited to 24 bits, the random number generator outputs data It must also be represented by a 24-bit pattern. Figure 18 shows a random number generator for transmitting: sending random number data matching the load instruction. The random number generator includes: LFSR1902, which transmits a 32-bit virtual random number; and a combinational logic circuit, 903, which performs an 8-bit product operation. During the processing, first, when the arithmetic instruction signal 1 0 0 1 is input from the decoder 1 450, L F S R will transmit a 32-bit virtual random number pattern. Next, the higher-order octet signal in the 32-bit virtual random number pattern will be transmitted to the combinational logic circuit 903, and then the product operation of those signals whose octets are " 0〃 , And mixed with those octets that are "quoted as 0" data 1 9 0 5. Finally, the lower-order paper sizes in the data 1 905 and 32-bit virtual random number patterns are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) .2Q. ------ ---- I equipment -------- Order- (Please read the precautions on the back before filling this page) 472189 A7 B7 V. Description of the invention (27) 2 4-bit information 1 9 0 4 The data will be used as the 32-bit data matching the input command. In addition, when the probability obtained by adjusting the probability of each bit, 〇 〃,, 丄 " is used as the data for the instruction b 用以 used to confirm the data format required to execute the test option The random number generator can be constructed by designing a combination circuit using the following factors: When the logical sum of multiple output bits of the LFSR is used as its output, it will increase the power of `` 1 〃 '' Probability of occurrence; and when the logical product is used as its output, it will increase the probability of '' 0 〃. In the case where the bit pattern set is used as the data to match the instruction `` c ，, when the pattern randomly selected from the pattern set is used as the data to match the instruction `` c ，, This can be achieved by using LFSR and memory storing bit patterns, and then using LSFR output to generate memory data output addresses. FIG. 17 shows another embodiment of the random number data generator used in FIG. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------- '' installation --------- '. (Please read the precautions on the back before filling this page) These random The number data generator includes: a decoder 1 8 0 5 'it can receive the instruction information signal 1 3 4 and then determine whether the random number generator is to transmit random number data, and if it is to transmit data', it will not only be used to specify random The signal of the digital data output operation is sent to LFSR 1 8 0 7 'It also sends information for selecting random number data that matches the instruction information 1 8 0 8; LFSR 1 8 0 7' It is used to output 32-bit virtual Random number data; directive adaptation agencies I801 to 1803 'In converting data into the directive applicable to the directive information signal 1 3 4 旳 This paper size applies the Chinese National Standard (CNS) A4 specification (210 297 Gongchu) -30 -472189 " -............. B7 V. Description of the invention (28) After random number food, it is used to transmit LF s R 3 2-bit data to selector 1804; selector 18〇4, in which the suitable information is selected from the output of the instruction adaptation mechanism according to the selection information 1 8 0 8 The instruction information resource of the random number data "is then transferred to the next stage. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I ------------ install ------- order. (Please read the precautions on the back before filling this page) During the processing period ' First, 'when a random number command generator 1 2 3 inputs a command information signal 1 3 4, the decoder 1 8 0 5 determines whether the random number data generator is to transmit random number data, and if it is to transmit data' then those The information used to specify that the instruction adaptation mechanism transmits random number data corresponding to the instruction information signal will be transmitted to the selector 1804, and the decoder will transmit the random number data output instruction signal 1804 to LFSR1807. Then, the received F S R 1 8 0 7 with the instruction will transmit the virtual random number data to the instruction adaptation mechanism 1 80 1 to 1 8 0 3. After receiving the virtual random number data from LFSR, the instruction adaptation mechanism will convert the purple data into random number data adapted to the instruction, and send the random number data to the selector 1 804. In this selector, the virtual random number data adapted to the instruction information signal 1 3 4 is selected from the output virtual random number data of the instruction adaptation mechanism according to the selection information 1 8 8 and transmitted to the next stage to Random number data adapted to the instruction defined by the instruction information signal 1 3 4. The load command shown in the embodiment of FIG. 1 is a specific example. LOAD R (S 1), R (D) is a load command, where the memory data addressed by the memory designated by S 1 will be Transfer it to the register specified by D. In this instruction, 'When using a random number generator to output the paper size Peng + Guan Xuzhan (CNS) A4 specifications (210 x 297 mm). 31-472189 Α7 Β7 5. Information of the invention description (29) (non- The register data specified by S 1) is used to randomly change the corresponding address and perform instruction execution test. Because the length of the address space is limited to 24 bits, the output data of the random number generator must also be 2 4-bit pattern. Figure 19 shows an instruction adaptation mechanism for converting the L F S R 1 8 0 7 output virtual random number data into a format that matches the load instruction. This instruction adaptation mechanism includes: a combinational logic circuit 2 0 01, which performs an 8-bit multiplication operation; and a penetrating circuit 2 0 0 2, which can transmit a 2 4-bit signal without any modification 0 Figure 1 4 shows a detailed embodiment of the register file in FIG. 1. This register file contains: 3 2 registers, which have two read ports and a write port, and are used to store data. The output selectors 1 500 and 15 0 1 will test signal Change to the random number data generator output signal (instead of the register output signal), and send the random number data generator output signal to the data bus; M ISR 1 5 0 5 to receive 3 2 bit data as The response analyzer is used; and the input selector 'where the register data input by the bus 1 2 0 is transmitted to the M ISR through the test mode signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Under normal operation mode, the register written by the bus 1 2 0 is written in the register specified by the instruction. In addition, the command selection register data is also transmitted to the buses 1 1 8 and 1 1 9. In the self-test mode, the data written by the register input by bus 1 2 0 is input to the selector and transmitted to M I S 1 505. In addition, the instruction selection register data is transformed into a random number data generator 1 5 0 3 and -32- ----------- 'equipment ----- order · (Please read the back first Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (21 × 297 mm). 472189 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention (30) 1 5 0 4 output, and then the data is then transmitted to the bus 1 1 8 and 1 1 9 ° Figure 15 shows an embodiment of this structure, in which the random number data output mechanism (instead of one of the serializer 104) Or more than one storage device) transmits the signal in the case of the embodiment of FIG. 1, wherein the test mode signal is designated as a self-test mode. The sequencer is a sequence circuit, which includes: a combination circuit block 16 0 1 and “i” storage devices 16 0 4 to 16 06. When the test mode signal 1 3 3 is designated as the self-test mode, the selectors 16 0 2 and 1 6 0 3 will send the output signals 1 607 and 1 of the random number data generator 1609 (instead of the storage devices 1605 and 1606). 608. The output data of the random number data generator can be obtained by assigning two bits from the output of the LFSR shown in FIG. 8. In this embodiment, although the two storage devices are selected by the selector, the signal output structure is not limited to this, but may further include one or more storage devices. Even if the random number instruction generator has generated non-branch instructions, the structure of this embodiment can also be tested using different program counter data. FIG. 16 shows the structure of the M I S R embodiment of FIG. 1. Generally, M I S R is used as a response analyzer in the B I S T functional block, and the response analyzer can use the sum of mutually exclusive logic to transmit the signal to each bit of L F S R. In FIG. 16, 17 is a D-flip-flop ′ and the data input signal lines of 17000 to 1732 2 are 33-bit patterns. The signal required for data acquisition is connected to the input signal line u by mutually exclusive logic between the output of the D-flip-flop and the data required during the displacement ------------- -.Packing ._—— Order. (Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (21〇X 297 mm) -33- 472189 A7 B7 V. Invention description (31) The sum of the series is sent to each D-flip-flop to complete the data acquisition. According to the present invention, by providing a function that can randomly generate test instructions, a combination of a large number of instruction generation sequences can be tested. In addition, since the instruction information generated by the random number instruction generator can be used to form random number data that matches the executed instructions, its test performance can be improved and a high error detection rate can be provided. In addition, you can also use hardware such as a random number instruction generator and a random number data output mechanism to achieve fast test operations. According to the present invention, a high error detection rate and fast testing can be achieved .------------ ii ------- Order · (Please read the precautions on the back before filling this page ) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to Chinese National Standard (CNS) A4 (210 X 297 mm) _ 34-

Claims (1)

472189 δ9 1 〇6 1 ia ‘-vs BH CH [.) 8 Please fill in the form ii. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. Application scope of patents 1. An embedded device 'contains: a program counter' to specify the instruction to be executed; an instruction register 'to store programs Instructions specified by the counter; registers to store data; arithmetic logic unit 'to download instructions from the instruction register, and then read data from the data storage register according to the downloaded instructions, and _ Perform arithmetic operations and store arithmetic result data in a data storage register; and a random number command generator 'for randomly generating test instructions based on externally input test signals. 2 · _ If the processor is in the scope of claim 1, wherein the random number instruction generator randomly generates a test instruction according to the test signal, and stores the test instruction in the instruction register. 3. The processor according to item 1 of the patent application scope, wherein the random number instruction generator randomly generates a test instruction according to a special test instruction, and generates an output signal for transmitting appropriate data of the data storage register 0 4 _ If the processor is any one of claims 1 to 3, wherein the random number instruction generator processes a plurality of instructions and transmits the instructions according to a preset condition. 5 · A processor including: a program counter to specify the instructions to be executed; a register file 'which has a plurality of registers capable of storing data; arithmetic logic: a unit for specifying according to the program counter -------------- i clothing ... (Please read the precautions on the back of 3t before filling out this page) ) Al specification (2ΐϋ x 297 male cage) -35-472189 A8 B8 C8 D8 夂, patent application scope Download data from the temporary register file, then perform arithmetic operations, and store the arithmetic result data in the data register; A random number instruction generator for randomly generating test instructions according to an externally input test signal; a random number data output mechanism for transmitting a random number to an arithmetic logic unit to perform an arithmetic operation; and a response analyzer for performing The random number data to be stored to store the arithmetic result. 6. The processor according to item 5 of the patent application scope, wherein the response analyzer captures the output signal from the program counter according to the test signal. 7. The processor according to any one of claims 1, 2, 3, 5, and 6, wherein the random number instruction generator has a mechanism for storing instructions executed by the processor, and a mechanism for obtaining instructions from the instructions. A mechanism that randomly selects instructions from a storage mechanism. 8. The processor according to any one of claims 1, 2, 3, 5, and 6, in which the random number instruction generator further includes: a semi-instruction storage mechanism for storing some or all of the instructions to be executed The instruction t supplementary instruction information storage mechanism is used to store supplementary information required when executing the half instruction in the half instruction storage mechanism; the instruction selection mechanism is used to randomly select the half instruction from the half instruction storage mechanism and the supplementary instruction information storage mechanism, respectively. And the corresponding supplementary instruction information; and used to supplement the applicable Chinese National Standard (CNS) A4 specification (210 X 297 mm) with this paper size according to the selected half instruction and supplementary instruction information (please read the note on the back first Please fill in this page for matters) 4 ---- Order --------- Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-36- 472189 .- \ 8 C \ S ns _____ VI. Application Patent scope machine data organization to generate instructions that the processor wants to execute 9. An information processing system having program or data storage memory and a processor connected to the memory To facilitate the reading and storage of data ', the processor additionally includes: an instruction register for outputting the instruction to be executed; a plurality of registers for storing data; an address register for storing and storing Address needed to record the billion body; data register to store the data to be stored in or read from the memory; the arithmetic logic unit, which can register according to the instruction The output command is used to calculate data that has been stored in multiple registers or data registers ------------- install -------- order. Read the phonetic on the back] Matters again-write this page) The middle device is rooted with a temporary order, a survival order, a storage order, a dagger, and a foreign order. The production machine comes with a number. Letter and evidence The middle root device stores the temporary collection of materials to receive funds, and the storage device stores the analysis of the internal rules of the executive order, which should be followed by a single finger. Set the production materials and order the index -line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A-I specification (210 x 297 mm) -37-