TW472189B - Processor with best function - Google Patents

Processor with best function Download PDF

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Publication number
TW472189B
TW472189B TW089106118A TW89106118A TW472189B TW 472189 B TW472189 B TW 472189B TW 089106118 A TW089106118 A TW 089106118A TW 89106118 A TW89106118 A TW 89106118A TW 472189 B TW472189 B TW 472189B
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Taiwan
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instruction
data
random number
register
instructions
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TW089106118A
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Chinese (zh)
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Kazufumi Hikone
Norinobu Nakao
Kazumi Hatakeyama
Takashi Hotta
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Hitachi Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/27Built-in tests
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31701Arrangements for setting the Unit Under Test [UUT] in a test mode
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/31813Test pattern generators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Self-testing can be implemented by providing random-number instruction generator 123, which generates testing instructions randomly, and random-number data generators, which generates and sends random-number data based on instruction information signals 134 created by the random-number instruction generator.

Description

472189 A7 B7 五、發明說明(1 ) 發明背景 (請先閱讀背面之注意事項再填寫本頁) 本發明關於一種內建自我測試(B I S T )技術,能 夠針對含有自我測試功能的邏輯電路進行快速的測試以及 高準確性的錯誤偵測。 一般用來偵測邏輯電路之錯誤的測試方法係藉由從外 部輸入預設的測試資料於電路中,然後觀察所形成的輸出 響應。然而,對於尺寸日益增大的邏輯電路而言,所輸入 之測試資料的容量也隨之增加,這會延長測試時間並增加 所需的測試成本。因此,亟需採用B I S T技術來降低測 試成本,藉此利用內建的自我測試電路來進行邏輯電路的 自我測試。 習知的B I S T技術係揭露於1 9 9 3年三月所發行 之"A Tutorial on Built-In Self-Test"— 書的第 7 3 — 8 2 頁 中,以及1 9 9 3年六月所發行之"IEEE DESIGN & TEST 〇F COMPUTER"雜誌的第69 — 77頁中。 經濟部智慧財產局員工消費合作社印製 B I S T (如圖2所示)係由測試控制區段、圖形產 生區段以及響應分析器所組成。從圖形產生器所輸出的輸 出信號被送至電路中以進行測試,然後其結果響應號則輸 入至響應分析器中,並且監視其狀態以便偵測錯誤。圖形 是由兩種主要方法之一來產生。一種方法是藉由將預設的 測試資料以及測試程式儲存於ROM等等,並且將資料與 程式傳送至欲被測試的電路中。對於這種方法而言’因爲 測試資料必須儲存於記憶體中,所以該欲儲存於邏輯電路 中之资料的容量有所受限。因此,雖然可偵測出該測試资 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -4- 472189 A7 __ B7 五、發明說明(2 ) (請先閲讀背面之注意事項再填寫本頁) 料範圍內的錯誤,但卻偵測不到其他的錯誤。另一種方法 是利用虛擬隨機數產生器(p s e u d 〇 - r a n d 〇 m n u m b βι-δ e n e r a t 〇 r ) 。 虛 擬隨機 數產生 器的使 用可產 生大量 的虛擬 經濟部智慧財產局員工消費合作社印製 隨機數,並傳送至欲測試的電路中。但,如果要測試按順 序排列之序列電路的§舌,則因爲不易產生所有的狀態改變 ,甚至如果要測試一個組合電路的話,則因爲可能產生不 可偵測的狀態,所以這種使用虛擬隨機數的方法不易達到 高的錯誤偵測率。在此情況下,雖然可增設一個電路用以 將虛擬隨機數直接指派給內部儲存裝置,以便將序列電路 作爲組合電路來處理,但所增加的電路會造成快速電路運 算的困難及/或增加電路的區域範圍。一種結合上述兩種 圖形產生方法的範例係揭露於日本上開專利N 〇 . 5 -120052 (1993)。在這種利用微處理器之指令 執行功能(i n s t r u c 11 ο n e X e c u t i ◦ n f u n c 11 ο η )來進行測試的 方法中,測試程式是儲存於記憶體中,且程式所使用的資 料是利用虛擬隨機數產生器來產生。在此電路結構中,測 試模式規格信號(t e s t m 〇 d e s p e c i f i c a t i ◦ n s i g n a 1 )的輸入 係設定爲自我测試模式,而且當執行預先儲存於程式記憶 體中的測試指令時,則便自動產生欲輸入於測試目標(亦 即,算術邏輯單元A L U )的測試資料,而且根據電路中 之狀態旗標(status flag )的特定狀態來將虛擬隨機數標 準化。因此,大量的測試資料便可供測試指令所使用。然 而,因爲測試指令係儲存於記憶體中,所以即使是使用這 種方法,其欲測試之指令組合的數目也有所受限制’而且 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -5- 472189 A7 B7 五、發明說明(3 ) 這也會使得某些運算順序不同於指令出現順序之邏樹電路 元件發生許多無法執行的測試。 (請先閱讀背面之注意事項再填寫本頁) 如上述習知範例所示,使用習知的自我測試方法會造 成儲存於記憶體之中的測試資料無法進行足夠的測試’且 上述僅採用虛擬隨機數產生器的方法會造成電路增加的負 擔,亦即會減緩運算的速度並增加電路的區域。即使結合 上述的兩種方法(亦即,使用處理器之指令執行功能的測 試方法)’也會造成指令組合數目受限的問題。爲了利用 B I S T來達到快速測試以及高的錯誤偵測率’則必須解 決上述的問題。本發明的目的是要提供一種機構’能夠快 速測試運算’並且測試大量的指令組合。 爲確實達成上述的目的’本發明中之處理器的特徵在 於具有隨機產生測試指令的功能,藉此進行快速的運算測 試並且能夠測試大量的指令組合° 經濟部智慧財產局員工消費合作社印製 尤其是,一種處理器的特徵在於藉由提供具有下列構 件的處理器來達成快速的運算測試以及測試大量的指令組 合:程式計數器’用以指定處理器所執行的指令;指令暫 存器,用以儲存程式計數器所指定的指令;暫存器’用以 儲存資料;算術邏輯單元’用以從指令暫存器中下載指令 ,然後根據下載的指令來從資料儲存暫存器中讀取出資料 ,並且執行算術運算以及將算術結果資料儲存於資料儲存 暫存器中;以及隨機數指令產生器’用以根據外部輸入的 測試信號來隨機產生測試指令。 一種處理器的特徵在於也藉由提供具有下列構件的處 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) .6 - 472189 A7 五、發明說明(4 理器來達成快速的運算測試以及測試 式計數器,用以指定欲執行的指令; 複數個能夠儲存資料的暫存器;算術 程式計數器所指定的指令而從暫存器 後執行算術運算,並且將算術結果資 中;隨機數指令產生器,用以根據外 隨機產生測試指令;隨機數資料輸出 傳送至算術邏輯單元以執行算術運算 用以根據隨機數資料來儲存算術結果, 爲了滿足上述的目的,可採用一 大量的指令組合:程 暫存器檔案,其具有 邏輯單元’用以根據 檔案中下載資料,然 料儲存於資料暫存器 部輸入的測試信號來 機構’用以將隨機數 ’以及響應分析器, 經濟部智慧財產局員工消費合作社印製 存記憶體以及連接至該 儲存,在此情況下,處 試大量的指令組合,其 用以存取記憶體所需的 儲存於記憶體中或欲從 單元,藉此可根據指令 被儲存於多重暫存器或 ,用以根據外部信號來 指令暫存器中;以及設 以接收那些根據指令產 於資料暫存器中的資料 爲了滿足上述的目 存記憶體以及連接至該 儲存,在此情況下’處 記憶體 理器可 另外包 位址; 記憶體 暫存器 資料暫 隨機產 於算術 生器之 的處理 實現快 含:位 資料暫 中所讀 所輸出 存器中 生指令 邏輯單 輸出指 種具有 器以利 速的運 址暫存 存器, 出的資 的指令 的資料 ,並且 元內的 令所執 程式或 資料的 算測試 器,能 用以儲 料;算 來運算 ;指令 將指令 響應分 行後而 資料儲 讀取與 並且測 夠儲存 存欲被 術邏輯 那些已 產生器 儲存於 析器, 被儲存 的,可採用一種具有程式或資料儲 器以利資料的讀取與 記憶體的處理 理器可實現快 本紙張尺度適用中國國家標準(CNS〉A4規格(210 χ 297公釐) ---------.—.裝---------訂. (請先閱讀背面之注咅?事項再填寫本頁) 472189 A7 B7 五、發明說明(5 ) (請先閱讀背面之注意事項再填寫本頁) 試大量的指令組合,其另外包含:指令暫存器’用以輸出 欲執行的指令;複數個暫存器’用以儲存資料;位址暫存 器,能夠儲存用以存取記憶體所需的位址;資料暫存器, 用以儲存欲被儲存於記憶體中或欲被從記憶體中所讀出的 資料;算術邏輯單元,藉此可根據指令暫存器所輸出的指 令來運算那些已被儲存於多重暫存器或資料暫存器中的資 料;指令產生器,用以根據外部信號來隨機產生指令,並 且將指令儲存於指令暫存器中;以及設於算術邏輯單元內 的響應分析器,以接收那些根據指令產生器之輸出指令所 執行後而被儲存於資料暫存器中的資料。 另外,隨機數指令產生器可藉由將不同的資料儲存於 指令暫存器中,或者是藉由隨機產生不同的測試指令並產 生那些暫存器送出指令相關資料所需的輸出信號’或者是 根據預設的機率資料(P r e s e t ρ 1: 〇 b a b 1111 y d a t a )來選擇指 令並傳送這些指令,或者是結合上述方法’以便測試大量 的指令組合。 另外,上述處理器中的隨機數指令產生器可藉由下列 程序以進行大量指令組合的測試: 經濟部智慧財產局員工消費合作社印製 半指令(P a r t i a 1 - i n s t r u c 11 ο η )儲存機構’用以儲存部 份或全部欲執行的指令; 補充指令(instruction-complementary )資訊儲存機構 ,用以儲存執行半指令儲存機構內之半指令時所需的補充 資訊; 指令選擇機構,用以分別從半指令儲存機構以及補充 尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ~ " 472189 A7 B7 五、發明說明(6 ) 指令資訊儲存機構中隨機選擇半指令以及對應的補充指令 資訊;以及 用以根據所選出之半指令以及補充指令資訊來補足隨 機數資料的機構,以產生處理器所欲執行的指令。 另外,當所需的測試模式信號指定爲自我測試時’可 藉由傳送來自隨機數資料輸出機構所輸出的資料(而非藉 由傳送暫存器檔案內之暫存器中的資料)來進行大量的指 令組合測試,其中該暫存器檔案內的暫存器是受相對應的 指令所指定而來傳送這些資料的:並且可接收來自響應分 析器的資料(而非接收暫存器檔案內之暫存器的資料)’ 其中該暫存器檔案內的暫存器是受相對應的指令所指定而 來儲存這些資料的。 另外,當所需的測試模式信號指定爲自我測試時’這 些處理器的響應分析器可藉由接收來自個別程式計數$ @ 輸出信號 '來自處理器的記億體存取位址以及來自個別資 料暫存器的輸出以進行快速的運算測試。 圖式簡單說明 經濟部智慧財產局員工消#合作社印製 圖1係顯示本發明之實施例的處理器方塊圖。 圖2顯示使用習知B I S T技術的結構。 圖3表列出圖1之處理器的指令。 圖4顯示圖1之處理器的指令格式。 圖5係一詳細說明圖,顯示圖1之處理器的指令格式 -9 - -------------裝---------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 472189 Α7 ---Β7 五、發明說明(7 ) 圖6係一方塊圖,顯示圖1之隨機數指令產生器的實 施例。 (請先閱讀背面之注意事項再填寫本頁) 圖7顯示圖6中用以實施指令儲存機構的記憶體內容 〇 圖8係一線性回饋位移暫存器(L S F R )的方塊圖 ’該L S F R係用以產生虛擬隨機數。 圖9係一方塊圖,顯示圖1中之隨機數指令產生器的 另一個貫施例。 圖1 0顯示圖9之半指令儲存機構的記憶體內容。 圖1 1顯示圖9之補充指令資訊儲存機構的記億體內 容。 圖1 2係一方塊圖,顯示圖9之指令產生器的詳細實 施例。 圖1 3係一方塊圖,顯示圖1之隨機數資料產生器的 實施例。 圖1 4係一方塊圖,顯示圖1之暫存器檔案的實施例 〇 圖1 5係一方塊圖,顯示本發明之序列器的實施例。 經濟部智慧財產局員工消費合作社印製 圖1 6係一多工輸入標記暫存器(Μ I S R )的方塊 圖。 圖1 7係一方塊圖,顯示圖1之隨機數指令產生器的 另一個實施例。 圖18係一顯示圖13之隨機數指令產生器之另一個 特定實施例的圖式。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) _ _ 472189 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(8 ) 圖1 9係一顯示圖 施例的圖式。 之指令適應機構之另一特定實 主要元件對照表 17 7 1 7 2 7 3 0 4 0 7 10 7 D -正反器 指令儲存機構 指令選擇機構 選擇信號 D -正反器 言己憶體界面 程式計數器 指令快取記憶體 序列器 指令暫存器 解碼器 暫存器檔案 算術邏輯單元 記憶體資料暫存器 記憶體位址暫存器 匯流排 匯流排 指令信號 旗標信號 位址信號 (請先閱讀背面之注意事項再填寫本頁) i « —I vt ^^1 UK n n 一°'、> n n m I - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -11 - 472189 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(9 0 7 0 4 3 7 3 8 3 9 4 0 4 1 4 2 匯流排 匯流排 匯流排 資料信號 資料信號 隨機數指令產生器 隨機數資料產生器 多工輸入標記暫存器 多工輸入標記暫存器 多工輸入標記暫存器 選擇器 選擇器 選擇器 選擇器 測試模式信號 指令資訊信號 測試模式信號 輸出信號 輸出信號 輸出信號 輸出信號 輸出指令 選擇器 隨機數資料產生器 (請先閱讀背面之注意事項再填寫本頁)472189 A7 B7 V. Description of the invention (1) Background of the invention (please read the notes on the back before filling this page) The present invention relates to a built-in self-test (BIST) technology, which can quickly perform logic circuits with self-test functions. Testing and highly accurate error detection. The test method generally used to detect errors in logic circuits is to input preset test data into the circuit from the outside and then observe the resulting output response. However, for logic circuits of ever-increasing size, the capacity of the input test data also increases, which will lengthen the test time and increase the required test cost. Therefore, it is urgent to use B I S T technology to reduce the test cost, so as to use the built-in self-test circuit to self-test the logic circuit. The conventional BIST technology department disclosed "A Tutorial on Built-In Self-Test", published in March 1993, on pages 7 3-82, and June 1993 Issued in "IEEE DESIGN & TEST 〇F COMPUTER" magazine, pages 69-77. The printed B I S T (shown in Figure 2) by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is composed of a test control section, a pattern generation section, and a response analyzer. The output signal from the graphics generator is sent to the circuit for testing, and the resulting response number is input to the response analyzer, and its status is monitored to detect errors. Graphics are produced by one of two main methods. One method is to store the preset test data and test program in ROM, etc., and transfer the data and program to the circuit to be tested. For this method, because the test data must be stored in memory, the capacity of the data to be stored in the logic circuit is limited. Therefore, although it can be detected that the test capital paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -4- 472189 A7 __ B7 V. Description of the invention (2) (Please read the precautions on the back first Fill out this page again), but no other errors were detected. Another method is to use a virtual random number generator (p s e u d 〇-r a n d 0 m n u m b βι-δ e n e r a t 〇 r). The use of the virtual random number generator can generate a large number of virtual random numbers printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and transmitted to the circuit to be tested. However, if you want to test the § tongue of a sequence circuit in order, it is not easy to cause all state changes, and even if you are testing a combination circuit, because it may produce an undetectable state, this kind of virtual random number It is difficult to achieve a high false detection rate with this method. In this case, although a circuit can be added to directly assign the virtual random number to the internal storage device so as to process the sequence circuit as a combination circuit, the added circuit will cause difficulties in fast circuit operations and / or increase the circuit Area range. An example of combining the above two patterns is disclosed in Japanese Patent Application Laid-Open No. 5-120052 (1993). In this method of using the microprocessor's instruction execution function (instruc 11 ο ne X ecuti ◦ nfunc 11 ο η) to perform the test, the test program is stored in memory, and the data used by the program uses virtual random Number generator to generate. In this circuit structure, the input of the test mode specification signal (testm odespecificati ◦ nsigna 1) is set to the self-test mode, and when the test command stored in the program memory is executed in advance, the desired input is automatically generated. The test data of the test target (ie, the arithmetic logic unit ALU), and the virtual random number is standardized according to a specific state of a status flag in the circuit. Therefore, a large amount of test data is available for the test instructions. However, because the test instructions are stored in the memory, even with this method, the number of combinations of instructions to be tested is limited 'and this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) -5- 472189 A7 B7 V. Description of the invention (3) This will also cause some logic tree circuit elements whose operation order is different from the order in which the instructions appear to have many untestable tests. (Please read the precautions on the back before filling this page) As shown in the above-mentioned conventional example, the use of conventional self-test methods will cause insufficient testing of the test data stored in the memory 'and the above only uses virtual The random number generator method will increase the burden on the circuit, that is, it will slow down the operation speed and increase the area of the circuit. Even combining the two methods described above (i.e., a test method using a processor's instruction execution function) 'may cause a problem that the number of instruction combinations is limited. In order to use B I S T to achieve fast test and high error detection rate ', the above problems must be solved. The object of the present invention is to provide a mechanism 'which can quickly test operations' and test a large number of instruction combinations. In order to achieve the above-mentioned objective, the processor of the present invention is characterized by having a function of randomly generating test instructions, thereby performing fast arithmetic testing and being able to test a large number of instruction combinations. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Yes, a processor is characterized by providing a processor with the following components to achieve fast computational tests and test a large number of instruction combinations: a program counter 'is used to specify the instructions executed by the processor; an instruction register is used to Store the instructions specified by the program counter; the register 'is used to store data; the arithmetic logic unit' is used to download the instructions from the instruction register, and then read the data from the data storage register according to the downloaded instructions, And perform arithmetic operations and store the arithmetic result data in a data storage register; and a random number instruction generator 'for randomly generating test instructions based on externally input test signals. A processor is characterized by also providing a paper size with the following components to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 6-472189 A7 V. Description of the invention (4 processors to achieve fast Operation tests and test-type counters to specify the instructions to be executed; a plurality of registers capable of storing data; instructions specified by the arithmetic program counter perform arithmetic operations from the registers, and the arithmetic results are stored in the funds; A random number instruction generator is used to randomly generate test instructions based on external data; the random number data output is transmitted to an arithmetic logic unit to perform arithmetic operations to store arithmetic results based on the random number data. In order to meet the above purpose, a large number of Instruction combination: a process register file, which has a logic unit 'for downloading data from the file, and it is expected to store the test signal input by the data register unit to' use random numbers' and a response analyzer, economically The Intellectual Property Bureau employee consumer cooperative prints memory and connects to the store, in this case , Try a large number of command combinations, which are used to access the memory and stored in the memory or the slave unit, so that they can be stored in multiple registers according to the instructions or used to instruct the temporary according to external signals. And is configured to receive data produced in the data register according to instructions in order to satisfy the above-mentioned destination memory and to connect to the storage, in which case the memory processor may additionally include an address; The memory register data is temporarily generated randomly in the arithmetic generator. The processing implementation is fast. It contains: the bit data is temporarily read and the output register is in the middle of the instruction logic. The single output refers to a temporary address register with a device to facilitate the speed. The data of the issued instruction, and the calculation tester of the order or data in the order can be used to store materials; calculate to calculate; after the instruction responds to the branch, the data is read and the data is stored. The logic of the memory of desire is stored in the parser. If it is stored, a program or data storage can be used to facilitate data reading and memory processing. Can realize fast paper size applicable to Chinese national standard (CNS> A4 specification (210 χ 297 mm) ---------.—. Installed --------- order. (Please read first Note on the back? Matters should be filled out on this page again) 472189 A7 B7 V. Description of the invention (5) (Please read the notes on the back before filling out this page) Try a large number of instruction combinations, which additionally include: instruction register To output the instruction to be executed; a plurality of registers are used to store data; an address register is capable of storing the address required to access the memory; a data register is used to store the data to be stored in Data in memory or data to be read from memory; arithmetic logic unit, which can calculate those that have been stored in multiple registers or data registers according to the instructions output by the instruction register. Data; an instruction generator for randomly generating instructions based on an external signal and storing the instructions in an instruction register; and a response analyzer provided in the arithmetic logic unit to receive those instructions based on the output instructions of the instruction generator Data stored in the data register after execution material. In addition, the random number instruction generator can store different data in the instruction register, or generate randomly different test instructions and generate the output signals required by those registers to send the instruction-related data 'or Select the instructions according to the preset probability data (P reset ρ 1: 〇bab 1111 ydata) and send them, or combine the above methods to test a large number of instruction combinations. In addition, the random number instruction generator in the above processor can test a large number of instruction combinations by the following procedures: Semi-instruction (P artia 1-instruc 11 ο η) storage mechanism printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs' It is used to store some or all of the instructions to be executed. Instruction-complementary information storage mechanism is used to store the supplementary information needed to execute the half-instructions in the half-instruction storage mechanism. The semi-instruction storage mechanism and supplementary standards are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ 472189 A7 B7 V. Description of the invention (6) The semi-instruction and corresponding supplementary instructions are randomly selected in the instruction information storage mechanism Information; and a mechanism for supplementing the random number data according to the selected half instruction and supplementary instruction information to generate an instruction that the processor wants to execute. In addition, when the required test mode signal is designated as a self-test, it can be performed by transmitting data output from the random number data output mechanism (instead of transmitting data in the register in the register file). A large number of command combination tests, in which the register in the register file is specified by the corresponding command to transmit the data: and can receive data from the response analyzer (instead of receiving the register file) The data in the register) 'Wherein the register in the register file is designated by the corresponding instruction to store these data. In addition, when the required test mode signal is specified as a self-test, 'the response analyzer of these processors can receive counts from individual programs by $ @ output signal' from the processor's memory access address and from individual data Register output for fast arithmetic testing. The drawing is a simple illustration. Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by a cooperative. Figure 1 is a block diagram showing a processor according to an embodiment of the present invention. Figure 2 shows the structure using the conventional BI ST technology. FIG. 3 is a table listing the instructions of the processor of FIG. FIG. 4 shows the instruction format of the processor of FIG. 1. Figure 5 is a detailed explanatory diagram showing the instruction format of the processor of Figure 1-9-------------- install --------- order · (Please read the back first Please pay attention to this page and fill in this page again) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 472189 Α7 --- B7 V. Description of the invention (7) Figure 6 is a block diagram showing Figure 1 An embodiment of a random number instruction generator. (Please read the precautions on the back before filling out this page) Figure 7 shows the memory content of the instruction storage mechanism in Figure 6 Figure 8 is a block diagram of a linear feedback displacement register (LSFR) 'The LSFR system Used to generate virtual random numbers. FIG. 9 is a block diagram showing another embodiment of the random number instruction generator in FIG. 1. FIG. FIG. 10 shows the memory contents of the half-command storage mechanism of FIG. 9. FIG. 11 shows the contents of the memory of the supplementary instruction information storage mechanism of FIG. 9. Fig. 12 is a block diagram showing a detailed embodiment of the instruction generator of Fig. 9. FIG. 13 is a block diagram showing an embodiment of the random number data generator of FIG. 1. FIG. Fig. 14 is a block diagram showing an embodiment of the register file of Fig. 1 Fig. 15 is a block diagram showing an embodiment of the sequencer of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 16 is a block diagram of a multiplexed input mark register (M I S R). FIG. 17 is a block diagram showing another embodiment of the random number instruction generator of FIG. 1. FIG. FIG. 18 is a diagram showing another specific embodiment of the random number instruction generator of FIG. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) _ 472 189 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) Scheme. Of the command adaptation mechanism of another specific real component 17 7 1 7 2 7 3 0 4 0 7 10 7 D-Positive and negative device instruction storage mechanism instruction selection mechanism selection signal D-Positive and negative device memory interface program Counter instruction cache memory sequencer instruction register decoder register file arithmetic logic unit memory data register memory address register bus bus bus command signal flag signal address signal (please read the back first Please pay attention to this page and fill in this page again) i «—I vt ^^ 1 UK nn -1 ° ', > nnm I-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -11-472189 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (9 0 7 0 4 3 7 3 8 3 9 4 0 4 1 4 2 Bus Bus Bus Bus Data Signal Data Signal Random Number Command Generator Random Data generator multiplexer input marker register multiplexer input marker register multiplexer input marker register selector selector selector selector test mode signal instruction information signal test mode signal output No output signal of the output signal output instruction random number selector data generator (Please read the notes and then fill in the back of this page)

B I n n 口 π I n n I ^^1 n In I 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -12 - 2 7 4 8 ) Λ7 B7 五、發明說明(10 14 3 14 4 9 0 0 - 9 3 2 10 0 1 10 0 2 10 0 3 10 0 4 0 0 7 經濟部智慧財產局員工消費合作社印製 4 0 1 4 0 2 4 0 3 4 0 4 4 0 5 4 0 6 5 0 0 4 隨機數資料產生器 多工輸入標記暫存器 虛擬隨機數圖樣輸出信號 指令選擇機構 半指令儲存機構 補充指令資訊儲存機構 指令產生器 選擇信號 半指令 補充指令資訊 線性回饋位移暫存器 及閘計算器 或閘計算器 隨機數產生器 隨機數產生器 隨機數產生器 選擇器 解碼器 隨機數資料 輸出選擇器 輸出選擇器 隨機數資料產生器 隨機數資料產生器 多工輸入標記暫存器 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -13 - 3 2 7 4 A7 B7 五、發明說明( 11 4 0 0 7 0 8 7 0 8 0 8 0 8 0 17 4 8 0 7 8 0 8 8 0 9 經濟部智慧財產局員工消費合作社印製 19 0 3 19 0 5 2 0 0 1 2 0 0 2 選擇器 選擇器 儲存裝置 儲存裝置 儲存裝置 輸出信號 輸出信號 隨機數資料產生器 資料輸入信號線 指令適應機構 指令適應機構 指令適應機構 選擇器 解碼器 線性回饋位移暫存器 輸出資訊 隨機數資料輸出指令信號 運算指令信號 線性回饋位移暫存器 組合邏輯電路 資料 組合邏輯電路 每、、未爭攸 (請先閱讀背面之注意事項再填寫本頁) 裝----- 訂---- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 472189 Λ7 B7 五、發明說明(12) 較佳實施例之說明 本發明之實施例將詳述於下。 圖1顯示一種含有處理器的L S I結構’其爲本發明 的一個實施例。 在此圖式中,1 〇 1係一記憶體界面’可透過匯?;[lj排 1 1 1而與記億體交換信號;1 〇 2爲程式計數器; 1 0 3爲指令快取記憶體;1 0 4爲用以控制程式計數器 的序列器:1 0 5爲指令暫存器;1 0 6爲解碼器’用以 將指令暫存器的內容進行解碼,並且用以控制算術邏輯單 元等等元件;1 〇 7爲暫存器檔案,其含有隨機資料輸出 的隨機數資料產生器以及多工輸入標記暫存器(Μ I R S )以作爲響應分析器;1 〇 8爲算術邏輯單元(A L U ) ;1 0 9爲記憶體資料暫存器(M D R ),用以與記憶體 交換資料;1 1 0爲記憶體位址暫存器(M A R ),用以 將位址指定給記憶體界面;1 2 3爲隨機數指令產生器, 用以隨機輸出自我測試所需的指令;1 2 5 ,1 4 2及 1 4 3爲隨機數資料產生器,用以輸出隨機數資料; 經濟部智慧財產局員工消費合作社印製 ------------β---------訂. (請先閱讀背面之注意事項再填寫本頁) 1 2 6,''1 2 7,1 2 8及1 4 4爲響應分析器的 ^13尺;129,130,131’132及141爲 選擇器,用已在正常模式與測試模式期間交換信號流;另 外,1 3 3爲L S I外部所輸入的測試模式信號,以指定 自我測試模式;1 3 4爲指令資訊侣號’用以表示隨機數 指令產生器1 2 3之輸出指令1 4 0的內容。 除了接收指令資訊信號1 3 4之外本實施例的隨機數 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐).15 - 472189 Λ7 B7 五、發明說明(13) 資料產生器也可改變隨機數資料產生方法,以使得產生器 的隨機數資料輸出可更符合於隨機數指令產生器1 2 3所 傳送過來的指令。分別來自1 4 4,1 2 6 ,1 2 7及 Μ I S R 1 2 8的輸出信號1 3 6,1 3 7,1 3 8及 1 3 9係被傳送至處理器外部。 本實施例中的處理器指令係表列於圖3中。所有的基 本指令皆爲內部暫存器算術運算指令。本實施例提供四種 類型的分支指令(branch instruction ):非條件分支指令 B R A,條件分支指令B R A c c ( & c c 〃表示分支條 件)' 分支—副常式(branch-into-subroutine)指令 C A L L,以及副常式回傳(return-from-subroutine )指令 R T N。 另外,也設有載入指令LOAD以及儲存指令 S T 0 R E。此外,分支指令(載入指令及儲存指令)中 可指定的位址空間皆以2 4位元的圖樣來表示。 圖4顯示其指令格式。所有指令皆具有3 2位元的固 定長度。基本指令格式中的'' f 〃位元用以表示運算結果 是否要被倂入於旗標(flag )當中。而'' S 1 〃 , 、、s 2 經濟部智慧財產局員工消費合作社印製 ----------1 -碧--------旬- (請先閱讀背面之注意事項再填寫本頁) 〃以及w D 〃欄位則分別表示第一來源欄位、第二來源欄 位以及目的地的位址。另外,分支指令格式中的d 〃表 示分支目的地的位址。 圖5顯示出圖4中用以表示運算碼(〇 P c 〇 d e )之定 義的詳細指令格式。基本指令中之位元〇至位元7的値皆 設爲* 〇 〃 ,且分支指令中之位元4至位元7的値也設爲 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐).-j6 . 472189 A7 _ B7 五、發明說明(14) * 0 〃 ’而位元8至3 1則塡入分支目的地的位址。載入 (請先閱讀背面之注意事項再填寫本頁) 指令與儲存指令中的位元1 6係設爲、' 1 〃 ,且位元〇的 値係用以識別L 0 A D或S T 〇 R E。 接著將詳述本實施例之處理器在正常模式期間的處理 流程。在正常模式的基本指令處理期間中,首先從指令快 取記憶體1 0 3中讀取出程式計數器1 〇 2所指定的指令 ’並將其設定於指令暫存器1 〇 5中。另外,來自算術邏 輯單元1· 0 8的指令信號1 1 5以及旗標信號1 1 6也被 傳送至序列器1 0 4中,以便進行程式計數器1 Q 2的控 制。接著,指令指定暫存器資料係由暫存器檔案1 0 7透 過匯流排1 1 8及1 1 9而被傳送至算術邏輯單元1 0 8 中,然後算術邏輯單元1 0 8會處理這些資料。最後,所 得到的A L U運算結果便透過匯流排1 2 〇而被儲存於暫 存器檔案1 0 7內的指令指定暫存器中。 經濟部智慧財產局員工消費合作社印製 在分支指令的處理期間中,首先從指令快取記憶體中 讀取出程式計數器1 0 2所指定的指令。接著,對於 B R A而言,分支目的地的位址係從指令信號線1 1 5傳 送至序列器1 0 4以便透過匯流排1 1 2來進行程式計數 器1 0 2的控制。對於B R A c c而言,分支目的地的位 址以及來自A L U 1 〇 8的旗標信號1 1 6係透過指令信 號線1 1 5而傳送至序列器1 0 4以進行程式計數器 1 0 2的控制。對於C A L L指定而言,程式計數器 1 0 2的內容係被儲存於暫存器檔案的暫存器〇中’且分 支目的地的位址則從指令信號線115傳送至序列器 -17 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 472189 Α7 Β7 五、發明說明(15 ) 1 〇 4中,以便透過匯流排1 1 2來進行程式計數器 丄〇 2的控制。對於RTN指令而言,暫存器檔案內之暫 存器0的內容則被設定於程式計數器1 0 2中。 在載入或儲存指令的處理期間中,首先從指令快取記 憶體中讀取出程式計數器1 〇 2所指定的指令’並將其設 定於指令快取記憶體中。接著,指令信號1 1 5以及來自 算術邏輯單元1 0 8的旗標信號1 1 6也被傳送至序列器 1 0 4中,以便進行程式計數器1 0 2的控制。接著,指 令指定暫存器信號被傳送至M A R 1 1 〇中。對於 S T 0 R而言,指令中之S 1欄位所指定的暫存器信號係 被轉送至MDR109。接著,對於STOR而言, M A R 1 1 0所指定的位址信號1 1 7以及來自M D R 1 0 9的資料信號1 2 1係被傳送至記憶體界面1 〇 1 , 藉此可將資料儲存於相對位址的記憶體位置中。對於 L 0 A D而言,M A R 1 1 0所指定的位址信號1 1 7係 傳送至記憶體界面1 0 1中,相對位址中的記憶體資料貝IJ 從記憶體界面1 0 1傳送至M D R,且M D R資料然後被 轉送至指令中之D欄位所指定的暫存器內。 經濟部智慧財產局員工消費合作社印製 下文將詳述本實施例中不同於正常模式下的自我測試 運算。首先,用以指定自我測試的測試模式信號1 3 3係 從處理器的外部輸入。根據測試模式信號1 3 3 ’來自隨 機數指令產生器的輸出指令1 4 0 (而不是指令快取記憶 體的輸出指令)係藉由選擇器141傳送至指令暫存器 1 0 5。根據測試模式信號1 3 3,選擇器1 3 0選擇 -18 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用_國國家標準(CNS)A4規格(210 X 297公釐〉 472189 Α7 Β7 五、發明說明(16) MI SR1 2 7作爲MARI 1 0之位址信號1 1 7的輸 出目的地。同樣地,根據測試模式信號1 3 3 ,選擇器 1 3 1選擇Μ I S R 1 2 8作爲M D R 1 〇 9資料信號 1 2 1的輸出目的地。此外,根據測試模式信號1 3 3 , 隨機數資料產生器1 2 5所輸出的隨機數資料(而非來自 記憶體界面的資料信號1 2 2 )係藉由選擇器丨3 2傳送 至M D R 1 〇 9。另外,根據測試模式信號1 3 3 ,隨機 數資料產生器1 4 2與1 4 3 (而非暫存器檔案χ 〇 7內 的暫存益)傳送資料’然後Μ I S R 1 4 4 (而非暫存器 檔案內的暫存器)接收資料。 經濟部智慧財產局員工消費合作社印製BI nn 口 π I nn I ^^ 1 n In I This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -12-2 7 4 8) Λ7 B7 V. Description of the invention (10 14 3 14 4 9 0 0-9 3 2 10 0 1 10 0 2 10 0 3 10 0 4 0 0 7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 0 1 4 0 2 4 0 3 4 0 4 4 0 5 4 0 6 5 0 0 4 Random number data generator Multiplex input marker register Virtual random number pattern output signal Instruction selection mechanism Half instruction storage mechanism Supplementary instruction information Storage mechanism instruction generator selection signal Half instruction supplementary instruction information Linear feedback displacement temporarily Register and gate calculator or gate calculator random number generator random number generator random number generator selector decoder random number data output selector output selector random number data generator random number data generator multiplex input flag temporarily Register (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -13-3 2 7 4 A7 B7 V. Description of the invention (11 4 0 0 7 0 8 7 0 8 0 8 0 8 0 17 4 8 0 7 8 0 8 8 0 9 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 19 0 3 19 0 5 2 0 0 1 2 0 0 2 Selector Selector Storage Device Storage Device Storage Device Output Signal Output Signal Random Number Data Generator Data input signal line instruction adaptation mechanism instruction adaptation mechanism instruction adaptation mechanism selector decoder linear feedback displacement register output information random number data output instruction signal operation instruction signal linear feedback displacement register combination logic circuit data combination logic circuit Not competing (please read the precautions on the back before filling this page) Loading ----- Ordering-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 472189 Λ7 B7 5 (12) Description of the preferred embodiment The embodiment of the present invention will be described in detail below. Fig. 1 shows a LSI structure including a processor, which is an embodiment of the present invention. In this figure, 1 〇1 is a memory interface 'can be exchanged through the exchange ?; [lj row 1 1 1 and exchange signals with the memory billion; 1 〇 2 is a program counter; 103 is the instruction cache memory; 1 0 4 Sequencer used to control the program counter: 105 is the instruction register; 106 is the decoder 'used to decode the contents of the instruction register, and used to control the arithmetic logic unit and other components; 1 〇 7 is a temporary register file, which contains a random number data generator for random data output and a multiplexed input tag temporary register (M IRS) as a response analyzer; 108 is an arithmetic logic unit (ALU); 1 0 9 Is a memory data register (MDR) for exchanging data with the memory; 1 10 is a memory address register (MAR) for assigning an address to the memory interface; 1 2 3 is a random number The instruction generator is used to randomly output the instructions required for self-test; 1 2 5, 14 2 and 1 43 are the random number data generators to output the random number data; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ β --------- Order. (Please read the notes on the back before filling in this page) 1 2 6, '' 1 2 7, 1 2 8 And 1 4 4 are ^ 13 feet of the response analyzer; 129, 130, 131 '132 and 141 are selectors, which have been used during normal mode and test mode Exchange signal flow; In addition, 1 3 3 is the test mode signal input from outside the LSI to specify the self-test mode; 1 3 4 is the instruction information pair number, used to indicate the output instruction of the random number instruction generator 1 2 3 1 4 0 content. Except for receiving the instruction information signal 1 3 4, the paper size of the random number in this embodiment applies the Chinese National Standard (CNS) A4 specification (21 × X 297 mm). 15-472189 Λ7 B7 V. Description of the invention (13) Information The generator can also change the random number data generating method, so that the random number data output of the generator can be more consistent with the instructions transmitted by the random number instruction generator 1 2 3. The output signals from 1 4 4, 1 2 6, 1 2 7 and M I S R 1 2 8 respectively are transmitted to the outside of the processor. The processor instruction table in this embodiment is listed in FIG. 3. All basic instructions are internal register arithmetic operation instructions. This embodiment provides four types of branch instructions: unconditional branch instruction BRA, and conditional branch instruction BRA cc (& cc 分支 indicates a branch condition) 'branch-into-subroutine instruction CALL , And the return-from-subroutine instruction RTN. In addition, a load instruction LOAD and a store instruction S T 0 R E are also provided. In addition, the address spaces that can be specified in branch instructions (load instructions and store instructions) are all represented by a 24-bit pattern. Figure 4 shows its instruction format. All instructions have a fixed length of 32 bits. The `` f '' bit in the basic instruction format is used to indicate whether the operation result is to be included in the flag. And "S 1 〃 , , s 2 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---------- 1 -Bi -------- Xun- (Please read the back Please fill in this page again) The 〃 and w D 〃 fields indicate the first source field, the second source field, and the destination address, respectively. In addition, d 中 in the branch instruction format indicates the address of the branch destination. FIG. 5 shows a detailed instruction format used in FIG. 4 to indicate the definition of an operation code (〇 P c 〇 de e). Bits 0 to 7 in the basic instructions are all set to * 〇〃, and bit 4 to 7 in the branch instruction are also set to this paper standard applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) .- j6. 472189 A7 _ B7 V. Description of the invention (14) * 0 〃 ', and bits 8 to 3 1 enter the branch destination address. Loading (Please read the precautions on the back before filling this page) Bits 16 in the instruction and storage instructions are set to '1', and the bit of bit 〇 is used to identify L 0 AD or ST 〇RE . Next, the processing flow of the processor in this embodiment during the normal mode will be described in detail. In the basic instruction processing period of the normal mode, the instruction designated by the program counter 10 is read from the instruction cache memory 103 and set in the instruction register 105. In addition, the instruction signal 1 15 and the flag signal 1 16 from the arithmetic logic unit 1 · 08 are also transmitted to the sequencer 104 to control the program counter 1Q2. Next, the instruction specifies that the register data is transferred from the register file 1 0 7 to the arithmetic logic unit 1 0 8 through the buses 1 8 and 1 1 9, and then the arithmetic logic unit 10 8 will process the data . Finally, the obtained A L U operation result is stored in the register designated by the instruction in the register file 107 through the bus 1 2 0. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs During the processing of branch instructions, the instruction designated by the program counter 102 is first read from the instruction cache. Then, for BRA, the address of the branch destination is transferred from the command signal line 1 15 to the sequencer 104 to control the program counter 10 through the bus 1 12. For BRA cc, the address of the branch destination and the flag signal 1 1 6 from ALU 1 0 8 are transmitted to the sequencer 1 0 4 through the instruction signal line 1 1 5 to control the program counter 1 0 2 . For CALL designation, the contents of the program counter 102 are stored in the register 0 of the register file, and the address of the branch destination is transmitted from the command signal line 115 to the sequencer-17-this paper The standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472189 A7 B7 V. Description of the invention (15) 1 04, in order to control the program counter 2 through the bus 1 12. For the RTN instruction, the contents of register 0 in the register file are set in program counter 102. During the processing of the load or store instruction, the instruction designated by the program counter 102 is first read from the instruction cache memory and set in the instruction cache memory. Then, the command signal 1 15 and the flag signal 1 1 6 from the arithmetic logic unit 10 8 are also transmitted to the sequencer 1 0 4 for controlling the program counter 10 2. Then, the instruction designation register signal is transmitted to M A R 1 1 0. For S T 0 R, the register signal specified by the S 1 field in the instruction is forwarded to MDR109. Then, for STOR, the address signal 1 1 7 designated by MAR 1 1 0 and the data signal 1 2 1 from MDR 1 0 9 are transmitted to the memory interface 1 0 1, so that the data can be stored in Relative memory location. For L 0 AD, the address signal designated by MAR 1 1 0 1 1 7 is transmitted to the memory interface 1 0 1 and the memory data at the relative address IJ is transmitted from the memory interface 1 0 1 to MDR, and the MDR data is then transferred to the register specified by the D field in the instruction. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The self-test operation in this embodiment is different from that in the normal mode. First, the test mode signal 1 3 3 for specifying the self-test is input from the outside of the processor. According to the test mode signal 1 3 3 ′, the output instruction 1 4 0 from the random number instruction generator (instead of the output instruction of the instruction cache memory) is transmitted to the instruction register 1 0 5 through the selector 141. According to the test mode signal 1 3 3, the selector 1 3 0 select -18-(Please read the precautions on the back before filling this page) This paper size is applicable _ National Standard (CNS) A4 specification (210 X 297 mm> 472189 Α7 Β7 V. Description of the invention (16) MI SR1 2 7 is the output destination of the address signal 1 1 7 of MARI 1 0. Similarly, according to the test mode signal 1 3 3, the selector 1 3 1 selects Μ ISR 1 2 8 is the output destination of the MDR 1 009 data signal 1 2 1. In addition, according to the test mode signal 1 3 3, the random number data output by the random number data generator 1 2 5 (not the data from the memory interface) The signals 1 2 2) are transmitted to the MDR 1 〇 9 through the selector 丨 3 2. In addition, according to the test mode signals 1 3 3, the random number data generators 1 2 4 and 1 4 3 (instead of the register file χ 〇7 temporary storage benefits) transmission of data 'then the M ISR 1 4 4 (not the register in the register file) to receive the data. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

接著,下文將詳述本實施例之處理器在自我測試期間 的處理流程。首先,隨機數指令產生器1 2 3產生輸出指 令1 4 0 ,並傳送至指令暫存器1 0 5。另外,隨機數指 令產生器1 2 3也傳送出相對應於輸出指令1 4 0的指令 資訊信號1 3 4。接著,如果該指令是基本指令的話,則 指令信號1 1 5以及來自算術邏輯單元1 0 8的旗標信號 1 1 6便被傳送至序列器1 〇 4以控制程式計數器1 0 2 。接著,來自隨機數資料產生器1 4 2與1 4 3的隨機數 資料(而非指令指定暫存器信號)係從暫存器檔案1 〇 7 中透過匯流排1 1 8與1 1 9而傳送至算術邏輯單元 1 0 8,其中資料便在算術邏輯單元1 〇 8中運算。最後 ,運算結果則透過匯流排1 2 0而儲存於Μ I S R的內部 暫存器中(而非暫存器檔案1 0 7內的指令指定暫存器) 。來自程式計數器1 〇 2的輸出信號也被輸入於Μ I S R -19- I---------丨-I 裝----------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) 472189 A7 ---- B7 五、發明說明(17) 1 2 6 中。 經濟部智慧財產局員工消費合作社印製 -----------.-裝---------訂· (請先閱讀背面之注意事項再填寫本頁) 在分支指令處理期間中,對於B R A而言,分支目的 地的位址係從指令信號線1 1 5傳送至序列器1 〇 4以便 透過匯流排1 1 2來進行程式計數器1 〇 2的控制。接著 ’程式計數器1 〇 2的輸出信號便被傳送給Μ I S R 1 2 6。對於B R A c c而言,分支目的地的位址以及來 自A L U 1 0 8的旗標信號1 1 6係透過指令信號線 1 1 5而傳送至序列器1 〇 4以進行程式計數器1 〇 2的 控制。接著,程式計數器1 0 2的輸出信號便被傳送給 MI SR126。對於CALL指定而言,程式計數器 1 ◦ 2的內容係被儲存於暫存器檔案1 〇 7的內部 M ISR中(而非儲存於暫存器檔案的暫存器〇中)。且 分支目的地的位址則也從指令信號線1 1 5傳送至序列器 1 0 4中,以便透過匯流排1 1 2來進行程式計數器 1 0 2的控制。對於R Τ Ν指令而言,來自暫存器檔案內 之隨機數資料產生器的隨機數資料輸出(而非暫存器檔案 內之暫存器0的內容)係被設定於程式計數器1 〇 2中。 接著,程式計數器1 〇 2的輸出信號便被傳送給Μ I s R 12 6° 在載入或儲存指令的處理期間中,指令信號1 1 5以 及來自算術邏輯單兀1 0 8的旗標信號1 1 6也被傳送至 序列器1 0 4中’以便進行程式計數器1 0 2的控制。接 著,暫存器檔案1 0 7內之隨機數產生器所產生的輸出信 號(而非指令指定暫存器信號)被傳送至M A R 1 1 〇中 本紙張尺度適用中國國家標準(CNS)A4規格(2i0 X 297公釐)-20-Next, the processing flow of the processor of this embodiment during the self-test will be detailed below. First, the random number instruction generator 1 2 3 generates an output instruction 1 4 0 and transmits it to the instruction register 1 0 5. In addition, the random number command generator 1 2 3 also sends a command information signal 1 3 4 corresponding to the output command 1 40. Then, if the instruction is a basic instruction, the instruction signal 1 15 and the flag signal 1 1 6 from the arithmetic logic unit 10 8 are transmitted to the sequencer 104 to control the program counter 10 2. Next, the random number data from the random number data generators 1 2 2 and 1 4 3 (instead of the register buffer signal specified by the instruction) are obtained from the register file 1 07 through the buses 1 1 8 and 1 1 9 It is transmitted to the arithmetic logic unit 108, where the data is calculated in the arithmetic logic unit 108. Finally, the operation result is stored in the internal register of MI SR through the bus 120 (not the register specified by the instruction in the register file 107). The output signal from the program counter 1 〇2 is also input to Μ ISR -19- I --------- 丨 -I equipment ------------ order Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm) 472189 A7 ---- B7 V. Description of the invention (17) 1 2 6 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -----------.- Pack --------- Order (Please read the precautions on the back before filling this page) In the branch During the instruction processing period, for the BRA, the address of the branch destination is transmitted from the instruction signal line 1 15 to the sequencer 1 104 to control the program counter 1 2 through the bus 1 1 2. Then, the output signal of the program counter 102 is transmitted to M IS R 1 26. For the BRA cc, the address of the branch destination and the flag signal 1 1 6 from ALU 1 0 8 are transmitted to the sequencer 1 〇 4 through the command signal line 1 1 5 to control the program counter 1 〇 2 . Then, the output signal of the program counter 102 is transmitted to the MI SR126. For CALL designation, the contents of the program counter 1 ◦ 2 are stored in the internal M ISR of the register file 107 (not in the register 0 of the register file). And the address of the branch destination is also transmitted from the command signal line 1 15 to the sequencer 104, so that the program counter 1 102 can be controlled through the bus 1 12. For the R T Ν instruction, the random number data output from the random number data generator in the register file (not the content of register 0 in the register file) is set to the program counter 1 〇 2 in. Then, the output signal of the program counter 10 is transmitted to M I s R 12 6 ° During the processing of the load or store instruction, the instruction signal 1 1 5 and the flag signal from the arithmetic logic unit 10 8 1 1 6 is also transmitted to the sequencer 104 to control the program counter 102. Then, the output signal generated by the random number generator in the register file 107 (not the register signal specified by the instruction) is transmitted to MAR 1 10. The Chinese paper standard is applicable to the Chinese National Standard (CNS) A4 specification. (2i0 X 297 mm) -20-

47218B 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(19 ) 控Μ I S R輸出信號;以及將這些信號與事先計算好的無 錯誤Μ I s R輸出資料進行比較。 如本實施例所示,隨機指令產生功能使得該測試可在 指令出現順序不同的組合下進行。另外,因爲利用隨機數 指令產生器所產生的指令資訊來產生與執行指令相符的隨 機數資料,所以可增進測試效能。 .圖6顯示隨機數指令產生器的一個實施例,其中隨機 數指令產生器包含:指令儲存機構7 1 ’用以儲存測試指 令;以及指令選擇機構7 2,用以隨機選擇指令儲存機構 所儲存的指令。 整個操作是藉由輸入用以表示自我測試的測試模式信 號1 3 3而開始的。首先,用以作爲選擇那些儲存於指令 儲存機構7 1內之指令的參考資訊係從指令選擇機構7 2 傳送至指令儲存機構7 1以作爲選擇信號7 3 ,然後此資 訊係作爲指令資訊信號1 3 4來傳送。接著,指令儲存機 構7 1在接收到選擇信號7 3之後便傳送相對應的指令給 14 0。 可藉由一個用以接收選擇信號7 3與位址信號的記憶 體來實現本實施例的指令儲存機構7 1。圖7顯示一個記 憶體的範例。在此記憶體中,位址係爲3 2位元’且自我 測試期間所產生的指令係爲圖5所示的3 2位元資料格式 。在圖8的範例中’儲存有'' η 〃個指令數。例如’以 3 2 位元碼"000000000000000100000 H00l100100 〃 所表示 的、、A D D 0 ,R ( 1 ) ,R ( 1 9 ) ,R ( 4 )"指令 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -22- ------------.!裝----*----訂· (請先閱讀背面之注意事項再填寫本頁) 472189 A7 B7 五、發明說明(20)47218B Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (19) Control M I S R output signals; and compare these signals with pre-calculated error-free M I s R output data. As shown in this embodiment, the random instruction generation function enables the test to be performed under a combination of instructions in different order of appearance. In addition, because the random number instruction generator is used to generate random number data corresponding to the executed instructions, the test performance can be improved. FIG. 6 shows an embodiment of a random number instruction generator, wherein the random number instruction generator includes: an instruction storage mechanism 7 1 ′ for storing test instructions; and an instruction selection mechanism 72 for randomly selecting the instructions stored in the instruction storage mechanism. Instructions. The entire operation is started by entering a test mode signal 1 3 3 to indicate a self-test. First, the reference information used to select the instructions stored in the instruction storage mechanism 71 is transmitted from the instruction selection mechanism 7 2 to the instruction storage mechanism 7 1 as the selection signal 7 3, and then this information is used as the instruction information signal 1. 3 4 to teleport. Next, after receiving the selection signal 73, the instruction storage mechanism 71 transmits a corresponding instruction to 140. The instruction storage mechanism 71 of this embodiment may be implemented by a memory for receiving the selection signal 73 and the address signal. Figure 7 shows an example of a memory. In this memory, the address is 32 bits, and the instructions generated during the self-test are in the 32 bit data format shown in FIG. 5. In the example of FIG. 8, 'n' is the number of instructions. For example, '3 2 digit code " 000000000000000100000 H00l100100 〃, ADD 0, R (1), R (1 9), R (4) " Instruction This paper standard applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -22- ------------.! Packing ---- * ---- Order · (Please read the precautions on the back before filling this page) 472189 A7 B7 V. Description of the invention (20)

係儲存於位址’’ 0 0 0 0 ”中,而且以3 2位元碼A 1000000000000000 1 0000 1 0000000 100 〃所表示的 (請先閱讀背面之注意事項再填寫本頁) LOAD R ( 1 ) ,R ( 4 ) 〃係儲存於位址'' Π 〃中 〇 本實施例的指令選擇機構7 2可採用一般作爲虛擬隨 機數產生器之用的線性回饋位移暫存器(L S F R )。 經濟部智慧財產局員工消費合作社印製 L F S R將其位移暫存器的最終狀態回饋給位移暫存器之 初始狀態的D —正反器’且同時利用互斥邏輯總和來將回 饋提供給中間狀態的D -正反器。除了所有位元皆爲w 〇 〃的情況之外,可藉由這種回饋結構以虛擬隨機的方式來 產生所有的位元圖樣。圖8顯示3 3位元之L F S R的範 例。在此圖示中’ 9 1爲D_正反器’而9 0 0至9 3 2 則爲3 3位元的虛擬隨機數圖樣輸出信號。在L F S R中 ,可藉由執行D -正反器的一個位移運算來獲得一個虛擬 隨機數,然後將D -正反器的結果信號資料指派給3 3位 元的虛擬隨機數圖樣輸出信號9 0 0至9 3 2。藉由重複 執行上述的位移運算便可取得複數個虛擬隨機數圖樣輸出 信號。另外,當初始L F S R資料中的所有位元皆爲"0 〃時,因爲尙未產生虛擬隨機數,所以正反器係由信號資 料組合所初始化;在所有位元皆爲〇 〃以外的情況下’ 當啓動LS I或者是當測試模式信號改變成自我測試模式 信號時,則正反器將作爲D -正反器使用。 圖6之實施例可利用下列方式來實現:從圖8的 L F S R中選擇那些含有用以指定記憶體內之特定指令所 -23- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製Stored in the address '' 0 0 0 0 '', and indicated by the 32-bit code A 1000000000000000 1 0000 1 0000000 100 〃 (Please read the precautions on the back before filling this page) LOAD R (1) R (4) is stored in the address '' Π〃. The instruction selection mechanism 7 2 of this embodiment may use a linear feedback shift register (LSFR) generally used as a virtual random number generator. Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative prints LFSR to return the final state of its displacement register to the initial state of the displacement register D-flip-flop ', and at the same time uses the sum of mutually exclusive logic to provide feedback to D in the intermediate state -Flip-flop. Except for the case where all bits are w 〇〃, all bit patterns can be generated in a virtually random manner by this feedback structure. Figure 8 shows an example of 33-bit LFSR In this illustration, '9 1 is the D_ flip-flop' and 9 0 to 9 3 2 are the 33-bit virtual random number pattern output signal. In LFSR, you can perform D-forward and reverse A shift operation to get a virtual random number, and then D-The result signal data of the flip-flop is assigned to the 33-bit virtual random number pattern output signals 9 0 to 9 3 2. By repeatedly performing the above-mentioned shift operation, a plurality of virtual random number pattern output signals can be obtained. In addition, when all the bits in the initial LFSR data are " 0 〃, because 尙 does not generate a virtual random number, the flip-flop is initialized by the signal data combination; in the case where all the bits are other than 0〃 Down 'When the LS I is activated or when the test mode signal is changed to a self-test mode signal, the flip-flop will be used as a D-flip-flop. The embodiment of FIG. 6 can be implemented in the following ways: from the LFSR of FIG. 8 Select those that contain specific instructions to designate the memory. 23- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.

47218B A7 _ B7 五、發明說明(21 ) 需之位元的輸出信號,然後將作爲位址信號線之用的相對 應輸出信號線連接至記憶體,並且以1 : 1的比率來傳送 那些鍵入於記憶體儲存指令中的位址信號’以作爲用以識 別隨機數指令產生器發送指令所需的指令資訊信號1 3 4 。另外,可藉由、、將一個指令事先儲存於記億體之多重位 址中,可增加指令選擇機構重複選擇該指令的或然率〃的 理由,來設定隨機數指令產生器產生指令的機率。 圖9顯示隨機數指令產生器的另一個實施例。隨機數 指令產生器包含:半指令儲存機構1 0 0 2 ’用以儲存部 份或全部欲執行的每個指令:補充指令資訊儲存機構 1 〇 0 3 ,用以儲存執行半指令儲存機構內之半指令時所 需的補充資訊;指令選擇機構1 0 0 1 ,用以分別從半指 令儲存機構以及補充指令資訊儲存機構中隨機選擇半指令 以及對應的補充指令資訊;以及指令產生器,用以根據所 選出之半指令以及補充指令資訊來補足隨機數資料,以產 生處理器所欲執行的指令。 整個操作是藉由輸入用以表示自我測試的測試模式信 號1 3 5而開始的。首先,用以作爲選擇那些儲存於指令 儲存機構1 0 0 2內之半指令的參考資訊係從指令選擇機 構1 0 0 1傳送至半指令儲存機構1 0 0 2以作爲選擇信 號1 0 0 5。同時,選擇信號1 〇 0 5係傳送至補充指令 資訊儲存機構以便選擇對應於選擇資訊的補充指令資訊。 然後選擇信號1 0 0 5係作爲指令資訊信號1 3 4而傳送 至半指令儲存機構1 0 0 2,藉此相對應於選擇信號 --------------- 裝----------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -24 - 472189 A7 ___B7 五、發明說明(22) (請先閱讀背面之注意事項再填寫本頁) 1 0 0 5的半指令1 ο 〇 6便被傳送至指令產生器 1 0 0 4。此外’相對應於選擇信號1 〇 〇 5的補充指令 資訊1 0 0 7也從補充指令資訊儲存機構1 〇 〇 3傳送至 指令產生益1 0 0 4。最後,在接收到半指令1 〇 〇 6與 補充指令資訊1 0 0 7之後,指令產生器1 0 0 4藉由將 補充隨機數資料指派給半指令的缺失部位以產生可執行的 指令,並將指令發佈爲輸出指令1 4 0。 可利用那些將選擇信號1 〇 〇 5接收爲位址信號的記 憶體來實現本實施例的半指令儲存機構1 〇 0 2與補充指 令資訊儲存機構1 0 0 3。圖1 0顯示用以實現這種半指 令儲存機構之記憶體的範例。在此記憶體中,位址係爲 3 2位元,且自我測試期間所產生的指令係爲圖5所示的 3 2位元+資料格式。此時,在整個欲儲存的指令碼中,只 有那些將被隨機數資料所補充進去的位元是設定爲'' 0 〃 。在圖1 0的範例中,儲存有'' m 〃個指令數。例如,以 3 2 位元碼"〇〇〇〇〇〇〇〇〇〇〇〇〇〇1〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〃 所表示 的'' S U B,〇,? ,?,? 〃指令係儲存於位址0001 〃中,而且以3 2位元碼'' 經濟部智慧財產局員工消費合作社印製 001 00000000000000000000000000000 〃 所表示的 '' B R A ?"係儲存於位址'' 0 0 0 4 〃中,其中指令中的'' ? 〃 是表示每個指令碼中將被隨機數資料所塡入的欄位。例如 ,在位址、0001〃的情況下’ w?〃表示指令碼的位 元1 7至3 1將被隨機數資料所塡入’且相對應的位元將 被儲存爲"0 〃 。圖1 1顯示一個用以實現補充指令資訊 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) .25 - 472189 A7 B7 五、發明說明(23) 儲存機構之記憶體的範例°位址係爲3 2位元’且補充指 令資訊係以3 2位元圖樣來表示。另外’那些儲存於圖 10之記億體內的半指令以及那些相對應於每個半指令的 補充指令資訊皆以匹配方式來儲存。補充指令資訊的格式 是相對應於那些儲存於半指令儲存機構內的半指令’在每 個欲塡入隨機數資料之半指令內的位兀係設爲 1 ’而 其他的位元則設爲、' 〇 〃 。在圖1 1的範例中’對於位址 ο ο ο Γ而言,相對應於圖1 〇之半指令的位元1 7至 3 1係設爲、、1 〃 ,而其他的位元則設爲'' 〇 〃 。因此’ 3 2 位元碼 '、〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇1111111111111111 〃 便儲存 於相對應的位址中。同樣地’對於位址〇 〇 〇 4而言’用 以表示分支指令之分支目的地的位元8至2 1係設爲"1 ",而位元0至7則設爲"0 〃 。因此,3 2位元碼" ooooooooimimiiiimiiiiiiin 〃便儲存於相對應的位 址中。 經濟部智慧財產局員工消費合作社印製 圖1 2顯示指令產生器1 0 0 4的詳細實施例。指令 產生器包含:L F S R 1 3 Ο 1 ,當輸入用以表示自我測 試模式的測試模式信號1 3 3時,可作爲一個3 2位元的 虛擬隨機數圖樣產生器;3 2位元的及閘計算器1 3 0 2 ,其接收兩組3 2位元的資料,然後在計算出每個位元的 邏輯乘積之後將其結果輸出;以及3 2位元的或閘計算器 1 3 0 3 ,其接收兩組3 2位元的資料,然後在計算出每 個位元的邏輯總和之後將其結果輸出。 在運算期間中,首先計算出補充指令資訊儲存機構所 -26 - -----------…-跋----------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 472189 A7 B7____ 五、發明說明(24 ) 給定之補充指令資訊1 0 0 7每個位元之間的邏輯乘積以 及L F S R 1 3 0 1所給定之虛擬隨機數資料每個位元之 ^ 間的邏輯乘積,並且藉由將隨機數資料指派給僅需補充的 位元,以產生作爲輸出之用的3 2位元資料。接著’計算 出半指令儲存機構所給定之3 2位元資料以及半指令 1 0 0 6每個位元之間的邏輯總和,並且藉由將隨機數資 料指派給僅需補充的位元,以產生作爲輸出之用的3 2位 元資料, 可利用圖8所示的L F S R來作爲指令選擇機構 1 0 0 1。從L F S R輸出中選擇出相當於用以指定半指 令儲存記憶體與補充指令資訊儲存記憶體兩者內容所需之 位元數的輸出信號,然後將所選擇的信號線連接至位址信 號線。那個接收到位址信號的記憶體將相對應的位址資料 當成半指令1 0 0 6與補充指令資訊1 0 0 7。如果位址 資料是當成指令資訊信號1 3 4來傳送的話,則便可識別 出隨機數指令產生器所輸出的輸出指令。在上述實施例的 結構中,爲了增進效能之故,儲存於記憶體中的的半指令 i 數係等於2的指數倍數(如圖6的實施例所示)。然而’ 經濟部智慧財產局員工消費合作社印製 L F S R的輸出也可被正常化成事先儲存於記憶體中之'' m 〃個半指令數。另外,可藉由“將一個指令事先儲存於 記憶體之多重位址中,可增加指令選擇機構重複選擇該指 令的或然率“的理由,來設定隨機數指令產生器產生指令 的機率。 相較於圖6 ,因爲圖9之實施例可藉由指派隨機數資 -27- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 47218947218B A7 _ B7 V. Description of the invention (21) The output signal of the required bit, then connect the corresponding output signal line for the address signal line to the memory, and transmit those keystrokes at a 1: 1 ratio The address signal 'in the memory storage instruction is used as the instruction information signal 1 3 4 for identifying the random number instruction generator to send the instruction. In addition, the probability that the random number instruction generator will generate an instruction can be set by storing an instruction in multiple addresses of the memory in advance, and increasing the reason why the instruction selection mechanism repeatedly selects the instruction. FIG. 9 shows another embodiment of the random number instruction generator. The random number instruction generator includes: a half-instruction storage mechanism 1 0 2 'to store each or all of the instructions to be executed: a supplementary instruction information storage mechanism 1 0 3 to store the execution in the half-instruction storage mechanism Supplementary information required in the case of a half-instruction; the instruction selection mechanism 1 0 0 1 is used to randomly select the half-instruction and the corresponding supplementary instruction information from the half-instruction storage mechanism and the supplementary instruction information storage mechanism respectively; and an instruction generator for The random number data is supplemented according to the selected half instruction and the supplementary instruction information, so as to generate an instruction to be executed by the processor. The entire operation is started by entering a test mode signal 1 3 5 to indicate a self-test. First, the reference information used to select those half-commands stored in the command storage mechanism 1 0 0 2 is transmitted from the command selection mechanism 1 0 0 1 to the half-command storage mechanism 1 0 0 2 as a selection signal 1 0 0 5 . At the same time, the selection signal 105 is transmitted to the supplementary instruction information storage mechanism to select the supplementary instruction information corresponding to the selection information. Then the selection signal 1 0 0 5 is transmitted as the command information signal 1 3 4 to the half-command storage mechanism 1 0 2 to thereby correspond to the selection signal. ---------- Order · (Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -24-472189 A7 ___B7 V. Description of the invention (22) (Please read the precautions on the back before filling in this page) The half command 1 0 0 5 of 1 0 0 5 is transmitted to the command generator 1 0 4. In addition, the supplementary instruction information 1 0 7 corresponding to the selection signal 1 0 05 is also transmitted from the supplementary instruction information storage mechanism 1 0 3 to the instruction generating benefit 1 104. Finally, after receiving the half instruction 1006 and the supplementary instruction information 1007, the instruction generator 1104 generates executable instructions by assigning the supplementary random number data to the missing part of the half instruction, and Issue the instruction as an output instruction 1 4 0. The memory that receives the selection signal 105 as an address signal can be used to implement the semi-command storage mechanism 1 0 2 and the supplementary command information storage mechanism 1 0 3 in this embodiment. Figure 10 shows an example of the memory used to implement such a semi-command storage mechanism. In this memory, the address is 32 bits, and the instructions generated during the self-test are 32 bits + data format as shown in FIG. 5. At this time, in the entire instruction code to be stored, only those bits to be supplemented by random number data are set to `` 0 〃. In the example in FIG. 10, `` m '' instruction numbers are stored. For example, the "SUB" represented by a 32-bit code " 0000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000, and 10,000, and 〇 ,? ,? ,? The 〃 instruction is stored in the address 0001 ,, and it is stored in the address 0001 3 `` BRA? &Quot; is stored in the address '' with a 32-bit code `` printed by 001 00000000000000000000000000000 〃 0 0 4 〃, where the ''? 〃 in the instruction is a field that will be entered by random number data in each instruction code. For example, in the case of address, 0001〃, 'w? 〃 means that bits 17 to 31 of the instruction code will be entered by random number data' and the corresponding bits will be stored as " 0 〃. Figure 11 shows a paper used to implement the supplementary instruction information. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 25-472189 A7 B7 V. Description of the invention (23) Example of the memory of the storage mechanism ° The address is 32-bit 'and the supplementary instruction information is represented by 32-bit pattern. In addition, those semi-commands stored in the memory of Figure 10 and the supplementary command information corresponding to each semi-command are stored in a matching manner. The format of the supplementary instruction information is corresponding to those of the half instructions stored in the half instruction storage mechanism. 'The bit system in each half instruction that wants to enter random number data is set to 1', and the other bits are set to , '〇〃. In the example in FIG. 11 'for the address ο ο ο Γ, the bits 17 to 3 corresponding to the half instruction of FIG. 10 are set to 1, and 1 ,, and the other bits are set to Is '' 〇〃. Therefore, the '32 -bit code ', 100,000, 000, 000, 000, 000, 000, 11, 111, 111, 111, 111 111 are stored in the corresponding addresses. Similarly, 'for address 00-04', bits 8 to 21 used to indicate the branch destination of the branch instruction are set to "1" and bits 0 to 7 are set to "0" 〃. Therefore, the 32-bit code " ooooooooimimiiiimiiiiiiin 〃 is stored in the corresponding address. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 12 shows a detailed embodiment of the instruction generator 104. The instruction generator includes: LFSR 1 3 Ο 1, when a test mode signal 1 3 3 is input to indicate a self-test mode, it can be used as a 32-bit virtual random number pattern generator; a 32-bit sum gate Calculator 1 3 0 2, which receives two sets of 32-bit data, and then outputs the result after calculating the logical product of each bit; and 32-bit OR gate calculator 1 3 0 3, It receives two sets of 32-bit data, and then outputs the result after calculating the logical sum of each bit. During the calculation period, first calculate the supplementary instruction information storage institution -26------------...- post ---------- order (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472189 A7 B7____ V. Description of the invention (24) The given supplementary instruction information 1 0 0 7 And the logical product of each bit of the virtual random number data given by LFSR 1 3 0 1, and by assigning the random number data to only the bits that need to be supplemented, it is generated as an output 3 2-bit data. Then 'calculate the logical sum of the 32-bit data given by the half-instruction storage mechanism and each bit of the half-instruction 106, and assign random number data to only the bits that need to be supplemented to To generate 32-bit data for output, the LFSR shown in FIG. 8 can be used as the instruction selection mechanism 1 0 0 1. From the L F S R output, select an output signal equivalent to the number of bits required to specify the contents of both the half-command storage memory and the supplementary command information storage memory, and then connect the selected signal line to the address signal line. The memory that received the address signal treats the corresponding address data as a half command 1 0 6 and supplementary command information 1 0 7. If the address data is transmitted as the command information signal 1 3 4, the output command output by the random number command generator can be identified. In the structure of the above embodiment, in order to improve performance, the number of semi-instructions i stored in the memory is equal to an exponential multiple of 2 (as shown in the embodiment of FIG. 6). However, the output of the L F S R printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs can also be normalized to '' m 半 one and a half instruction numbers stored in memory in advance. In addition, the probability that the random number instruction generator generates an instruction can be set by the reason that "an instruction is stored in multiple addresses in memory in advance, and the instruction selection mechanism can repeatedly select the probability of the instruction". Compared to Figure 6, because the embodiment of Figure 9 can be assigned random number data -27- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472189

五、發明說明(25 ) 料來補充每個指令以產生複數個指令,所以能夠測試大量 的指令組合。 圖1 3顯示圖1之隨機數資料產生器的詳細實施例。 追些隨機數資料產生器具有:3 2位元的隨機數產生器 1 4 0 1至1 4 0 3 ;選擇器1 4 0 4 ,用以選擇隨機數 產生器的一組輸出資料’並且用以傳送隨機數資料 1 4 0 6 ;以及解碼器1 4 0 5 ,其可接收指令資訊信號 1 3 4 ’然後判斷隨機數產生器是否要傳送隨機數資料, 且如果要傳送資料的話,則將那些用來指定對應於指令資 訊信號之隨機數產生器輸出的資訊以及那些用以指定隨機 數產生器所欲執行之運算的信號傳送給選擇器。 隨機數產生器1 4 0 1至1 4 0 3傳送用以執行測試 選項所需之資料格式的資料。 在處理期間中,首先,當輸入隨機數指令產生器 1 2 3的指令資訊信號1 3 4時,解碼器1 4 0 5便判斷 隨機數資料產生器是否要傳送隨機數資料,且如果要傳送 資料的話,則那些用來指定對應於指令資訊信號之隨機數 -----------.i --------訂 _ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 器 1 資料指產數 碼 ο 令資應數機 解 4 指數對機隨 且 1 於機相隨的 ,器對隨於的式 4 生相的配例格 ο 產送器匹施料 4 數傳生爲實資 1 機會產作本之 器隨器數送在需 擇給擇機傳。所 選定選隨被料項 給指該自} 資選 送算中來定數試 傳運其,指機測 被出,著所隨行 將輸個接 5 的執 訊料一 。ο 4 以 資資的料 4 3用 的數中資 1 1 些 出機 3 數器r别 輸隨 ο 機碼信 , 器把 4 隨解訊中 生會 1 的由資器 產將至訊 ^ 令生 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐).28- 472189 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(26 ) 資料可被傳送作爲匹配於相對應指令的隨機數資料。 可利用組合電路來實現甩以傳送該匹配於指令資訊信 號之隨機數資料的隨機數產生器,其中該組合電路利用 L F S R及其輸出以作爲輸入之用。例如,如果具有固定 位元資料之部份係作爲用以測試指令'' a 〃的資料部份的 話,便可利用增設一個L F S R輸出遮罩(masking )電路 來完成。圖1之實施例中所示的載入指令是一個特定的範 例。LOAD R ( S 1 ) ,R(D)是一個載入指令, 其中S 1指定之記憶體所定址的記憶體資料將被傳送至D 所指定的暫存器中。在此指令下,當使用隨機數產生器所 輸出的資料(非S 1所指定的暫存器資料)時,因爲位址 空間的長度受限於2 4位元,所以隨機數產生器輸出資料 也必須以2 4位元的圖樣來表示。圖1 8顯示一種用以傳: 送匹配於此載入指令之隨機數資料的隨機數產生器。此隨 機數產生器包含:LFSR1902 ,其傳送32位元的 虛擬隨機數;以及組合邏輯電路1 9 0 3 ,其執行8位元 的乘積運算。 在處理期間中,首先,當從解碼器1 4 0 5中輸入蓮 算指令信號1 9 0 1時,L F S R會傳送一個3 2位元的 虛擬隨機數圖樣。接著,3 2位元之虛擬隨機數圖樣中白勺 較高階八位元信號將被傳送至組合邏輯電路1 9 0 3中, 然後進行那些八位元皆爲"0〃之信號的乘積運算,並雜 此傳送那些八位元皆.爲"0 〃的資料1 9 0 5 。最後,由 資料1 9 0 5以及3 2位元虛擬隨機數圖樣中之較低階 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) .2Q . ----------I裝--------訂- (請先閱讀背面之注意事項再填寫本頁) 472189 A7 B7 五、發明說明(27) 2 4位元資料1 9 0 4所組成的資料將作爲匹配於戦入指 令的3 2位元資料。 另外’當藉由調整每個位元所產生之、' 〇 〃與、、丄" 的機率所取得的貝料係作爲用以確認執行測試選項所需之 資料格式之指令b 〃的資料時,可藉由設計一種運用下 列因素的組合電路來建構隨機數產生器:當L F S R之多 重輸出位元之間的邏輯總和係作爲其輸出之用時,將會增 力口 '' 1 〃 ’的產生機率;且當邏輯乘積係作爲其輸出之用時 ,則會增加'' 0 〃的產生機率。 .在位元圖樣集合是作爲用以匹配指令'' c 〃之資料的 情況下,當從圖樣集合中所隨機選出的圖樣是要作爲用以 匹配於指令'' c 〃的資料來使用時,便可利用L F S R以 及儲存有位元圖樣的記憶體來實現,然後利用L S F R的 輸出來產生記憶體資料輸出位址。 圖1 7顯示圖1中所使用之隨機數資料產生器的另一 個實施例。 經濟部智慧財產局員工消費合作社印製 ------------'裝---------訂. (請先閱讀背面之注意事項再填寫本頁) 這些隨機數資料產生器包含:解碼器1 8 0 5 ’其可 接收指令資訊信號1 3 4,然後判斷隨機數產生器是否要 傳送隨機數資料,且如果要傳送資料的話’則不僅將用來 指定隨機數資料輸出運算的信號給L F S R 1 8 0 7 ’也 傳送用以選擇內些匹配於指令資訊之隨機數資料的資訊 1 8 0 8 ; L F S R 1 8 0 7 ’用以輸出3 2位元的虛擬 隨機數資料;指令適應機構I801至1803 ’在將資 料轉換成那個適用於指令資訊信號1 3 4所足義之指令旳 本紙張尺度適用中國國家標準(CNS)A4規格(210 297公楚) -30 - 472189 " -............. B7 五、發明說明(28 ) 隨機數食料之後,用以傳送L F s R 3 2位元的資料給選 擇器1804 ;選擇器18〇4,其中根據選擇資訊 1 8 0 8而從指令適應機構之輸出中選擇出適應於指令資 訊的隨機數資料’然後傳送至下個階段。 經濟部智慧財產局員工消費合作社印製 I----------—裝-------訂. (請先閱讀背面之注意事項再填寫本頁) 在處理期間中’首先’當從隨機數指令產生器1 2 3 輸入指令資訊信號1 3 4時,解碼器1 8 0 5便判斷隨機 數資料產生器是否要傳送隨機數資料,且如果要傳送資料 的話’則那些用來指定指令適應機構傳送相對應於指令資 訊信號之隨機數資料的資訊將被傳送給選擇器1 8 0 4 , 且解碼器將會把隨機數資料輸出指令信號1 8 0 9傳送給 LFSR1807。接著,接收有該指令的l F S R 1 8 0 7會將虛擬隨機數資料傳送給指令適應機構 1 8 0 1至1 8 0 3。在接收到來自L F S R的虛擬隨機 數資料之後,指令適應機構會將紫資料轉換成適應於該指 令的隨機數資料,並且將隨機數資料傳送給選擇器 1 8 0 4。在此選擇器中,根據選擇資訊1 8 0 8而從指 令適應機構的輸出虛擬隨機數資料中選擇出適應於該指令 資訊信號1 3 4的虛擬隨機數資料,並且傳送至下個階段 ,以作爲適應於該指令資訊信號1 3 4所定義之指令的隨 機數資料。 圖1之實施例中所示的載入指令是一個特定的範例° LOAD R ( S 1 ) ,R ( D )是一個載入指令’其中 S 1指定之記憶體所定址的記憶體資料將被傳送至D所指 定的暫存器中。在此指令中’當使用隨機數產生器所輸出 本紙張尺度朋+關緖準(CNS)A4規格(210 x 297公釐).31 - 472189 Α7 Β7 五、發明說明(29) 的資料(非S 1所指定的暫存器資料)來隨機改變相對應 的位址並進行指令執行測試時,因爲位址空間的長度受限 於2 4位元,所以隨機數產生器輸出資料也必須以2 4位 元的圖樣來表示。圖1 9顯示一種指令適應機構,用以將 L F S R 1 8 0 7輸出虛擬隨機數資料轉換成匹配於此載 入指令的格式。此指令適應機構包含:組合邏輯電路 2 0 0 1,其執行8位元的乘積運算;以及穿透電路 2 0 0 2 ,其不須進行任何修正便可傳送2 4位元的信號 0 圖1 4顯示圖1中之暫存器檔案的詳細實施例。此暫 存器檔案包含:3 2暫存器,其具有兩個讀取埠以及一個 寫入埠,並用以儲存.資料;輸出選擇器1 5 0 0及 1 5 0 1 ,其將測試模式信號改變成隨機數資料產生器輸 出信號(而不是暫存器輸出信號),並且將隨機數資料產 生器輸出信號傳送至資料匯流排;Μ I S R 1 5 0 5,接 收3 2位元的資料以作爲響應分析器使用;以及輸入選擇 器’其中由匯流排1 2 0所輸入的暫存器寫入資料將透過 測試模式信號而傳送至該Μ I S R。 經濟部智慧財產局員工消費合作社印製 在正常運算模式下,由匯流排1 2 0所輸入的暫存器 寫入資料係儲存於由指令所指定的暫存器中。另外,指令 選擇暫存器資料也被傳送至匯流排1 1 8及1 1 9。在自 我測試模式中,由匯流排1 2 0所輸入之暫存器寫入資料 被輸入選擇器傳送至Μ I S R 1 5 0 5中。另外,指令選 擇暫存器資料轉變成隨機數資料產生器1 5 0 3及 -32- -----------' 裝 -------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) 472189 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(30) 1 5 0 4的輸出,然後該資料隨後被傳送至匯流排1 1 8 及 1 1 9 ° 圖1 5顯示一種此結構的實施例,其中隨機數資料輸 出機構(而非序列器1 0 4中之一個或一個以上的儲存裝 置)傳送圖1之實施例情況下的信號,其中測試模式信號 指定爲自我測試模式。序列器是一種序列電路,包含:組 合電路區塊1 6 0 1以及” i ”個儲存裝置1 6 0 4至 1 6 0 6。當測試模式信號1 3 3指定爲自我測試模式時 ,選擇器1 6 0 2及1 6 0 3便會傳送隨機數資料產生器 1609 (而非儲存裝置1605及1606)的輸出信 號1 607及1 608。可藉由從圖8所示之LFSR的 輸出中指派兩個位元,以取得隨機數資料產生器的輸出資 料。在本實施例中,雖然兩個儲存裝置係受選擇器所選擇 ,但信號輸出結構並不侷限於此,反而可更進一步包含一 個或多個儲存裝置。即使隨機數指令產生器已經產生非分 支指令,本實施例之結構也可利用不同的程式計數器資料 來進行測試。 圖1 6顯示圖1之Μ I S R實施例的結構。通常 Μ I S R在Β I S Τ功能區塊中係被作爲響應分析器來使 用’且響應分析器可利用互斥邏輯總和來將信號傳送至 L F S R的每個位元中。在圖1 6中,1 7爲D -正反器 ’且1 7 0 〇至1 7 3 2係3 3位元圖樣的資料輸入信號 線。資料取得所需的信號係被連接至輸入信號線u藉由將 D -正反器之輸出以及位移期間所需之資料之間的互斥邏 --------------.裝._——訂. (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) -33- 472189 A7 B7 五、發明說明(31 ) 輯總和傳送至每個D -正反器來完成資料之取得。根據本 發明,藉由提供一種可隨機產生測試指令之功能以進行大 量指令產生序列之組合的測試。另外,因爲可利用隨機數 指令產生器所產生的指令資訊來形成與執行指令相互匹配 的隨機數資料,所以可增進其測試效能並提供高的錯誤偵 測率。此外,也可利用諸如隨機數指令產生器以及隨機數 資料輸出機構等硬體來實現快速的測試運算。 根據本發明,可實現高的錯誤偵測率以及快速的測試 ------------ii-------訂· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) _ 34 -5. Description of the invention (25) It is expected to supplement each instruction to generate a plurality of instructions, so it is possible to test a large number of instruction combinations. FIG. 13 shows a detailed embodiment of the random number data generator of FIG. 1. Some random number data generators have: a 32-bit random number generator 1 4 0 1 to 1 4 0 3; a selector 1 4 0 4 to select a set of output data of the random number generator 'and use To send random number data 1 4 0 6; and the decoder 1 4 0 5, which can receive the instruction information signal 1 3 4 ′ and then determine whether the random number generator is to send random number data, and if it is to send data, it will send Those used to specify the output of the random number generator corresponding to the instruction information signal and those used to specify the operation to be performed by the random number generator are transmitted to the selector. The random number generator 1 4 0 1 to 1 4 0 3 transmits data in the data format required to execute the test option. During the processing period, first, when the instruction information signal 1 3 4 of the random number instruction generator 1 2 3 is input, the decoder 1 4 0 5 determines whether the random number data generator is to transmit random number data, and if it is to transmit If it is data, those random numbers that are used to specify the command information signal -----------. I -------- order_ (please read the precautions on the back before filling in this Page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative Printed Device 1 Data refers to the production of digital information ο order the data to be solved by machine 4 index-to-machine and 1 to machine-to-machine, machine-to-machine 4格 ο Production and delivery equipment, material application, 4 data transmission as actual capital, 1 opportunity to produce the equipment, and the number of equipment will be sent to the machine. The selected item will be sent to the operator for a certain number of trials during the calculation. It will be tested by the computer, and the follow-up will be followed by a message of 5. ο 4 Use the materials 4 3 Use the data 1 1 Some out of the machine 3 Do not enter the machine code ο The machine code letter, the device 4 will follow the information from the Zhongsheng Club 1 to the news ^ The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 28- 472189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (26) Information can be transmitted as a match Random number data corresponding to the instruction. A random number generator can be implemented by using a combination circuit to transmit the random number data matching the instruction information signal, wherein the combination circuit uses L F S R and its output as inputs. For example, if the part with fixed bit data is used as the data part to test the instruction '' a ,, it can be accomplished by adding an L F S R output masking circuit. The load instruction shown in the embodiment of Fig. 1 is a specific example. LOAD R (S 1), R (D) is a load instruction, in which the memory data addressed by the memory designated by S 1 will be transferred to the register designated by D. Under this instruction, when using the data output by the random number generator (not the register data specified by S 1), because the length of the address space is limited to 24 bits, the random number generator outputs data It must also be represented by a 24-bit pattern. Figure 18 shows a random number generator for transmitting: sending random number data matching the load instruction. The random number generator includes: LFSR1902, which transmits a 32-bit virtual random number; and a combinational logic circuit, 903, which performs an 8-bit product operation. During the processing, first, when the arithmetic instruction signal 1 0 0 1 is input from the decoder 1 450, L F S R will transmit a 32-bit virtual random number pattern. Next, the higher-order octet signal in the 32-bit virtual random number pattern will be transmitted to the combinational logic circuit 903, and then the product operation of those signals whose octets are " 0〃 , And mixed with those octets that are "quoted as 0" data 1 9 0 5. Finally, the lower-order paper sizes in the data 1 905 and 32-bit virtual random number patterns are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) .2Q. ------ ---- I equipment -------- Order- (Please read the precautions on the back before filling this page) 472189 A7 B7 V. Description of the invention (27) 2 4-bit information 1 9 0 4 The data will be used as the 32-bit data matching the input command. In addition, when the probability obtained by adjusting the probability of each bit, 〇 〃,, 丄 " is used as the data for the instruction b 用以 used to confirm the data format required to execute the test option The random number generator can be constructed by designing a combination circuit using the following factors: When the logical sum of multiple output bits of the LFSR is used as its output, it will increase the power of `` 1 〃 '' Probability of occurrence; and when the logical product is used as its output, it will increase the probability of '' 0 〃. In the case where the bit pattern set is used as the data to match the instruction `` c ,, when the pattern randomly selected from the pattern set is used as the data to match the instruction `` c ,, This can be achieved by using LFSR and memory storing bit patterns, and then using LSFR output to generate memory data output addresses. FIG. 17 shows another embodiment of the random number data generator used in FIG. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------- '' installation --------- '. (Please read the precautions on the back before filling this page) These random The number data generator includes: a decoder 1 8 0 5 'it can receive the instruction information signal 1 3 4 and then determine whether the random number generator is to transmit random number data, and if it is to transmit data', it will not only be used to specify random The signal of the digital data output operation is sent to LFSR 1 8 0 7 'It also sends information for selecting random number data that matches the instruction information 1 8 0 8; LFSR 1 8 0 7' It is used to output 32-bit virtual Random number data; directive adaptation agencies I801 to 1803 'In converting data into the directive applicable to the directive information signal 1 3 4 旳 This paper size applies the Chinese National Standard (CNS) A4 specification (210 297 Gongchu) -30 -472189 " -............. B7 V. Description of the invention (28) After random number food, it is used to transmit LF s R 3 2-bit data to selector 1804; selector 18〇4, in which the suitable information is selected from the output of the instruction adaptation mechanism according to the selection information 1 8 0 8 The instruction information resource of the random number data "is then transferred to the next stage. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I ------------ install ------- order. (Please read the precautions on the back before filling this page) During the processing period ' First, 'when a random number command generator 1 2 3 inputs a command information signal 1 3 4, the decoder 1 8 0 5 determines whether the random number data generator is to transmit random number data, and if it is to transmit data' then those The information used to specify that the instruction adaptation mechanism transmits random number data corresponding to the instruction information signal will be transmitted to the selector 1804, and the decoder will transmit the random number data output instruction signal 1804 to LFSR1807. Then, the received F S R 1 8 0 7 with the instruction will transmit the virtual random number data to the instruction adaptation mechanism 1 80 1 to 1 8 0 3. After receiving the virtual random number data from LFSR, the instruction adaptation mechanism will convert the purple data into random number data adapted to the instruction, and send the random number data to the selector 1 804. In this selector, the virtual random number data adapted to the instruction information signal 1 3 4 is selected from the output virtual random number data of the instruction adaptation mechanism according to the selection information 1 8 8 and transmitted to the next stage to Random number data adapted to the instruction defined by the instruction information signal 1 3 4. The load command shown in the embodiment of FIG. 1 is a specific example. LOAD R (S 1), R (D) is a load command, where the memory data addressed by the memory designated by S 1 will be Transfer it to the register specified by D. In this instruction, 'When using a random number generator to output the paper size Peng + Guan Xuzhan (CNS) A4 specifications (210 x 297 mm). 31-472189 Α7 Β7 5. Information of the invention description (29) (non- The register data specified by S 1) is used to randomly change the corresponding address and perform instruction execution test. Because the length of the address space is limited to 24 bits, the output data of the random number generator must also be 2 4-bit pattern. Figure 19 shows an instruction adaptation mechanism for converting the L F S R 1 8 0 7 output virtual random number data into a format that matches the load instruction. This instruction adaptation mechanism includes: a combinational logic circuit 2 0 01, which performs an 8-bit multiplication operation; and a penetrating circuit 2 0 0 2, which can transmit a 2 4-bit signal without any modification 0 Figure 1 4 shows a detailed embodiment of the register file in FIG. 1. This register file contains: 3 2 registers, which have two read ports and a write port, and are used to store data. The output selectors 1 500 and 15 0 1 will test signal Change to the random number data generator output signal (instead of the register output signal), and send the random number data generator output signal to the data bus; M ISR 1 5 0 5 to receive 3 2 bit data as The response analyzer is used; and the input selector 'where the register data input by the bus 1 2 0 is transmitted to the M ISR through the test mode signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Under normal operation mode, the register written by the bus 1 2 0 is written in the register specified by the instruction. In addition, the command selection register data is also transmitted to the buses 1 1 8 and 1 1 9. In the self-test mode, the data written by the register input by bus 1 2 0 is input to the selector and transmitted to M I S 1 505. In addition, the instruction selection register data is transformed into a random number data generator 1 5 0 3 and -32- ----------- 'equipment ----- order · (Please read the back first Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (21 × 297 mm). 472189 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention (30) 1 5 0 4 output, and then the data is then transmitted to the bus 1 1 8 and 1 1 9 ° Figure 15 shows an embodiment of this structure, in which the random number data output mechanism (instead of one of the serializer 104) Or more than one storage device) transmits the signal in the case of the embodiment of FIG. 1, wherein the test mode signal is designated as a self-test mode. The sequencer is a sequence circuit, which includes: a combination circuit block 16 0 1 and “i” storage devices 16 0 4 to 16 06. When the test mode signal 1 3 3 is designated as the self-test mode, the selectors 16 0 2 and 1 6 0 3 will send the output signals 1 607 and 1 of the random number data generator 1609 (instead of the storage devices 1605 and 1606). 608. The output data of the random number data generator can be obtained by assigning two bits from the output of the LFSR shown in FIG. 8. In this embodiment, although the two storage devices are selected by the selector, the signal output structure is not limited to this, but may further include one or more storage devices. Even if the random number instruction generator has generated non-branch instructions, the structure of this embodiment can also be tested using different program counter data. FIG. 16 shows the structure of the M I S R embodiment of FIG. 1. Generally, M I S R is used as a response analyzer in the B I S T functional block, and the response analyzer can use the sum of mutually exclusive logic to transmit the signal to each bit of L F S R. In FIG. 16, 17 is a D-flip-flop ′ and the data input signal lines of 17000 to 1732 2 are 33-bit patterns. The signal required for data acquisition is connected to the input signal line u by mutually exclusive logic between the output of the D-flip-flop and the data required during the displacement ------------- -.Packing ._—— Order. (Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (21〇X 297 mm) -33- 472189 A7 B7 V. Invention description (31) The sum of the series is sent to each D-flip-flop to complete the data acquisition. According to the present invention, by providing a function that can randomly generate test instructions, a combination of a large number of instruction generation sequences can be tested. In addition, since the instruction information generated by the random number instruction generator can be used to form random number data that matches the executed instructions, its test performance can be improved and a high error detection rate can be provided. In addition, you can also use hardware such as a random number instruction generator and a random number data output mechanism to achieve fast test operations. According to the present invention, a high error detection rate and fast testing can be achieved .------------ ii ------- Order · (Please read the precautions on the back before filling this page ) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to Chinese National Standard (CNS) A4 (210 X 297 mm) _ 34-

Claims (1)

472189 δ9 1 〇6 1 ia ‘-vs BH CH [.)8472189 δ9 1 〇6 1 ia ‘-vs BH CH [.) 8 填請委Π 内容 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 1 . 一種處埋器’包含: 程式計數器’用以指定所欲執行的指令; 指令暫存器’用以儲存程式計數器所指定的指令; 暫存器,用以儲存資料; 算術邏輯單元’用以從指令暫存器中下載指令,然後 根據下載的指令來從資料儲存暫存器中讀取出資料,並且 _行算術運算以及將算術結果資料儲存於資料儲存暫存器 中;以及 隨機數指令產生器’用以根據外部輸入的測試信號來 隨機產生測試指令。 2· _如申請專利範圍第1項之處理器,其中該隨機數 指令產生器根據該測試信號來隨機產生測試指令,並將測 試指令儲存於該指令暫存器中。 3 .如申請專利範圍第1項之處理器,其中該隨機數 指令產生器根據特殊的測試指令來隨機產生測試指令,並 且產生用以傳送該資料儲存暫存器之適當資料的輸出信號 0 4 _如申請專利範圍第1至3項中任一項之處理器, 其中該隨機數指令產生器處理複數個指令,並根據預設的 條件來傳送該指令。 5 · 一種處理器,包含: 程式計數器,用以指定欲執行的指令; 暫存器檔案’其具有複數個能夠儲存資料的暫存器; 算術邏輯:單元,用以根據程式計敝器所指定的指令而 --------------i衣·-- (請先閱3t背面之注意事項再填寫本頁) · -線 本紙張尺度適用中國0家檔準(CNS)A-l規格(2ΐϋ x 297公笼) -35 - 472189 A8 B8 C8 D8 夂、申請專利範圍 從暫存器檔案中下載資料,然後執行算術運算,並且將算 術結果資料儲存於資料暫存器中; 隨機數指令產生器,用以根據外部輸入的測試信號來 隨機產生測試指令; 隨機數資料輸出機構,用以將隨機數傳送至算術邏輯 單元以執行算術運算;以及 響應分析器,用以根據該欲儲存的隨機數資料來儲存 算術結果。 6 .如申請專利範圍第5項之處理器,其中該響應分 析器根據測試信號而從程式計數器中抓取輸出信號。 7 .如申請專利範圍第1、2、3、5及6項中任一 項之處理器,其中該隨機數指令產生器具有用以儲存處理 器所執行之指令的機構,以及用以從該指令儲存機構中隨 機選擇指令的機構。 8 .如申請專利範圍第1、2、3、5及6項中任一 項之處理器,其中該隨機數指令產生器另外包含: 半指令儲存機構,用以儲存部份或全部欲執行的指令 t 補充指令資訊儲存機構,用以儲存執行半指令儲存機 構內之半指令時所需的補充資訊; 指令選擇機構,用以分別從半指令儲存機構以及補充 指令資訊儲存機構中隨機選擇半指令以及對應的補充指令 資訊;以及 用以根據所選出之半指令以及補充指令資訊來補足隨 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注咅?事項再填寫本頁) 4 ----訂---------線· 經濟部智慧財產局員工消費合作社印製 -36- 472189 .-\8 C\S ns _____ 六、申請專利範圍 機数資料的機構,以產生處理器所欲執行的指令° 9 . 一種資訊處理系統,其具有程式或資料儲存記憶 體以及連接至該記憶體的處理器以利資料之讀取與儲存’ 其中處理器另外包含: 指令暫存器,用以輸出欲執行的指令; 複數個暫存器,用以儲存資料; 位址暫存器,能夠儲存用以存取記億體所需的位址; 資料暫存器,用以儲存欲被儲存於記憶體中或欲從記 億體中所讀出的資料; 算術邏輯單元,藉此可根據指令暫存器所輸出的指令 來運算那些已被儲存於多重暫存器或資料暫存器中的資料 -------------裝--------訂. (請元閱讀背面之注音〕事項再-寫本頁) 中 器 根存 以暫 用令 , 匕曰 生存 產儲 令令 匕曰 匕曰 , 將 且 外 據 並 令 指 生 產 機 隨 來 號. 信 及 以 據中 根器 些存 那暫 收料 接資 以於 , 存 器儲 析被 分而 應後 響行 的執 內所 元令 單指 輯出 邏輸 術之 算器 於生。 設產料 令資 指的 -線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A-I規格(210 x 297公釐) -37 -Please fill in the form ii. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. Application scope of patents 1. An embedded device 'contains: a program counter' to specify the instruction to be executed; an instruction register 'to store programs Instructions specified by the counter; registers to store data; arithmetic logic unit 'to download instructions from the instruction register, and then read data from the data storage register according to the downloaded instructions, and _ Perform arithmetic operations and store arithmetic result data in a data storage register; and a random number command generator 'for randomly generating test instructions based on externally input test signals. 2 · _ If the processor is in the scope of claim 1, wherein the random number instruction generator randomly generates a test instruction according to the test signal, and stores the test instruction in the instruction register. 3. The processor according to item 1 of the patent application scope, wherein the random number instruction generator randomly generates a test instruction according to a special test instruction, and generates an output signal for transmitting appropriate data of the data storage register 0 4 _ If the processor is any one of claims 1 to 3, wherein the random number instruction generator processes a plurality of instructions and transmits the instructions according to a preset condition. 5 · A processor including: a program counter to specify the instructions to be executed; a register file 'which has a plurality of registers capable of storing data; arithmetic logic: a unit for specifying according to the program counter -------------- i clothing ... (Please read the precautions on the back of 3t before filling out this page) ) Al specification (2ΐϋ x 297 male cage) -35-472189 A8 B8 C8 D8 夂, patent application scope Download data from the temporary register file, then perform arithmetic operations, and store the arithmetic result data in the data register; A random number instruction generator for randomly generating test instructions according to an externally input test signal; a random number data output mechanism for transmitting a random number to an arithmetic logic unit to perform an arithmetic operation; and a response analyzer for performing The random number data to be stored to store the arithmetic result. 6. The processor according to item 5 of the patent application scope, wherein the response analyzer captures the output signal from the program counter according to the test signal. 7. The processor according to any one of claims 1, 2, 3, 5, and 6, wherein the random number instruction generator has a mechanism for storing instructions executed by the processor, and a mechanism for obtaining instructions from the instructions. A mechanism that randomly selects instructions from a storage mechanism. 8. The processor according to any one of claims 1, 2, 3, 5, and 6, in which the random number instruction generator further includes: a semi-instruction storage mechanism for storing some or all of the instructions to be executed The instruction t supplementary instruction information storage mechanism is used to store supplementary information required when executing the half instruction in the half instruction storage mechanism; the instruction selection mechanism is used to randomly select the half instruction from the half instruction storage mechanism and the supplementary instruction information storage mechanism, respectively. And the corresponding supplementary instruction information; and used to supplement the applicable Chinese National Standard (CNS) A4 specification (210 X 297 mm) with this paper size according to the selected half instruction and supplementary instruction information (please read the note on the back first Please fill in this page for matters) 4 ---- Order --------- Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-36- 472189 .- \ 8 C \ S ns _____ VI. Application Patent scope machine data organization to generate instructions that the processor wants to execute 9. An information processing system having program or data storage memory and a processor connected to the memory To facilitate the reading and storage of data ', the processor additionally includes: an instruction register for outputting the instruction to be executed; a plurality of registers for storing data; an address register for storing and storing Address needed to record the billion body; data register to store the data to be stored in or read from the memory; the arithmetic logic unit, which can register according to the instruction The output command is used to calculate data that has been stored in multiple registers or data registers ------------- install -------- order. Read the phonetic on the back] Matters again-write this page) The middle device is rooted with a temporary order, a survival order, a storage order, a dagger, and a foreign order. The production machine comes with a number. Letter and evidence The middle root device stores the temporary collection of materials to receive funds, and the storage device stores the analysis of the internal rules of the executive order, which should be followed by a single finger. Set the production materials and order the index -line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A-I specification (210 x 297 mm) -37-
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