JP3119383B2 - Semiconductor memory tester with data width switching function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator of a semiconductor memory test device having a data width switching function, and more particularly to a semiconductor memory test device which facilitates generation of an expected value pattern in a test of a semiconductor memory having a data width switching function. Related to a pattern generator.

[0002]

2. Description of the Related Art As a semiconductor memory having a data width switching function, a data width can be switched from a word (16 bits) to a byte (8 bits) by changing a signal level applied to a specific input pin of the semiconductor memory. There is a mask ROM that can be used. A conventional example of a method of testing a ROM of this type by a semiconductor memory test apparatus will be described with reference to FIG.

In FIG. 1, reference numeral 10 denotes a timing generator,
20 is a pattern generator. An address signal and a data signal are sent from the pattern generator 20 to the waveform shaper 30, whereby the waveform generated by the waveform shaper 30 is subjected to a mask R to be tested via the driver 60.
Input to OM50. The response output to the input of the mask ROM 50 is supplied to the logical comparator 40, while the logical comparator 40 is supplied with the expected value data generated by the pattern generator 20, where the expected value and the value of the mask ROM 50 are stored. A test result of the mask ROM 50 can be obtained by a logical comparison between a response to an input and an output. The internal configuration of the pattern generator 20 includes an address generator 22, a data generator 23, and an expected value data memory 24.
1 is sequence controlled. Here, the internal structure of the expected value data memory unit 24 is as shown in FIG. 2 and includes a memory unit 241 and a memory configuration control unit 242. Expected value data for the mask ROM 50 is written in advance from the data write terminal to the memory unit 241, which is accessed and read by the same address as the mask ROM 50 to be tested, and supplied to the logical comparator 40. It is.

[0004] The memory configuration control unit 242 includes a memory unit 241.
If the memory under test has the 8 / 16-bit switching function, the memory section 241 is changed to the 16-bit configuration if the memory under test has the 16-bit switching function, and if the memory under test has the 16 / 32-bit switching function. 3 memory units 241
This is for changing and setting to a 2-bit configuration, whereby the expected value data memory section 24 can output data with the same data width as the mask ROM 50 to be tested. The memory configuration inside the memory unit 241 is as illustrated in FIG.

[0005]

The pattern generator 20 of the semiconductor memory test device having the data width switching function as described above is used for testing the ROM having the data width switching function.
First, the memory configuration of the expected value data memory unit 24 is set to the same memory configuration as one of the memory configurations to be tested of one of the ROMs to be tested, and then the test is performed.
Here, there may be a case where it is desired to perform a further test on the other memory configuration. In such a case, the test is terminated once, and the memory configuration of the expected value data memory unit 24 is reset to another memory configuration to be tested.
Further testing had to be performed. The memory configuration of the expected value data memory section 24 could not be changed during the test. This is not favorable for test efficiency.

An object of the present invention is to provide a semiconductor memory test device with a data width switching function which has solved the above-mentioned problems.

[0007]

An address generator 22, a data generator 23, an expected value data memory unit 24, a control signal generator 25, and a sequence control unit for controlling the sequence of these units are provided with a timing generator 10. 21 and a waveform shaper 30. A control signal, an address signal, and an expected value data signal generated in the pattern generator 20 are sent to the waveform shaper 30. A logic comparator 40 for inputting the waveform generated at 30 to a semiconductor memory 50 with a data width switching function to be tested and comparing a response output to the input of the semiconductor memory with a data width switching function with an expected value data signal. In a semiconductor memory test apparatus with a data width switching function provided, an expected value data memory unit 2 241 to which expected value data is written, and outputs data read from the memory 241 by halving the data width by the control signal generated by the control signal generator 25 and the least significant bit of the input address. And a data selector unit 243 having the above configuration.

[0008]

An embodiment of the present invention will be described with reference to FIGS. 4 and 5, FIG. 1 and FIG.
The same reference numerals indicate the same parts. A feature of the present invention is that, in the semiconductor memory test apparatus having the data width switching function as described above, the pattern generator 20 is provided with the control signal generator 25 and the expected value data memory 24 is Selector section 243
Is controlled by a control signal generated by the control signal generator 25, for example, “0” or “1”. That is, the data selector 243 selects and outputs the expected value data read from the memory 241. This selection is performed by a control signal generated by the control signal generator 25 and the least significant bit A- _{1 of the} input address. The control signal is generated by controlling the sequence of the control signal generator 25 in the pattern generator 20 by the sequence controller 21. These will be specifically described below.

FIG. 6 is a diagram showing a state of output data of the expected value data memory unit 24 (a case where the memory configuration is 16 bits is illustrated). FIG. 6A shows a normal state, that is, a state in which the control signal generator 25 generates the control signal = 0. In this case, the data selector 243
Outputs the data read from the memory unit 241 as it is. In the expected value data memory section 24, the address A- ₁ is ignored.

FIG. 6B shows a memory configuration change state, that is, a case where the control signal = 1 is generated from the control signal generator 25. In this case, the data selector 243 divides the data read from the memory 241 into upper 8 bits and lower 8 bits and outputs the data. As for the method of dividing into two, the least significant bit 0 or 1 is added to the input address, and A
_{When -1} = 0, the lower bit D7-0 is output, and when A- ₁ = 1, the upper bit D8-15 is output.

A response output to the input of the mask ROM 50 is supplied to the logical comparator 40, and these outputs, that is, expected value data are supplied to the logical comparator 40, where the expected value and the response output to the input of the mask ROM 50 are compared. The test result of the mask ROM 50 can be obtained by logical comparison between the two. Although the switching of the memory configuration between 16 bits and 8 bits has been exemplified, this can be extended and applied to the case where the switching of the memory configuration is between 64 bits and 32 bits. In addition, the least significant bit of the address applied to the data selector 243 is not 1 bit as described above but 2 bits, and the control signal generated by the control signal generator 25 is also 2 bits. 7
Can be controlled as shown in FIG.

[0012]

As described above, the semiconductor memory test apparatus with the data width switching function of the present invention can change the control signals "0" and "1" even during the test. Therefore, even if the data width of the mask ROM 50 is changed during the execution of the test, the expected value data of the data width corresponding to the change can be generated. Therefore, even if it is desired to perform a further test on the other memory configuration, the test must be interrupted in order to reset the memory configuration of the expected value data memory unit 24 to another memory configuration to be tested. There is no such inconvenience as not to be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional example of a semiconductor memory test device with a data width switching function.

FIG. 2 is a diagram showing a conventional example of an expected value data memory unit.

FIG. 3 is a diagram showing a memory configuration of a memory unit.

FIG. 4 is a diagram showing a semiconductor memory test device with a data width switching function according to the present invention.

FIG. 5 is a diagram showing an expected value data memory unit according to the present invention.

FIG. 6 is a diagram showing expected value output data of an expected value data memory unit according to the present invention.

FIG. 7 is a diagram showing another example of expected value output data.

[Explanation of symbols]

 Reference Signs List 10 timing generator 20 pattern generator 21 sequence control unit 22 address generation unit 23 data generation unit 24 expected value data memory unit 25 control signal generation unit 30 waveform shaper 40 logical comparator 50 semiconductor memory with data width switching function 241 memory Section 243 Data selector section

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G01R 31/28 G01R 31/3183 G11C 29/00 651 G11C 29/00 657

Claims (1)

(57) [Claims] 1. A pattern generator comprising a timing generator, an address generator, a data generator, an expected value data memory, a control signal generator, and a sequence controller for controlling these in sequence. A waveform shaper for sending a control signal, an address signal and an expected value data signal generated in the pattern generator to the waveform shaper, thereby switching a data width to be tested on the waveform generated in the waveform shaper; A logic comparator for inputting to the semiconductor memory with the function and comparing an expected output data signal with a response output to the input of the semiconductor memory with the data width switching function, wherein the expected value data memory section is used to write the expected value data; And a control signal generated by the control signal generator and an input address. A data selector unit having a configuration for halving the data width by the least significant bit of the data and outputting the data.