JPH0836035A - Test pattern generating unit - Google Patents

Abstract

PURPOSE:To provide a test pattern generating unit, which can easily generate an expected value in relation to any initial value in the case of testing a test memory with writing-enable/disable control per bit. CONSTITUTION:The test pattern generating unit is provided with an XOR control unit 131 for generating the control signal on the basis of the signal from an instruction memory 112, an AND gate 123, which receives the output signal of the XOR control unit 131 at one input terminal thereof, and which receives the output reversing signal of a data generating unit B15 at the other input terminal thereof, and an exclusive OR gate 121, which receives the output of the AND gate 123 at one input terminal thereof and which receives the output signal of a data generating unit A14 at the other input terminal thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator for testing a device under test, and more particularly to a test pattern generator which facilitates generation of expected value data which tends to be complicated.

[0002]

2. Description of the Related Art FIG. 2 shows an example of the configuration of a conventional semiconductor test apparatus for testing the quality of a device under test. FIG. 2 shows an example in which the device under test is a memory. A data signal is supplied from the data generator A14 for the memory under test.
A mask data signal for prohibiting the writing of the data signal to the memory under test is supplied from the data generator B15. Then, the waveform shaper 2 shapes these signals and supplies them to the memory under test 3 for writing. Also,
The address signal is supplied from the address generator 13.
Each of the above generators generates data according to an instruction from the instruction memory 12. The instruction memory 12 is controlled by the program counter 11. As described above, the test pattern generator 10 is configured by each generator, the instruction memory, and the program counter.

Next, the data read from the memory under test 3 is compared with the expected value data output from the data generator A14 in the logical comparator 4. Then, the quality of the memory under test 3 is determined by whether or not it matches the written content.

Generally, in semiconductor memories, there are devices capable of write enable / disable control for each data bit. In writing to such a semiconductor memory, write mask data having the same number of bits as the write data is applied together with write data, and data rewriting is performed only for the bit having write mask data of "1". FIG. 3 shows an example of writing to the semiconductor memory when the bit width is 4. In this case, the write mask data is #E, and the write data is written in the bits "1", "2", and "3". Then, in the bit “0”, the data before writing is stored as it is.

As described above, many test pattern generators have two systems of data generators (14, 15) in order to test a semiconductor memory capable of write enable / disable control for each data bit. There is. At the time of writing, one is used for writing and the other is used for generating mask data. At the time of reading, either one is used to generate the expected value. Which one is used can be arbitrarily determined and is connected to the logical comparator 4.

Next, FIG. 4 shows an example of conventional operation. FIG. 4 shows the case where the initialization data from the data generator A is # 3. In the initialization step, all bits are write enabled, and the mask data from the data generator B is #F.
Is. As a result, # 3 is written as initial data in the memory under test.

Next, in the write step, the write data from the data generator A is set to #C. This corresponds to the inverted data of the initial value (# 3). The write mask data from the data generator B is #E.
As a result, "0" is written to bit 1 in the memory under test,
“1” is written in bit 2 and “1” is written in bit 3. Then, since the initial data "1" remains in the bit 0 whose mask data is "0", #D becomes the data of the memory under test.

In the read step, it is necessary to generate the same data as the data #D of the memory under test as expected value data from the data generator A. That is,
It is necessary to generate the expected value in consideration of the write data and the write mask data. As described above, generation of expected value data is generally complicated, which makes it difficult to test the memory under test with write enable / disable control for each bit.

In the test of the memory under test, which generally does not have the write enable / disable control for each bit,
Since it is possible to generate the same data as at the time of writing at the time of reading and use it as the expected value, the test can be performed easily. Similarly, even in the case of the memory under test with write enable / disable control for each bit, if the initial value is all bits 0 or all bits 1, the expected value data generated in the reading step is used in the writing step. Data generator B
The expected value data can be easily obtained by using the same data as the mask data generated in step 1 or its inverted data. However, except for such a special case, it is generally complicated to generate the expected value of the memory under test with write enable / disable control for each bit.

[0010]

In recent years, the data bit width of a memory under test with write enable / disable control for each bit tends to be wide, and the data bit width is 16 or 32 from the conventional 4 or 8 bits. Things are appearing. As described above, as the data bit width becomes wider, the initial value to be written and the mask data at the writing step are diversified. In that case, the generation of expected value data in the reading step becomes more complicated and difficult.

The object of the invention is to eliminate these drawbacks,
When testing the memory under test with write enable / disable control for each bit, it was difficult to generate the expected value in tests other than when the initial value was all bits 0 or all bits 1, but any initial value It is an object of the present invention to provide a test pattern generator that can easily generate an expected value.

[0012]

In a test pattern generator 10 for generating expected value data for testing a device under test 3, an XOR controller 131 for generating a control signal in response to a signal from an instruction memory 112. To provide. Then, the output signal of the XOR controller 131 is received at one input terminal, and the data generator B15 is received at the other input terminal.
An AND gate 123 is provided for receiving the output inversion signal of.
Then, an exclusive OR gate 121 that receives the output of the AND gate 123 at one input terminal and receives the output signal of the data generator A14 at the other input terminal constitutes a test pattern generator.

[0013]

According to the present invention, the output data of the XOR controller is "0" in the initialization and writing steps, but is set to "1" in the reading step. Therefore, the AND gate 123 is opened. Next, data generator B
, The output of the AND gate is "1", so that the signal passing through the exclusive OR gate 121, that is, the output signal of the data generator A is inverted. If the output data of the data generator B is "1", the output of the AND gate is "1".
The signal passing through the exclusive OR gate 121, that is, the output signal of the data generator A is not inverted.
In this way, the expected value is generated by generating the same data as the data generated at the time of writing at the time of reading.

[0014]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a test pattern generator showing an embodiment of the present invention. As shown in FIG. 1, an exclusive OR gate 121 is provided and connected after the data generator A14. An AND gate 123 is provided and connected to the other input terminal of the exclusive OR gate 121. An XOR controller 131 is provided and connected to one input terminal of the AND gate 123. The XOR controller 131 is
Settings are made from the instruction memory 112.
The output of the data generator B15 is connected to the other input terminal of the AND gate 123 via the inverter 122.

With this configuration, the XOR is generated by the control signal from the instruction memory 112.
When "0" is output from the controller 131, the output signal from the data generator A14 is converted into the waveform shaper 2 as usual.
Supply to. Also, it is supplied to the logical comparator 4 as expected value data. When "1" is output from the XOR controller 131, the signal passing through the exclusive OR gate 121 is inverted according to the output data of the data generator B15, or as an expected value without being inverted, The operation of supplying to the logical comparator 4 is performed.

FIG. 5 shows an operation example according to the present invention. The bit width is 4, and the initial value from the data generator A is # 3. The write data in the write step is #C, which corresponds to the inverted data of the initial value. The mask data in the writing step is #E, which means that only the least significant bit is write-protected. The program counter advances from 0 → 1 → 2, and in the reading step,
The following operations are performed.

The output data of the XOR controller is "0" in the initial value and the writing step, but is set to "1" in the reading step. Therefore, the AND gate 123 is opened. Next, when the output data of the data generator B is "0", the output of the AND gate is "
Therefore, the signal passing through the exclusive OR gate 121, that is, the output signal of the data generator A is inverted. If the output data of the data generator B is "1", The output of the gate becomes "0", and the signal passing through the exclusive OR gate 121, that is, the output signal of the data generator A is not inverted.

In FIG. 5, the output data of the data generator A is #C, and the 0 bit of the data generator B is "0".
Therefore, it is inverted when passing through the exclusive OR gate 121, and eventually #D is generated as an expected value. This expected value #
D matches the content #D of the memory under test.

As described above, it can be seen that the expected value can be generated by generating the same data as the data generated at the time of writing at the time of reading. That is, when the write data is the inverted data of the initial value, the output bit of the XOR control unit 131 is set to “0” at the time of writing and the output bit of the XOR control unit 131 is set to “0” at the time of reading as in the present configuration. By setting 1 ", it is possible to easily generate the expected value by generating the same data as at the time of writing. Therefore, according to the present invention, it is possible to easily generate an expected value with respect to an arbitrary initial value. Further, the present invention is based on the idea that the expected value is inverted when only the write-protected bits are read at the time of writing. Therefore, the present invention can be easily applied even if the bit width becomes wide and the number of write-protected bits increases.

[0021]

Since the present invention is configured as described above, it has the following effects. A test pattern generator capable of easily generating an expected value with respect to an arbitrary initial value when testing a memory under test with write enable / disable control for each bit was provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a test pattern generator showing an embodiment of the present invention.

FIG. 2 shows a configuration example of a conventional semiconductor test apparatus for testing the quality of a device under test.

FIG. 3 shows an example of writing to a semiconductor memory when the bit width is 4.

FIG. 4 shows a conventional operation example.

FIG. 5 shows an example of operation according to the present invention.

[Explanation of symbols]

 2 waveform shaper 3 memory under test 4 logical comparator 10 test pattern generator 11 program counter 12, 112 instruction memory 13 address generator 14 data generator A 15 data generator B 121 exclusive OR gate 122 inverter 123 AND gate 131 XOR controller

Claims (2)

[Claims] 1. A test pattern generator (1) for generating expected value data for testing a device under test (3).
0), an XOR controller (131) that generates a control signal by a signal from the instruction memory (112) is provided, and the data generator A (14) receives the output signal of the XOR controller (131). An exclusive OR gate (121) for performing an exclusive OR of the data signal generated in 1) and the data signal generated in the data generator B (15) is provided, and the test pattern is provided. Generator. 2. A test pattern generator (1) for generating expected value data for testing a device under test (3).
0), an XOR controller (131) that generates a control signal by a signal from the instruction memory (112) is provided, and the output signal of the XOR controller (131) is received at one input terminal and the other input terminal. Is provided with an AND gate (123) for receiving an inverted signal of the output of the data generator B (15), the output of the AND gate (123) is received at one input terminal, and the other input terminal of the data generator A (14) is received. A test pattern generator comprising an exclusive OR gate (121) for receiving an output signal and having the above-mentioned configuration.