JPS62266474A - Dynamic burn-in tester - Google Patents

Abstract

PURPOSE:To achieve a highly reliable test, by controlling the synchronous relationship between the operation of a logic integrated circuit (MPU) and the operation of a master MPU with a dynamic burn-in input generator to enable the operation of the MPU as desired. CONSTITUTION:Outside a burn-in unit 10 containing a plurality of MPUs 1 to be tested, one master MPU1' identical to the MPU1 is operated according to a program for dynamic burn-in tests to generate a dynamic burn-in input waveform. A dynamic burn-in input generator 20 is provided to supply this input waveform into the MPUs 1 in the unit 10 in common while controlling the synchronous relationship between the operation of the respective MPUs 1 and the operation of the MPU1'. This permits the unit 20 to supply the dynamic burn-in input waveform so that the MPUs 1 in the unit 10 will be operated as the master MPU1' following the program for dynamic burn-in after being put to the initial state the same as that of the master MPU1' outside the unit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a dynamic burn-in test device for logic integrated circuits, and more particularly to a dynamic burn-in input generation device.

(Prior Art) Conventionally, logic integrated circuits, such as microprocessors (
When performing a burn-in test for an MPU (MPU), a static method or a clocked method has been adopted. In the static burn-in test described above, as shown in Figure 2, burn-in is performed without applying a clock signal with the power supply voltages VC and C applied to each of the MPUs installed in the burn-in device. and klPU
1... Since each internal circuit is fixed in a certain state, there are many parts to which voltage stress is not applied.

In addition, the clocked type bar-twin test is performed using MPU 1 installed in a burn-in device as shown in FIG.
Since the clock signal is input with the power supply voltage Vcc applied to each of them, the internal circuits of the MPU 1 can be operated to some extent. However, it is not possible to perform arbitrary operations such as reading or writing data by specifying a specific address between the MPU j and an external memory integrated circuit (not shown). MPU 1...The application rate of each voltage stress is insufficient.

(Problems to be Solved by the Invention) As described above, the present invention performs a burn-in test only in a state where the logic integrated circuit that is the target of the burn-in test is not allowed to perform arbitrary operations and the rate of application of voltage stress is low. This was done to solve the problem of not being able to do the following.
It is an object of the present invention to provide a dynamic burn-in test device that can perform any of the above operations and easily generate a dynamic burn-in input waveform for the integrated circuit.

[Configuration of the Invention (Means for Solving the Problems)] The Guinemic burn-in test device of the present invention has the above-mentioned external burn-in device in which a plurality of logic integrated circuits to be subjected to a dynamic burn-in test are installed. A dynamic burn-in input waveform is generated by operating one master integrated circuit, which is the same as the integrated circuit, according to a dynamic burn-in test program, and this input waveform is commonly supplied to each integrated circuit in the burn-in apparatus, and the above-mentioned Guinemic burn-in 7 for controlling the synchronization relationship between the operation of each integrated circuit and the operation of the master integrated circuit.
It is characterized by comprising an input generation device.

(Function) After each integrated circuit in the burn-in device is put into the same initial state as the master integrated circuit outside the burn-in device by the dynamic burn-in input generator, the operation is the same as that of the master integrated circuit according to the dynamic burn-in test program. Since it is possible to supply a dynamic burn-in input waveform to make the logic system operate as desired, it is possible to cause the logic integrated circuit that is the subject of the burn-in test to perform arbitrary operations and increase the voltage stress application rate sufficiently to ensure reliability. It becomes possible to perform a high dynamic burn-in test. Moreover, operating the master integrated circuit to generate a dynamic burn-in input waveform is easily possible by using a memory integrated circuit that stores appropriate programs and data, and by changing this program and data. It is possible to easily change the dynamic burn-in input waveform.

(Embodiment) An embodiment of the present invention will be described in detail below with reference to one drawing. In FIG. 1, 1o is a known-in device, 11.
. . . are personal/ports inserted into the above-mentioned bar/in device IQ, each of which is a plurality of logic integrated circuits (in this example, fl MPU
1) is installed. Each MPU 1 has Vc
e Power terminals are connected to each other, ground (GND) terminals are connected to each other, data input terminals are connected to each other, control terminals (reset input, etc.) are connected to each other, and clock input terminals are connected to each other.

On the other hand, numeral 20 is a dynamic burn-in input generator installed outside the burn-in device 1o for commonly providing input signals for dynamic burn-in testing to each MPU I. In this input generation device 20,
One master identical to each MPU l! vlPU
A microphone/computer section 2 using the microcomputer section 1', a clock generation circuit 22 for supplying the ztvc clock signal, and a data input of the master MPU 1' from the microcomputer section 21 and reset. An output buffer circuit 23 to which signals are separately given and commonly supplies these signals to each MPU 1; It includes a timing control circuit 24 that adjusts the relationship between the signal supply timing from the circuit 23 to each MPU 1 and the operation timing of the master MPU 1'.

The microcomputer section 21 is the master MP
U 1' and this master MPU 1' to each of the MPUs.
Data read/write is performed between the master MPU 1' and the ROM (read-only memory) 25 in which the program and fixed data for operating according to the dynamic burn-in test program for 1' are stored.
It has a RAM (random access memory) 26 for writing and other integrated circuits for necessary peripheral circuits. In addition, ROM 25 is installed in the master MPU 1'.
data from, data from pasted M26, master MPU
1' Each data input line into which its own output data etc. is input is connected to the output/? It is also wired to the 7-a circuit 23. Further, the clock signal output from the clock generation circuit 22 is also supplied to each MPU 1.

Next, the operation of the dynamic burn-in test apparatus will be explained. The timing control circuit 24 first controls the master MP
A reset signal is given to U1' to initialize it, and a reset signal is given to each MPU1 through the output buffer circuit 23 to initialize it, and then the above reset signal is given at a constant timing in synchronization with the black and red signals. Release and master MP
U 1' and each MPU 1 are synchronized to start their respective operations. Master MPU 1' is ROM 25
The operation is executed according to the dynamic burn-in test program stored in the master M.
Since the data input to PU 1' is also input to each MPU l via the output buffer circuit 23, each MPU
1 performs the same operation as the master MPU 1'. Therefore, by appropriately composing the above program, it becomes possible to cause each MPU 1 to perform arbitrary operations, and it is possible to greatly improve the voltage stress application rate, thereby significantly increasing the perfining effect. be able to. Furthermore, by simply storing a dynamic burn-in test program or input signal waveform generation data in a memory integrated circuit, the master MPU 1' can automatically generate a dynamic burn-in input waveform. Since it is not necessary to use a minicon beater for generating dynamic burn-in input signals, it is possible to realize a dynamic burn-in test device system at low cost. Additionally, if you want to change the pattern of the dynamic burn-in input signal waveform, you can do so very easily by simply changing the data written in advance to the memory integrated circuit (or replacing the memory integrated circuit with different stored data). It is possible.

In addition, as described above, each MPU 1 is connected to the master MPU 1
′, so each M
It is also possible to measure dynamic characteristics by comparing each output data of PU 1 with an expected output value.

Furthermore, since the dynamic burn-in input generator 20 is provided outside the parfin device 1.10, this device itself is not burn-in, making it possible to perform highly reliable dynamic burn-in tests. Become.

In addition, burn-in tests are not limited to the above-mentioned MPU, but also other logic integrated circuits (integrated circuits for input/output circuits,
Custom LS1. For gate arrays, etc.), the same master integrated circuit as the integrated circuit under test is put into dynamic operation outside the burn-in equipment, and the dynamic burn-in input waveform generated is supplied to each integrated circuit under test in the perfin equipment. Bye. In this case, it is sufficient to start the operations of the master integrated circuit and the integrated circuit under test from the same initial state, but depending on the type of integrated circuit, input of an external clock signal may not be necessary.

[Effects of the Invention] As described above, according to the dynamic burn-in test device of the present invention, it is possible to cause a logic system integrated circuit such as an MPU to perform any desired operation, and the application rate of voltage stress is sufficiently large to ensure reliability. A high dynamic burn-in test can be performed. Moreover, it is easy to generate and change the dynamic burn-in input waveform, and since the input waveform generator is provided outside the burn-in device, it does not undergo burn-in itself, and therefore its reliability is high.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the dynamic burn-in test device of the present invention, FIG. 2 is a configuration explanatory diagram showing a conventional static burn-in test device, and FIG. 3 is a configuration explanatory diagram showing a conventional clocked burn-in test device. FIG. No... MPU to be burned-in, 1'... Master MPU, 10... Burn-in device, 20... Dynamic burn-in input generator, 21... Microcomputer section, 22... Clock generation circuit , 23
...Output 2 hehehe...ROM, 26...RAM. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3

Claims (2)

[Claims] (1) Outside the burn-in equipment containing multiple logic integrated circuits that are subject to dynamic burn-in testing,
A dynamic burn-in input waveform is generated by operating one master integrated circuit same as the above-mentioned integrated circuit according to a dynamic burn-in test program, and this input waveform is commonly supplied to each integrated circuit in the burn-in apparatus, and each of the above-mentioned 1. A dynamic burn-in test device comprising a dynamic burn-in input generator for controlling the synchronization between the operation of an integrated circuit and the operation of the master integrated circuit. (2) The logic system integrated circuit is a microprocessor, and a memory integrated circuit for storing the dynamic burn-in test program and required data is connected to a master microprocessor and each microprocessor in the burn-in device. The processor is reset at the same time, and the data input of the master microprocessor is branched and supplied to each microprocessor in the burn-in device through an output buffer circuit. Dynamic burn-in test equipment according to scope 1.