JPS60203870A - Test pattern forming circuit - Google Patents

Abstract

PURPOSE:To execute copying processing at a high speed by providing the titled circuit with a control part, input pattern storage part, output pattern storage part, address latch, expected value registor, address selector, expected value selector, etc. CONSTITUTION:The control part 11 for controlling the input pattern storage part 12 and the output pattern storage part 13 and the address latch 14 for latching address data outputted from the control part 11 are connected. In addition, the address selector 16 for outputting address data in the address latch 14 at a copy mode time and that on an address bus l outputted from the control part 11 at a normal mode time and the expected value selector 17 for outputting an expected value pattern stored in the expected value register 15 at the copy mode and that stored in the output pattern storage part 13 at the normal mode are connected. Thus, the copying processing can be performed efficiently.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a test pattern generation circuit having an input cover pattern storage unit and an output cover pattern storage unit, which can efficiently write a copy result to the output cover pattern storage unit. This is how it was done.

[Prior art and problems]

FIG. 1 is a block diagram of a conventional test pattern generation circuit, in which 1 is a control section, 2 is a pattern generator, 3 is an input cover pattern section, 4 is an output cover pattern storage section, and 5 is a block diagram of a conventional test pattern generation circuit. 1, numeral 6 indicates a waveform shaping circuit, numeral 6 indicates a device under test, numeral 7 indicates a comparison/judgment circuit, and numeral 8 indicates a write control circuit. The control unit 1 controls writing of data to the pattern generator 2 and reading of data from the pattern generator 2. The pattern generator 2 includes an input pattern storage section 3 and an output pattern storage section 4. The waveform shaping circuit 5 shapes the waveform of the input cover pattern read from the input cover pattern storage section 3. The device under test 6 is an LSI logic circuit. The comparison/determination circuit 7 compares and determines the output data from the device under test 6 and the expected value pattern read from the output pattern storage section 4 on a bit-by-bit basis. Fail
l) Output the signal. This comparison/judgment circuit 7 may be considered to be composed of a Rubit exclusive OR circuit. The write control circuit 8 operates in the copy dispute mode,
If the fail signal is logic "1", write the comparison judgment result to the output pattern storage section 4. When performing copy processing, first write the input pattern pattern to the input pattern storage section 3, then write the input pattern pattern to the output pattern storage section 4. An expected value pattern of all 0s (or all 1s) is written in .Next, data is read from the input cover pattern storage section 3 and the output cover pattern storage section 4.The input cover pattern read from address 6 of the input cover pattern storage section 3 is The expected value pattern 4 which is inputted to the device under test 6 via the waveform shaping circuit 5 and read from the address t of the output pattern storage section 4 is input to the comparison judgment circuit 7. The output data of the device under test 6 and the expected value pattern are compared at the timing of When the pattern is all 1, an inverted version of this) is written into the output pattern storage section 4.

The write address at this time is address i. When this process is completed, the address number of pattern generator 2 +
The input pattern and expected value pattern are read from 1 and the same process is repeated.

In the conventional test pattern generation circuit shown in Fig. 1,
When performing copy processing, the input pattern and expected value pattern are read from address i of the pattern generator 2, and the copy result (comparison and judgment result or the inverted version thereof) is written to address i of the output pattern storage section 4, and then Since the copy process for address i+1 was performed later, it was not possible to perform the copy process at high speed.

[Purpose of the invention]

The present invention is based on the above consideration, and an object of the present invention is to provide a test pattern generation circuit that can perform copy processing at high speed.

[Structure of the invention]

Therefore, the test pattern generation circuit of the present invention includes an input cover pattern storage section, an output cover pattern storage section, a waveform shaping circuit that shapes the output from the input cover pattern storage section, and an output of the waveform shaping circuit that is inputted. a device under test;
A comparison judgment circuit that compares and judges the output signal from the device under test with expected value data at a specified timing, and an expected value register, and when in copy mode, sends the expected value data of the expected value register to the comparison judgment circuit. In the copy mode, an expected value selector sends the expected value data read from the output pattern storage section to the comparison judgment circuit, and in the copy mode, if a fail signal is output from the comparison judgment circuit, the copy result is sent to the output pattern storage section. A write control circuit for writing to the storage section, a control section for generating address data and read signals for the human cover one turn storage section and the output cover turn storage section, and latching the address data from the control section to the output cover turn storage section. address latch.

and an address selector that sends the address data of the address latch to the output cover pattern storage section in the copy mode, and immediately sends the address data output from the control section to the output cover pattern storage section in the normal mode. This is a characteristic feature.

[Embodiments of the invention]

FIG. 2 is a block diagram of one embodiment of the present invention. In FIG. 2, 11 is a control section, 12 is an input cover pattern storage section,
13 is an output pattern storage section, 14 is an address latch,
15 is an expected value register, 16 is an address selector, 1
7 indicates the expected value and selector', respectively. In addition,
The same reference numerals as in FIG. 1 indicate the same parts.

The control unit 11 controls the input cover pattern storage unit 12 and the output cover pattern storage unit 13.

The hardcover turn storage section 12 and the hard turn storage section 13 are independent memories. address·
The latch 14 latches the address data output from the control section 11. The address selector 16 is
In the copy mode, the address data of the address latch 14 is output, and in the normal mode, the address data on the address bus currently output by the control unit 11 is output.

Expected value register 5 contains all O's (or all 1's).
) is stored. The expected value selector 17 outputs the expected value pattern stored in the expected value register 15 in the copy mode, and outputs the expected value pattern sent from the output pattern storage section 13 in the normal mode.

The operation of the embodiment shown in FIG. 2 in the copy mode will be explained with reference to FIG. In #1 cycle.

The control section 11 outputs the address number and also provides a read command signal R to the storage section 12.13. The input cover pattern read from the address number in the input cover pattern storage section 12 is applied to the device under test 6 via the waveform shaping circuit 5. In addition,
#t psi, address latch 14 is at address i
-1 is held, and the address selector 16 outputs the right 90 inputs, so the address i -1 is given to the output pattern storage section 13. The comparison/determination circuit 7 compares and determines the output data based on the input pattern of the address i-1 and the expected value pattern of the expected value register 15 at a prescribed timing, and if the two do not match, outputs a fail signal of logic "1". Output. When the fail signal becomes logic "1", the write control circuit 8 supplies the copy result to the output pattern storage section 13 and provides the write instruction signal W. This copy result is stored at address i in the output pattern storage section 13.
-1 is written into 1. Near the end of the #i cycle, the address t is latched into the address e latch 14, and the address #+
At one cycle, the control unit 11 outputs the address i+1, and then outputs the read command signal R. Similar operations are performed thereafter. Note that during the copy operation, the expected value pattern read from the output pattern storage section 13 is not affected in any way by the copy process.

In the normal mode, address selector 16 and expected value selector 17 each output their left inputs, and write control circuit 8 does not perform any operation.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, copy processing can be performed efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional test pattern generation circuit, FIG. 2 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a diagram for explaining copy processing of the present invention. 5... Waveform shaping circuit, 6... Device under test, 7...
Comparison/judgment circuit, 8... Write control circuit, 11... Control section. 12... Input cover pattern storage section, 13... Output pattern storage section, 14... Address setting latch, 15... Expected value register, 16... Address selector, 17.
...Expected value selector. Patent applicant: Usatsuk Electronic Industry Co., Ltd. Patent attorney Higashitani

Claims (1)

[Claims] an input cover pattern storage section, an output cover pattern storage section, a waveform shaping circuit that shapes the waveform of the output from the input cover pattern storage section, a device under test to which the output of the waveform shaping circuit is input, and a device under test to which the output from the device under test is input. A comparison judgment circuit that compares and judges the output reliability with expected value data at a specified timing, an expected value register, and when in copy mode, the expected value data of the above expected register is sent to the above comparison judgment circuit, and when in normal mode, the above output pattern is stored. an expected value selector that sends the expected value data read from the unit to the comparison judgment circuit, and a write that writes the copy result to the output pattern storage unit if a fail signal is output from the comparison judgment circuit in the copy mode. a control circuit, a control section that generates address data and read signals for the input cover turn storage section and output cover turn storage section, an address latch that latches address data from the control section to the output cover turn storage section, and a copy. - An address selector is provided which sends the address/data of the above address to the output pattern storage section in the normal mode, and immediately sends the address/data output from the control section to the output pattern storage section in the normal mode. A test pattern generation circuit featuring: