JPS62223895A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate expensive PROM writer on programming and verifying of an integrated PROM by internally providing an address signal generating circuit, a timing signal generating circuit, a writing pulse generating circuit and a data comparison circuit. CONSTITUTION:The device consists of the address signal generating circuit 2, the PROM 3, the timing signal generating circuit 4, the writing pulse generating circuit 5, the data comparator 6, an address bus 7, a data bus 8, a memory control terminal 9, an input terminal 10, an output terminal 11 and a verify output terminal 12. When the input terminal 10 goes to an active level at the timing of T1, the output terminal 11 is brought into the active level ('1') at the timing of T2 and the operating for programming and verifying is informed externally. The programming and verifying is completed by repeatedly addressing from T3 to T11 on all the addresses of the PROM 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device 1d in which various electronic circuits are mounted on a single chip, and particularly to one incorporating a rewritable PROM.

[Conventional technology]

Conventionally, in a semiconductor device with a built-in PROM, the gP
Programming and verifying the ROM required a dedicated device called a PROM writer. FIG. 2 shows a conventional example. The PROM writer 21 includes a storage device 22 that stores write data, an address signal generation circuit 23 that specifies a write and helifix address, a write pulse generation circuit 24 that generates a write pulse 28 (PGM), and a data comparison circuit that compares data. 35, a control signal 29 (RD) that controls the storage device 22, a control signal 30 that controls the address signal generation circuit 23, a control signal 31 that controls the write pulse generation circuit 24, and a PROM 3.
A control signal 32 (VPP) for supplying power to the semiconductor device 33 incorporating 4, a control signal 36 for controlling the data comparison circuit 35, a control signal 37 (OE) for reading data from the PROM 34, and the control signals 29, 30. ,31.3
Timing signal generation circuit 25 that generates 2, 36, 37
A semiconductor device 33 containing a PROM 34 is connected as shown in FIG. 2 to program and verify the PROM 34. The procedure is described below.

First, the control signal 32 from the timing signal generation circuit 25
(VPP) supplies power to the semiconductor device 33. ? from the timing signal generation circuit 25? 5! In response to the master signal 30, a predetermined address is output from the address signal generation circuit 23 to the address bus 26. In response to the control signal 29 (RD) from the timing signal generation circuit 25, data at the address specified by the address bus 26 is read out from the memory device 22 and output to the data bus 27.
"L, b. Next, the write pulse generation circuit 24 operates according to the split/discount signal 31 from the timing No. 16 generation circuit 25.

Write pulse 2 from write pulse generation circuit 24
P (PGM) built into the semiconductor device 33
Write data from the data bus 27 is programmed into a predetermined address indicated by the address bus 26 of the ROM 34 . At the same time, the data comparison circuit 35 inputs data from the data bus 27 in response to the control signal 36 from the timing signal generation circuit 25. When the program ends, the control signal 29 (RD) k inactive level ("
Return to O”).

Finally, the PROM 34 data is output to the data bus 27 by the control □□ double signal 7 (OE) from the timing signal generation circuit 25. The data comparison circuit 35 compares the data on the data bus 27 with the previously input data using a control signal 36. Thereafter, while the voltage level of the control signal 32 (VPP) from the timing signal generation circuit 25 remains unchanged, the control signals 28, 29, 30.31.degree. 36.37 are repeatedly changed to perform programming and verification over all addresses.

[Problem that the invention seeks to solve]

Programming and verifying using the conventional PROM writer described above has the disadvantage that an expensive PROM writer is required. Another disadvantage is that the semiconductor device must be removed from the depacking tool used for programming and verification.

[Failure to solve the problem]

The semiconductor device of the present invention is a PROM (Programab).
leReadOnlyMemory) and the above P
an address signal generation circuit that designates addresses of the ROM and external storage device; an input terminal that inputs program and verify designation signals of the PROM; and a signal applied to the input terminal is determined and the data is read from the external storage device. , a control means for writing (programming) into the PROM, a circuit for comparing data in the PROM and data in an external storage device, and performing verification 1, and a Z output terminal for outputting the verified results are connected at the same level. on the body substrate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The half-body kege 1 has an address signal generation circuit 2 and a PROM 3.
and timing signal generation circuit 4, write pulse generation port i
'45, data comparison circuit 6, address bus 7, data bus 8, memo! J ffrlJ4'JC'M It is composed of a child 9, an input terminal 10, an output terminal 11, and a verify output terminal 12. Further, FIG. 3 shows the timing of programming and verifying.

The program and verify operations are started by an active edge ("0"→"1") of the input terminal 10 that specifies the program and verify operations. Input terminal 1
When 0 becomes active level at timing T1, T
At timing 2, output terminal 11 is set to active level ("
1") to inform the outside that programming and verifying operations are in progress. Furthermore, the control signal 13 (VPP) from the timing signal generation circuit 4 becomes active level (1"). Control signal 13 (VPP) is PRO
This is a signal that supplies power to M3, and - set power supply (VDD)
The active level ('1') is when the voltage is higher than 2l-25V, and the inactive level ('0'') is when the voltage is the same as the installed power supply (VDD).

This high voltage f! The means for obtaining the high voltage from the outside may be either a method of supplying the high voltage from the outside or a method of boosting the voltage inside the semiconductor long jet 1. next,
At timing T3, the control signal 14.15 from the timing signal generation circuit 4 becomes active level 1'').

Address signal generation circuit 2, timing signal generation circuit 4
A predetermined address is output to the address bus 7 by the control signal 14 from
ry)) (7) Specify the address. External storage device 2
0 indicates the address bus 7, data bus 8, and
-: +) The address bus 7 Data at a predetermined address indicated by is read out at timing T5 determined by the external storage device 20 and output to the data bus 8.

The write pulse generation circuit 5 receives the control signal 15 from the timing signal generation circuit 4 at the timing PRO of T6.
Outputs input pulse 17 (PGM) to M3.

PROM3 is t! From flJ Goi No. 8 13 (VPP)'
Data from the external storage device 20 is written via the data bus 8 to a predetermined address indicated by the address bus 7 by the write pulse 17 (PGM) from the enrichment pulse generation circuit 5. ). At this time, the data comparison circuit 6 outputs the input pulse 17 (PG
Write data (data 1) is received from the data bus 8 in synchronization with M).

When the data is completely written to the PROM 3, the timing signal generation circuit 4 outputs the control signal 16 (R) at the timing T7.
D) Return to the inactive level (on). The data bus 8 is in a floating (high/high) state, and the timing signal generation circuit 4
sets the control signal 18 (OE) to the active level ('1'') at the timing of T8.Then, the PROM 3 outputs data to the data bus 8 at the timing of T9.

The timing signal generation circuit 4 sets the timing control signal 18 (OE) of T10 to an inactive level (0'').
Return to At this time, the data comparison circuit 6 reads and stores data (data 2) at the same address from the PROM 3 via the data bus 8 at timing T10. after that,
When the control signal 19 from the timing signal generation circuit 4 becomes active level ('1') at the timing of 'I'll', the data comparison circuit 6 compares the stored data 1 and data 2.

Of the above operations, the program and verify are completed by repeatedly executing T3 to Tll for all addresses of PROM3. When programming and verification are completed, the timing signal generation circuit 4B, T
At timing 12, the control signal 13 ('VPP) and the output terminal 11 are set to inactive level (O'') to indicate that the program and verify operations are completed.When all data is written correctly, that is, the compared data If data 1 and data 2 match across all addresses of the PROM 3, the data comparison circuit 6 sets the verify output terminal 12 to an active level (1''), indicating that the verify result is normal.

Note that if the semiconductor device tξ1 in this embodiment is a single-chip microphone/computer, a program counter is used as the address signal generation circuit 2, and an ALU (Arithmetic Logic U) is used as the data comparison circuit 6.
nit) can be used. Furthermore, in this embodiment, the external storage device 20 is RAM, but it can be ROM or PR.
OM can also be used.

〔Effect of the invention〕

As explained above, the present invention provides an address signal generation circuit, a timing signal generation circuit, a write pulse generation circuit, and a data comparison circuit in a semiconductor device having a built-in PROM. This has the great effect of not requiring a PROM writer. Another advantage is that programming and verification can be performed without taking out the semiconductor device from the depacking tool being used. Furthermore, when the present invention is applied to a single-chip microconverter, the program counter is used as an address signal generation circuit, and the ALU (Arith-me
Logic Unit) can be used as a data comparison circuit, so there is no need for an increase in hardware.

[Brief explanation of drawings]

FIG. 1 shows a block configuration of an embodiment of the present invention. 1...Semiconductor device ζ, 2...-Ato, SHE signal generation circuit, 3...PROlVl, 4...
...timing signal generation circuit, 5 ... rich pulse generation circuit, 6 ... data comparison circuit, 7
...Address bus, 8...Data bus, 9...Memory control terminal. 10...Input terminal, 11...Output terminal, 12...
Verify output terminals, 13, 14, 15. 16, 18.
19... Control signal, 17... Write pulse, 20... External storage device (RAM). FIG. 2 is a conventional block diagram using a PROM writer. 21・・・・・・PROM writer, 22・・・・・・
Memory device, 23...Address signal generation circuit, 2
4...---Write pulse generation circuit, 25...
...Timing signal generation ID, 26...Address bus, 27...Data bus, 28...
... Baraki pulse, 29, 30, 31, 32° 36.
37... Control signal, 33... Semiconductor device, 34... PROM, 35... Data comparison circuit. FIG. 3 is a timing diagram of programming and verifying in the apparatus of FIG. 1. Agent Patent Attorney Otohara Uchihara Figure 2 (Example of a new floor)

Claims (1)

[Claims] a PROM, an address signal generation circuit for instructing addresses of the PROM and the external storage device, an input terminal for inputting program and verify designation signals for the PROM, and a signal applied to the input terminal for determining the signal applied to the external storage device. A control means for reading data from and writing it to the PROM, a circuit for comparing data in the PROM and data in an external storage device, and an output terminal for outputting a comparison result are provided on the same semiconductor substrate. A semiconductor device.