JPS6045827B2 - test pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test pattern generator that makes it possible to test a semiconductor memory circuit or a memory circuit portion in a semiconductor device and efficiently analyze the results.

Figures 1a to 1e show arbitrary memory cell matrices used to test malfunctions of address circuits, decoder circuits, etc. of the memory under test, effects of interference between memory cells in the memory cell matrix, etc. An example is shown in which a test pattern that intentionally inverts the write data pattern of an area is written to the memory under test.

The shaded area in the figure indicates that the write data is inverted with respect to the others. Conventionally, test patterns for performing data inversion in arbitrary areas have been created using a microprogram system having a configuration including a program control section 1, an address pattern generation section 2, and a data pattern generation section 3 as shown in Fig. 2. It was generated by the pattern generator that was used. In such a conventional test pattern generator, both the address pattern to be generated and the data pattern (for example, a write pattern) to be generated at that time are generated by essentially independent pattern generation sections, so that they are It was difficult to create a relationship between the two. Therefore, in order to invert the data pattern in an arbitrary area as shown in FIG.
, inversion, +N, -N, etc.) and the instruction set that controls the program control unit 1 of the microprogram that describes the test pattern sequence.
Not only does the number of steps in the microprogram increase and make it more complex, but it is also generated by the combination of the arithmetic function of the data pattern generation section 3 and the instruction set that controls the program control section 1. Therefore, it has the disadvantage that it imposes restrictions on the area in which data can be inverted. The present invention makes it possible to perform data pattern inversion in an arbitrary area with a simple configuration, whereas the microprogram is complicated and has restrictions in a pattern generator using the conventional microprogram method as described above. Examples are described in detail below.

In the present invention, the address pattern applied to the memory circuit under test and the data pattern (for example, write data pattern) at that time are independently applied to the memory circuit under test. By creating a relationship between the address pattern generation section and the data pattern generation section, it is now possible to easily invert the data pattern in any area, as shown in Figure 3. 1 shows a block diagram of an embodiment of the present invention.

The embodiment shown in FIG. 3 stores a microprogram that describes a test pattern to be generated, decodes the microprogram at the time of execution, and sends an instruction to a pattern generation section. A program control unit 1 that receives state information and controls the progress of the microprogram, and a data pattern generation unit 3 that generates data patterns by receiving commands from the program control unit 1 and performing corresponding arithmetic operations. an address pattern generation section 2 that generates an address pattern by receiving instructions from the program control section 1 and performing corresponding arithmetic operations; a boundary value register 5 that stores boundary values of data inversion areas; and an address pattern generation section 2 a comparison logic circuit 4 which compares the address pattern generated from the data pattern and the contents of the boundary value register 5 according to one logic state selected by a selection signal;
The logic circuit 4 compares the data pattern generated from the raw section 3.
It is constituted by an inverting circuit 6 that performs an inverting or non-inverting operation depending on the output state of the inverting circuit 6.

In order to explain the operation of the present invention, FIG. 4 takes a memory circuit under test 10 with a memory cell matrix size of 8×8 as an example, and data is inverted from the 4th place to the 6th place of the memory cell. The operation will be explained below using this figure and the previous figure 3. Note that a region 11 indicated by a thick line indicates a data inversion region. Before executing the test, the microprogram that describes the test pattern to be generated in the program control unit 1 and the boundary value of the area in which data is to be inverted in the memory under test, for example, a value of 40 in the case of Fig. 4, are set. It is stored in the boundary value register 5. The test receives a microinstruction for the data pattern generation section of the microprogram decoded by the program control unit 1, and generates a data pattern by performing an arithmetic operation corresponding to the microinstruction, as well as an address pattern of the microprogram. It receives an address pattern generated by receiving a microinstruction for the generating section and performing an arithmetic operation corresponding to the microinstruction, and selects one of the multiple address patterns based on the contents of the preset boundary value register 5 and a selection signal. One comparison logic (for example, in the symbol in Figure 3, A=B, A>B
, A<B, A half B, A≧B, A≦B, etc.), and the inverting circuit 6 inverts the signal. That is, the comparison logic circuit 4 is provided with a comparator, an exclusive OR circuit, etc. for performing these comparison logics in parallel, and is further provided with a multiplexer. [The above various logical operations are performed on address patterns commonly given as these inputs. Each of the logically operated output signals is applied to the multiplexer, and one output determined by the selection signal is selected and output as inverted information C. In the example of FIG. 4, the data pattern generator 3
causes the memory circuit under test 10 to write "0", the boundary value register 5 stores the value 40 as mentioned above, and the selection signal to the comparison logic circuit 4 is , A≧B is “true”. Note that when the comparison logic result is determined to be true, the comparison logic circuit 4 sends inversion information to the inversion circuit 6.
Perform the operation to output to. Therefore, in the area 11 from the 4th area to the 6th area, the data pattern is inverted and written from the data pattern generating section 3. FIG. 5 is a block diagram of another embodiment of the present invention, in which the address pattern generation section is capable of generating two types of address patterns, X address and Y address, in parallel;
Furthermore, in this embodiment, partial area inversion is convenient for investigating malfunctions of address circuits, decoder circuits, etc., such as B, d, and e in FIG. 1, and the influence of interference between memory cells in a memory cell matrix. In order to generate a test pattern that performs
If Yl to Y4, a configuration is provided to perform the logical operation, and accordingly, boundary value registers X1 to X4, Yl to Y4 are provided.
The number of boundary value registers for storing the values is also four for each of X and Y, that is, 5x1 to 5x4 and 5y1 to 5y4.

Note that the same symbols as in FIG. 3 indicate the same parts. Further, the number of boundary value registers is not limited to the above-described embodiment, and a larger number may be provided. As explained above, in the present invention, the address pattern from the address pattern generating section 2 and the boundary value registers 5, 5x are connected between the address pattern generating section 2 and the data pattern generating section 3.
A comparison logic circuit 4 is provided that stores boundary values in advance in 1 to 5x4 and 5y1 to 5y4 and compares them with the contents, and inverts the data pattern from the data pattern generation section 3 according to the output of this comparison logic circuit 4. The circuit 6 performs inversion and non-inversion, and by associating the address pattern with the data pattern, the data pattern in any area can be inverted with an extremely small number of program steps.

[Brief explanation of the drawing]

1A to 1E are explanatory diagrams of the data inversion area for the memory under test, FIG. 2 is a block diagram of a conventional test pattern generation section, and FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 4 is an operation explanatory diagram, and FIG. 5 is a block diagram of another embodiment of the present invention. 1 is a program control section, 2 is an address pattern generation section, 3 is a data pattern generation section, 4 is a comparison logic circuit, 5,
5x1~5x4.5y1~5y4 are boundary value registers, 6
is an inverting circuit.

Claims (1)

[Claims] 1 Stores a microprogram that describes the test pattern to be generated, decodes the microprogram during execution, sends commands to the pattern generator, and receives status information from the pattern generator to control the progress of the microprogram. a program control section to control, a data pattern generation section that receives instructions from the program control section and performs corresponding arithmetic operations to generate a data pattern, and a data pattern generation section that receives instructions from the program control section and performs corresponding arithmetic operations. an address pattern generation section that generates one or more types of address patterns, and a boundary value of the data inversion area corresponding to each of the one or more types of address patterns from the address pattern generation section. Compare one or more boundary value registers, the address pattern generated from the address pattern generation section, and the contents of the boundary value register by selecting one of the logic circuits prepared in advance by a selection signal. a comparison logic circuit that calculates logic and outputs inversion information; and an inversion circuit that receives the inversion information output from the comparison logic circuit and performs inversion and non-inversion operations on the data pattern generated from the data pattern generation section according to the contents thereof. A test pattern generator characterized in that it performs data inversion in an arbitrary area.