JPH0271178A - Test sequence generation circuit - Google Patents

Abstract

PURPOSE:To effect most efficiently a test according to a type of a circuit to be tested by calculating an exclusive OR of output of a plurality of FF's with a plurality of FF's connected in series. CONSTITUTION:A test sequence generation circuit 10 includes circuits 12 to 43 containing FF's connected in 32stages in series, exclusive OR calculation (EOR) circuit 44 to 46, and ternary drivers 51 to 82 which output values connected to output terminals Q of circuits 12 to 43 and stored in the output terminals Q, and in addition, a multiplexer (MUX) 90. The MUX 90 selects one of signals according to a logical value 1 or 0 of a control signal 102 from among an output 100 of the circuit 44 as a calculation result of an exclusive OR for Q outputs of the 10th, 30th, 31st and 32nd stages of the circuits 12 to 43 and an output Q32 of the circuit 43 so that the circuit 10 can generate a test sequence according to a type of a circuit to be tested, and supplies it to an input terminal of the circuit 12.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a test sequence generation circuit used in testing integrated circuits, and in particular to a test sequence generation circuit that has optimal characteristics depending on the type of circuit to be tested. The present invention relates to a test sequence generation circuit that can generate a sequence and supply it to a circuit under test.

(Prior art) Conventionally, gate array LSI or standard cell type L
In order to perform a functional test on a logic LSI such as an SI, a test sequence is input to the logic LSI through the input terminal, and the logic LSI
The output of I is compared with the expected value.

Furthermore, when the scale of integrated circuits increases, the ratio of the number of internal states to the number of input/output terminals increases with the above method, making it difficult to perform reasonable tests. An effective method is to provide a test sequence generation circuit within the integrated circuit, operate this test sequence generation circuit during testing, generate a test sequence, and use this to test circuits such as combinational logic circuits and arithmetic circuits within the integrated circuit. Methods are being used to test the functionality of blocks. What makes this method possible is an integrated circuit with a built-in self-diagnosis function.

Conventionally, a test sequence having pseudo-random number characteristics has been used in such a functional test.

FIG. 6 shows a conventional test sequence generation circuit 1 that generates a test sequence having such pseudo-random number characteristics. This is a so-called EXTERNAL type LFSR (Line
ar Feedback 5hift Register
or ), a predetermined number of stages of flip-flops 2 to 9, in this example 8 stages, are connected in series to form a shift register, and a predetermined plurality of flip-flops constituting this shift register, In the example, 3,5
．． A feedback loop is formed by calculating the exclusive OR of the Q outputs of the seventh and eighth stage flip-flops and supplying the result to the input terminal of the first stage flip-flop 2 of the shift register.

Generally, when the total number of stages of the shift register configured as described above is m, m-bit test data is obtained on the internal data bus. A set of test data constitutes a test sequence, this test sequence is an M sequence, has pseudorandom number characteristics, and has 2
It has a period of m-1.

A conventional integrated circuit with a built-in self-diagnosis function includes a test sequence generation circuit configured as shown in FIG. In this case, a set of output values of each flip-flop in the test sequence generation circuit, that is, 8-bit test data in the example shown in FIG. The data is transferred to a combinational logic circuit connected to the data bus, such as a circuit block under test such as an ALU.

The test data transferred to the circuit block under test undergoes predetermined calculations or processing there. The result is compared with an expected value, and it is determined whether the circuit block is able to perform a predetermined function or whether a failure has occurred.

(Problems to be Solved by the Invention) However, such conventional techniques have the following problems.

In other words, a circuit block having a configuration in which a large number of unit components are regularly arranged and connected, such as a register file consisting of an ALU, a shifter, or a RAM, is tested using a test sequence having random number or pseudo-random number characteristics. However, in order to obtain sufficient fault coverage, it is necessary to apply a large number of test data to the block under test.
It is not possible to conduct an efficient test and the test must take a long time.

Further, in testing the RAM, a test series called checker flag or checker board is usually used. This involves writing to the arrays of even and odd addresses in memory in regular repetitions in the order of 0.1 and 1.0, respectively, and then reading them to see if the expected results are obtained. This is something to check. However, test data having such regularity cannot generally be generated by the test sequence generation circuit having only a pseudo-random number generation function according to the prior art described above.

The present invention has been made to solve these problems in the prior art, and is capable of generating a plurality of optimal test sequences in the sense of performing the test most effectively according to the type of each circuit to be tested. The purpose is to provide a test sequence generation circuit.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the test sequence generation circuit of the present invention includes a first circuit means configured by connecting a plurality of flip-flops in series; The outputs of a plurality of flip-flops among the flip-flops constituting the first circuit means are inputted and the exclusive OR is calculated, so that the first circuit means generates a test series according to the type of the circuit to be tested. A first signal which is the result of the exclusive OR operation is input to the input terminal of the first stage flip-flop of the first circuit means so as to be generated, and the first signal is the output of the final stage flip-flop of the first circuit means. second circuit means for selectively supplying either the second signal, a third signal having a constant logical value of 1 or 0, or a fourth signal in which logical values of 1 and 0 appear alternately; have

(Operation) The test sequence generation circuit configured as described above is capable of generating not only a test sequence having pseudo-random number characteristics but also a plurality of test sequences having various regularities.

That is, in order to generate a test sequence with pseudo-random number characteristics, an exclusive OR is calculated on the outputs of a predetermined plurality of flip-flops connected in series to form a shift register, and the result is transferred to the shift register. The signal is fed back to the input side of the first stage flip-flop. That is, it has an LFSR configuration.

On the other hand, in order to generate a test sequence having a predetermined regularity, a signal having a value or change pattern corresponding to this regularity is supplied to the input terminal of the first stage flip-flop of the shift register.

Selection of the type of test sequence to be generated, that is, selection of the input mode to the flip-flop in the first stage of the shift register, can be performed using, for example, a multiplexer.

In this way, when the test sequence generation circuit of the present invention is incorporated into an integrated circuit, it is possible to use the optimum test sequence according to the type and characteristics of each part of the integrated circuit to perform a functional test or failure inspection of each part of the integrated circuit. Therefore, a high failure detection rate can be achieved and the test time can be significantly shortened.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a test sequence generation circuit 'il! used in an integrated circuit with a built-in self-diagnosis function according to a first embodiment of the present invention. 110
FIG.

In addition to the test sequence generation circuit 10, the integrated circuit of this embodiment includes:
It has circuit blocks such as ALU, RAM, shifter, adder, etc., and a test sequence generation circuit 10 for each of these circuit blocks.
A functional test is performed using a test series that generates

The integrated circuit of this embodiment has an internal bus structure, and an internal data bus 11 is connected to a test sequence generation circuit 10 and each of the circuit blocks described above. Further, the integrated circuit of this embodiment has a micro ROM that stores a micro program, and a test micro program for controlling the operation of each part in the integrated circuit during a functional test is stored in this micro ROM. .

Each microinstruction read from the microROM is held in a microinstruction holding register, and control is performed based on the information held in this register.

The test sequence generation circuit 10 includes circuits 12 to 43 including 32 stages of flip-flops connected in series, exclusive OR operation (FOR) times ff444, 45 and 46, each including any one of 12 to 43 flip-flops. The internal data bus 1 is connected to the output terminal Q of the circuit and carries the value held at the output terminal Q of the circuit including each flip-flop.
In addition to having ternary drivers 51 to 82 that output to 1,
According to the purpose of the present invention, a multiplexer (MUX>90) is provided.

MUX90 has 10th stage, 30th stage, 31st stage and 3rd stage.
The output 100 of the EOR circuit 44, which is the result of the exclusive OR operation on the Q output of the circuit including the second stage flip-flop, and the output Q32 of the circuit 43 including the flip-flop occupying the final stage in the series configuration are input. , and a control signal 102 for controlling the selection of the signal to be output from the output 100 of the EOR circuit 44 and the output Q32 of the circuit 43 including the flip-flop to the input terminal of the circuit 12 including the first stage flip-flop. ing.

FIG. 2 shows the circuit configuration of the circuit 12 including flip-flops. Circuits 13 to 4 containing other 7 lipfrogs
3 also has a completely similar configuration.

The circuit 12 including flip-flops is composed of a D-type flip-flop 105 and two selectors 107 and 108. When the signal 110 input via the terminal U for control of the selector 108 has a logic value of 0, the Q output of the flip-flop 105 is fed back to the input 1 rule, and the flip-flop 105 holds data. On the other hand, when the signal 110 has a logic value of 1, the selector 1
If the signal 111 input as the control signal 5 for 07 through the terminal T has a logical value of 0 or 1, the flip-flop 105 inputs the signal through the terminal S or terminal P, respectively.

Using the test sequence generation circuit E@10 having such a configuration, a test on an integrated circuit is executed as follows.

That is, when starting a test on the integrated circuit of this embodiment, by inputting a test start signal to a predetermined input pin of the integrated circuit, the test sequence generation circuit 10 is activated and starts executing its function.

The functional test is performed for each circuit block in the integrated circuit in a predetermined order according to the contents of the test microprogram stored in the microROM.

For example, when a series of microinstructions corresponds to a test on an ALU, one of the microinstructions is read into the microinstruction holding register, and this microinstruction specifies a write from the bus to the ALU. , and instructs to read test data corresponding to the ALU test from the test sequence generation circuit to the bus. In this way, the operation of the test sequence generation circuit is under the control of microinstructions.

For example, when the circuit blocks to be tested are combinational logic circuits, ALUs, or RAMs, the control signal 1 to the MUX 90 according to the microinstruction as described above.
The value of 02 is set to O or 1, respectively, and the input terminal S of the circuit 12 including the flip-flop is set to EOR.
Output 100 of circuit 44, circuit 4 including flip-flops
The output Q32 of No. 3 is selected and inputted by the MUX 90. The test sequence generation circuit 10 generates test sequences in different manners depending on these two types of input manners to the circuit 12 including flip-flops.

That is, when the output 100 of the EOR circuit 44 is input to the input terminal S of the circuit 12 including the flip-flop, the circuits 12 to 43 including the flip-flop, the EOR circuits 44, 45 and 46, and the MUX 90 as a whole are connected to the LFSR. This LFSR is 3
2-bit pseudo-random number data is output onto the internal data bus 11.

A set of pseudorandom number data as a test series forms a so-called M (Maximum) series,
In this embodiment, the period is as long as 2321.

On the other hand, when the MUX 90 selects the output Q32 of the circuit 43 including the flip-flop in accordance with the value 1 of the control signal 102 and supplies it to the input terminal S of the circuit 12 including the flip-flop, the circuits 12 to 43 including the flip-flop and the MUX 90 constitutes a circular shift register as a whole, and the test sequence generation circuit 10 generates a test sequence on the internal data bus 11 in a data rotation mode, which will be explained later using an example.

On the other hand, when starting to supply a test series according to the type of circuit to each circuit under test, it is necessary to set initial values to the flip-flops in circuits 12 to 43 including each flip-flop. It is done as follows.

That is, in the tarok cycle in which the initial value setting macro command is executed, the control signal 115 shown in FIG.
, 116 and 117 are logical values 1, 1 . A selection is made in accordance with the combination of control signal values in selectors 107 and 108 provided on the input side of the circuit including each flip-flop, and the initial value data present on the internal data bus 11 is transferred to the selector 107. , 108 to each flip-flop and are held therein.

Further, in the test data read cycle, the logical values of control signals 115, 116 and 117 are 0, 1, .
1, and the circuit 12 etc. including each flip-flop outputs the held value to the internal data bus 11 via the ternary driver 51 etc., and the circuits 12 to 43 including the flip-flop output the held value to the internal data bus 11 via the selectors 107 and 108. The Q output of the circuit including the previous stage flip-flop is input to its input terminal.

In cycles other than initial value setting and test data reading, the values of control signals 116 and 117 are 0,
The test sequence generation circuit does not perform any operation.

The values of the control signals 115 to 117 are set by executing a microprogram.

A case in which the test sequence generation circuit 10 generates a test sequence in data rotation mode will be described using an example.

That is, in this operation mode, test data is output onto the internal data bus 11 in a manner in which a set of initial values set for each flip-flop is sequentially subjected to cyclic operations.

For example, if initial values are set for each flip-flop by a microinstruction so that all the flip-flops in circuit 812 have a value of O except for the value of the flip-flop in circuit 812, which is 1.

In this data rotation mode, the following test sequence is output onto the internal data bus 11 every time a microinstruction reads the test sequence generation circuit: Read number Test data 1 (10000...000) 2
(01000...000)3 (00100
...000)4 (00010...000
) In the array of numbers in parentheses indicating test data, the i-th number from the left corresponds to the value from the circuit including the i-th stage flip-flop in the shift register consisting of circuits 12 to 43 including flip-flops.

In other words, in the data rotation mode as shown in this example, the test data obtained by reading the held value from the circuit including each flip-flop is the same as the test data from the previous read. It has been toured. That is, assuming that i is not 1, the value from the circuit including the first-stage flip-flop in the current reading is equal to the value from the circuit including the i-1-th stage flip-flop in the previous read. In addition,
The value from the circuit 2412 including the first stage flip-flop in this readout is equal to the value from the circuit 43 including the 32nd stage flip-flop in the previous readout.

In this embodiment, this test series is used to test circuit blocks such as ALU.

That is, each test data constituting this test series is controlled by a microinstruction and supplied to, for example, an ALU via the internal data bus 11, where it is subjected to predetermined processing such as bit pattern inversion, and the processing result is transmitted by another microinstruction. The data is read out from the ALU under control, guided to a conventionally known data compression circuit via the internal data bus 11, and its output is compared with an expected value to perform a functional test on the ALU.

Also, as an example of a pond, the initial value (01010...101)
When set to each flip-flop, the following test sequence is obtained in data rotation mode: Readout number Test data 1 (01010...101)2
(10101...010)3 (01010
...101)4 (10101...010
) This test series has a characteristic in which 0s and 1s appear regularly and alternately, and is called a checker flag pattern, and in this embodiment, it is used in testing circuit blocks such as RAM. .

That is, the first test data read out is supplied to the RAM under the control of the microinstruction and stored at the first address. Furthermore, the stored results are read out onto the internal data bus 11 under the control of other microinstructions, and the RAM is tested.

As described above, in this embodiment, a test sequence generation circuit that generates test sequences in the data rotation mode and the pseudorandom number generation mode is incorporated on the integrated circuit chip.
Since the system is configured and controlled to automatically generate a test sequence that most efficiently tests the circuit block to be tested depending on the type of the circuit block to be tested, a significant reduction in testing time is achieved.

In addition, the ternary driver, rose 1, etc. are held in a high impedance state with the value of the signal 117 set to O in cycles other than data reading from each flip-flop onto the internal data bus 11.

Next, a second embodiment of the present invention will be described. FIG. 3 shows the circuit configuration of the test sequence generation circuit 120 used in the integrated circuit with built-in self-diagnosis function of this embodiment.

The test sequence generation circuit 120 includes circuits 12 to 43 including flip-flops, and EOR circuits 44.45 and 46.3.
Value driver array or 82 and multiplexer (MU
It is configured such that X>90. The basic configuration is the same as that of the test sequence generation circuit 10 of the first embodiment, and elements having corresponding functions are referred to by the same reference numerals in both cases.

In this embodiment, the MUX 90 receives the output 100 of the EOR circuit 44 and the signal 12 from a fixed value generator (not shown).
1 is input. Furthermore, a control signal 102 is input to the MUX 90, and according to the value of this control signal,
A selection of the output of the UX 90 is made. That is, when the control signal 102 has a logic value of 0, the MUX 90 selects the EOR circuit 44 output 100 from among its two inputs and outputs it to the input terminal S of the circuit 12 including the flip-flop. In this case, the test sequence generation circuit 120 outputs pseudorandom number data onto the internal data bus 11 as in the first embodiment.

On the other hand, when the control signal 102 has a logic value of 1, the MUX
90 selects the signal 121 from the fixed value generator and supplies it to the input terminal S of the circuit 12 including a flip-flop. In this case, the test sequence generation circuit 120 generates data in a fixed value shift-in mode, as illustrated below using an example, so that each time data is read onto the internal data bus 11, the value of the signal 121 includes a flip-flop. Circuits 12 to 4
The signal is shifted into a shift register consisting of 3.

For example, each flip-flop has an initial value (00000...
000) and set the value of the control signal 102 to 1, each time data is read, the following series of data,
That is, the test series is output onto the internal data bus 11: Readout number Test data 1 (00000...000) 2
(10000...000)3 (11000
...000)4 (11100...000
) The main elements constituting the fixed value generator are a micro ROM that stores a test microprogram and a register for holding micro instructions. The data for generating the fixed value is held in the instruction.

Similarly, MUX9 is added to the microinstruction in the middle of the microprogram that controls test sequence generation in fixed value shift-in mode.
The control signal 102 to 0 takes the value 1, and data is held for causing the MUX 90 to select the fixed value signal 121 having a logical value of 0 or 1.

The test series in the previous example is used to test circuit blocks such as ALUs, shifters, adders, etc., but the test method is basically the same as in the first embodiment. For example, when testing an adder,
The corresponding test microprogram is executed and the 32-bit test data output to the internal data bus 11 is
The calculation result is transferred to the data compressor via the internal data bus 11, and the addition circuit performs its normal function by comparing the result with the expected value. It will be determined whether it is possible.

Next, a third embodiment of the present invention will be described. FIG. 4 shows the circuit configuration of the test sequence generation circuit 130 used in the integrated circuit with built-in self-diagnosis function of this embodiment.

The test sequence generation circuit 130 includes circuits 12 to 43 including flip-flops, and EOR circuits 44.45 and 46.3.
Value driver array or 82 and multiplexer (MU
X>91 and 92, etc. That MUX
The basic configuration of the parts excluding 91 and 92 is the same as that of the test sequence generation circuit 10 of the first embodiment, and even in this embodiment, the elements having corresponding functions in both are the same. Referenced by code.

In this embodiment, a signal 135 from a fixed value generator (not shown) and an output Q32 of a circuit 43 including a flip-flop are input to the MUX 91, and an EO signal is input to the MUX 91.
Output 100 of R circuit 44 and signal 131 from MUX 91
is entered.

Furthermore, MUX91 and MUX92 each have a control signal 13.
4 or 133 is input, and this control signal 13
The outputs of MUX 91 and 92 are selected according to the values of 3 and 134. That is, when the control signal 133 has a logical value O, the MUX 92 selects the output 100 of the EOR circuit 44 from among its two inputs and outputs it. In this case, the test sequence generation circuit 130 outputs pseudorandom number data onto its internal data bus 11, as in the first embodiment.

On the other hand, when the control signal 133 has a logic value of 1, the MUX
92 selects input 131 from MUX 91, but at this time, the value of control signal 134 to MUX 91 is 1.
If so, the signal 135 from the fixed value generator is selected by the MUXs 91 and 92 and supplied to the input terminal S of the circuit 12 including the flip-flop. In this case, the test sequence generation circuit 130 generates data in fixed value shift-in mode, as described above with respect to the second embodiment.

On the other hand, control signals 133 and 134 each have a logic value of 1.
and 0, MUX91 and MUX92 output Q32 of circuit 43 including a flip-flop from among the inputs.
is selected and outputted to the input terminal S of the circuit 12 including a flip-flop, and in this case, the test sequence generating circuit 130 generates test data in the data rotation mode as described in connection with the first embodiment.

Even in this embodiment, the test is carried out under the control of the test microprogram stored in the micro ROM. For example, the MUX 91 and 92 Control signal 1 to
The values of 33 and 134 are also set based on the data held in the microinstruction. In this embodiment, not only can the same effects as in the first embodiment be obtained, but also when there are multiple types of circuit blocks in an integrated circuit, an optimal test sequence can be determined for each type of circuit block. Since the test can be performed using the generated test data, the test can be further streamlined and the test time can be shortened.

Next, a fourth embodiment of the present invention will be described. As shown in FIG. 5, the integrated circuit with built-in self-diagnosis function of this embodiment includes circuits 12 to 43 including flip-flops, EOR circuits 44, 45, and 46. Three-value drivers 51 to 82.
, a test sequence generation circuit 140 configured with a multiplexer (MUX>90 and a toggle flip-flop circuit 141) is used.The toggle flip-flop circuit 1
The basic configuration of the parts other than 41 is the same as that of the test sequence generation circuit 10 of the first embodiment, and even in this embodiment, elements having corresponding functions in both have the same reference numerals. Referenced.

The circuit 143 in the toggle flip-flop circuit 141 has the same configuration as the circuit 12 including flip-flops.

In this embodiment, the output 100 of the EOR circuit 44 and the signal 142 from the toggle flip-flop circuit 141 are input to the MUX 90.

The selection of the signal from both signals in MUX 90 to be output to circuit 12, which includes a flip-flop, is made according to the value of control signal 102.

That is, when the value of the control signal 102 is 0, MUX9
0 selects the EOR circuit B44 output 100 and outputs it to circuit 12 including flip-flops, circuits 12 to 43 including flip-flops, EOR circuits 44, 45, and 46.
The MUX 90 has an LFSR configuration, and a pseudo-random number sequence, which is a set of 32-bit pseudo-random number data, is obtained on the internal data bus 11.

On the other hand, when the value of the control signal 102 is 1, the MUX 90
selects the toggle flip-flop circuit output 142 and outputs it to the circuit 12 including the flip-flop. in this case,
Each time the test data on the internal data bus 11 is read out to the circuit under test, the toggle flip-flop circuit 141 performs a toggle operation and the value of its output 142 is inverted.

The initial value setting for the toggle flip-flop circuit 141 is as follows.
This is done by setting the values of control signals 115 and 116 both to 1, which causes the grounded circuit 14 to
The initial value 0 is set through the terminal P of No. 3.

For example, (10101...010) is set as an initial value in each flip-flop in circuits 12 to 43 including flip-flops, and
When a signal having values repeated in the order of 0.1 from 10101...010)2
(01010...101)3 (10101
...010)4 (01010...101
) The test sequence generated in this toggle mode has a checker flag pattern and is suitably used for testing RAM.

Although the embodiments of the present invention have been described above as integrated circuits with a built-in self-diagnosis function that are equipped with a test sequence generation circuit, the present invention is not limited to these. A test sequence generation circuit constructed according to the present invention may be provided in the test system to perform the test. Even in this case, for example, if a test sequence generation circuit having the configuration basically shown in FIG. 3 is used, a plurality of multiple If a test sequence is generated, and if the test is performed using the one most suitable for the type of circuit to be tested, the test can be significantly streamlined and the test time can be significantly shortened.

[Effects of the Invention] Since the present invention is configured as described above, it has the following effects.

With a relatively simple configuration that adds a gate to a conventional LFSR, by arbitrarily combining initial value data and operation modes, it is possible to generate not only test sequences with pseudo-random number characteristics but also multiple tests with various regularities. Therefore, a functional test can be performed using the optimum test sequence according to the type of circuit to be tested, and the test time can be significantly shortened.

It is also possible to generate a test sequence with a checker flag pattern for testing the RAM.

[Brief explanation of the drawing]

1, 3, 4 and 5 are circuit diagrams of test sequence generation circuits according to first, second, third and fourth embodiments of the present invention, respectively, and FIG. , FIG. 6 is a circuit diagram of a test sequence generation circuit according to the prior art. 1... LFSR 2, 3, 9... Flip-flop 10.120, 130, 140... Test sequence generation circuit 11... Internal data bus 12.13, 14, 39, 41, 42, 43° 143・
・Circuit including flip-flop 44, 45, 46...
・EOR circuit 51, 52, 53, 78, 79, 80, 81° 82...
・Three-level driver 90.91.92...Multiplexer (MUX) 10
2.115,116,117,133°134...Control signal 105...D type flip-flop 107.108...Selector

Claims (4)

[Claims] (1) A test sequence generation circuit that generates a test sequence to be supplied to a circuit under test, comprising a first circuit means configured by connecting a plurality of flip-flops in series; The first circuit means inputs the outputs of a plurality of flip-flops among the flip-flops constituting the flip-flops, calculates an exclusive OR of these, and causes the first circuit means to generate a test sequence according to the type of circuit to be tested. A first signal, which is the result of the exclusive OR operation, is input to the input terminal of the flip-flop in the first stage of the first circuit means, and a second signal, which is the output of the flip-flop in the last stage of the first circuit means, is constant. a third signal having a logical value of 1 or 0, or a fourth signal in which logical values of 1 and 0 appear alternately; second circuit means for selecting and supplying one signal from at least two signals; A test sequence generation circuit comprising: 2. The test sequence generation circuit according to claim 1, wherein the second circuit means has a toggle flip-flop for generating a fourth signal in which logic values of 1 and 0 appear alternately. (3) A first circuit means configured by connecting a plurality of flip-flops in series, and inputting the outputs of a plurality of flip-flops among the flip-flops forming the first circuit means, and calculate the exclusive OR, and
A first signal which is the result of the exclusive OR operation is applied to the input terminal of the first stage flip-flop of the first circuit means so that the circuit means generates a test sequence according to the type of circuit to be tested. a second signal which is the output of the last flip-flop of the first circuit means; a third signal having a constant logic value of 1 or 0; or a fourth signal in which logic values of 1 and 0 appear alternately. 1. An integrated circuit testing method characterized in that it is carried out using a test sequence generation circuit having second circuit means for selecting and supplying one signal from at least two of the signals. (4) An integrated circuit with a built-in self-diagnosis function, comprising the test sequence generation circuit according to claim 1 together with a circuit to be tested.