KR100450655B1 - Digital block test circuit and digital to analog converter by using the same, especially testing with simple circuit construction without adding plurality of pins - Google Patents

Abstract

PURPOSE: A digital block test circuit and a digital to analog converter(DAC) by using the same are provided to easily test with a simple circuit construction without adding a plurality of pins. CONSTITUTION: A digital block test circuit(210) includes an operation unit, a data storage unit an output controller and a random access memory(RAM) DAC. The operation unit inputs the output of the digital block as an input and performs a predetermined operation by inputting the previous operation result as another input. The data storage unit stores the output of the operation unit in response to the clock signal and outputs the stored value as another input of the operation unit. The output controller outputs the final operation result of the operation unit stored at the data storage unit to the input terminal of the digital block in response to the output enable signal. And, the RAM DAC performs the test for the output of the digital block from the signal applied to the input terminal of the digital block.

Description

Digital Block Test Circuit and RAM Digital-to-Analog Converter Using the Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RAM Digital-to-Analog Converter (hereinafter referred to simply as RAMDAC), and more particularly to a digital block test circuit for testing the performance of a packaged RAMDAC.

In general, computers use digital signals, but monitors use analog signals to represent information on the screen. RAMDAC is a device that converts a digital signal transmitted from a computer into an analog signal in order to express information on a screen faster on a monitor.

FIG. 1 is a block diagram of a conventional RAM home, comprising a first D flip-flop 102, a RAM 104, a second D flip flop 106, and a digital-to-analog converter (DAC) 108. .

The RAMDAC shown in FIG. 1 uses a DAC as a core, stores a digital signal input from an external controller (not shown) such as a graphic controller, and then outputs the stored value as an analog signal.

Specifically, the RAM 104 shown in FIG. 1 receives an 8-bit address ADD1 from the external controller through the address bus ADD <7: 0>, and also receives 8 through the data bus DB <7: 0>. The digital data D of the bit is received, and the digital data D is written to the address ADD1 in response to the write enable signal WEN. Here, the RAM 104 has a size of 256 × 8, for example, and the addresses ADD1 are generated sequentially. In addition, the digital data D written in the RAM 104 is read in response to the read enable signal REN.

While the RAM 104 described above does not perform a sequential write or read operation, when the desired data is to be read from the stored digital data D, the RAM 104 may read an address ADD0 in addition to the address ADD1. Receive.

The first D flip-flop 102 latches, for example, 8-bit pixel data PD (all or part of the above-described digital data D), and latches the latched data in response to the clock signal CK. Output as ADDO). The RAM 104 inputs the address ADD0 to output the corresponding digital data D.

The second D flip-flop 106 latches the digital data D output from the RAM 104 and outputs the latched data in response to the aforementioned clock signal CK. Next, the DAC 108 inputs the output of the second D flip-flop 106, that is, the digital data D, and outputs the corresponding analog signal through the output terminal OUT.

The conventional RAMDAC described so far is made of an IC chip and then subjected to a test process to confirm whether or not the above operation is performed properly. In the conventional test method, a test signal is applied by using existing pins of a chip, and accordingly, an abnormality of the chip is determined by checking the output signal.

Here, since the IC chip must apply a test signal using the limited pins and check the output signal, the IC chip must be suitable for determining whether the applied test signal is abnormal and also check all circuits inside the chip. For this reason, in some cases, a single line inside the chip is connected to a pin on an external chip (ie, a pin must be added) or a test circuit is added to use an existing pin.

However, integrating a conventional RAMDAC into an IC, the analog output of the DAC is coming out only on one pin of the chip. In other words, the abnormality of the circuits other than the DAC should be checked through the analog output of the DAC. Therefore, at the time of the test, in which digital block is composed of the first D flip-flop 102, the RAM 104 and the second D flip-flop 106 and the analog block consisting of the DAC 108, which block is abnormal? There was a problem that is not easy to distinguish correctly.

In addition, in the case of digital blocks, there is a difficulty in terms of fault coverage, which indicates how much can be checked among all the abnormalities in the circuit. ) And apply it to the IC chip. However, even if a large number of input vectors are applied, the fault coverage is calculated by a software tool that calculates fault coverage at high and low levels in the digital circuit, so it is impossible to check this value by checking the output of the analog block. there was.

Therefore, in the case of an IC using a DAC such as a RAMDAC, a design must be made to increase the fault coverage using a small input vector and to calculate the fault coverage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a digital block test circuit and a RAM digital-to-analog converter using the same, which facilitate a test of a RAMDAC with a simple circuit configuration without adding a plurality of pins for a test.

1 is a block diagram of a conventional RAM digital-to-analog converter.

2 is a block diagram illustrating a digital block test circuit according to the present invention in a RAM digital-to-analog converter.

In order to achieve the above object, the test circuit according to the present invention includes a digital block for storing a digital signal, and optionally outputting the stored value in response to a clock signal, and an analog block for converting and outputting the output of the digital block into an analog signal. It is used to test a digital block in a RAM digital-to-analog converter, and it is preferable that it consists of arithmetic means, data storage means, and output control means. The calculating means inputs the output of the digital block as one input, and inputs the previous calculation result as another input to perform a predetermined operation. The data storing means stores the output of the calculating means in response to the clock signal, and outputs the stored value as another input of the calculating means. The output control means outputs the final calculation result of the calculation means stored in the data storage means to the input terminal of the digital block in response to the output enable signal. Here, by testing the output of the digital block from the signal applied to the input of the digital block, there is an effect of facilitating the test of the RAMDAC with a simple circuit configuration without adding a plurality of pins for the test.

In order to achieve the above object, the RAM digital-analog converting apparatus according to the present invention for converting a digital signal into an analog signal and outputting the analog signal to a display device is preferably composed of a RAM, a digital-analog converting means, and a test means. The RAM inputs and stores a digital signal, and the digital-analog converting means converts the output of the RAM into an analog signal and outputs the same to the display device. The test unit sequentially inputs the output of the RAM to perform a predetermined operation, and outputs a final operation result to the input terminal of the RAM, and is used to test whether there is an abnormality of the RAM.

Hereinafter, the configuration and operation of a RAM block digital block test circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a digital block test circuit according to the present invention in a RAM DAC. The RAM DAC includes a first D flip-flop 202, a RAM 204, a second D flip-flop 206, and a DAC 208. And a digital block test circuit 210.

Here, the digital block test circuit 210 has one input connected to the input of the DAC 208, and an exclusive inverted logic sum gate (XNOR) 212 that performs arithmetic operation, and an input D connected to the output of the XNOR 212. ), The clock CK connected to the clock terminal CK, the reset RN connected to the reset terminal TRSET, and the other inputs of the XNOR 212 similarly to the clocks CK of the first and second D flip-flops 202 and 206. An output A connected to the control terminal TRDEN and an input A connected to the output F of the D flip-flop 214 and the D flip-flop 214 that have an output Q connected to the data storage operation. E) and, like the data input DIN of the RAM 204, an output Y connected to the data bus DB, and a three-state buffer 216 for output control operation.

In the conventional RAMDAC (see FIG. 1), one of the methods to solve the above-mentioned problems is to check whether there is an abnormality of the digital block in front of the DAC without going through the DAC by directly connecting the node A to the pin of the IC chip. However, this method is simple and can increase fault coverage with the fewest input vectors, but adds a separate chip to the IC chip, increasing the pin count of the packaged IC. In other words, if the number of digital data processed by the DAC is small, the number of pins is small. However, the larger the number of bits, the more pins are used. Also, when using a plurality of DACs for a plurality of cores, more pins are added, thereby increasing the cost. do.

Ramdack of the present invention shown in Figure 2 has the same effect as adding a pin using an existing pin without adding a plurality of pins. Now, the operation of the digital block test circuit according to the present invention in the RAM is described.

The D flip-flop 214 of the digital block test circuit 210 is initialized in response to a reset signal input through the reset terminal TRSET from an external control device (not shown) during the RAMDAC test. Is in three states in response to the low level output enable signal input through the control terminal TRDEN.

The RAM 104 receives an 8-bit write address ADD1 from the external controller via the address bus ADD <7: 0>, and also receives 8-bit digital data D through the data bus DB <7: 0>. The digital data D is written to the corresponding write address ADD1 in response to the write enable signal WEN.

The first D flip-flop 102 latches, for example, 8-bit pixel data PD and outputs the latched data as the read address ADDO in response to the clock signal CK. Here, the pixel data PD is used as a test signal during the test of the RAMDAC. The RAM 104 inputs the read address ADD0 to output the corresponding digital data D.

The second D flip-flop 106 latches the digital data D output from the RAM 104 and outputs the latched data in response to the aforementioned clock signal CK. Next, the DAC 108 inputs the output of the second D flip-flop 106, that is, the digital data D, and outputs the corresponding analog signal through the output terminal OUT.

In the first clock cycle in which the clock signal CK is generated, the XNOR 212 of the digital block test circuit 210 enters the digital data D and the D flip-flop 214 initially input to the DAC 208 described above. Exclusive inversion OR of the initial value output from

In a second clock cycle, the D flip-flop 214 latches the output of the XNOR 212, feeds back the latched data to the XNOR 212, and outputs it to the tri-state buffer 216. At this time, the XNOR 212 exclusively inverts the next digital data D input to the DAC 208 and the next value output from the D flip-flop 214. That is, if this operation and storage operation is repeated every clock cycle, the D flip-flop 214 stores the finally calculated digital data (D).

The external control device transmits the pixel data PD to be transmitted to the first D flip-flop 202, that is, the test signal, and then outputs a high level output enable signal through the control terminal TRDEN. The tri-state buffer 216 transfers the last calculated digital data D stored in the D flip-flop 214 to the data bus DB <7: 0> connected to the RAM 204 in response to the output enable signal at this time. send. Here, obtaining the final calculated digital data D with respect to the series of test signals is for simplifying the test.

By checking the data bus line DB <7: 0> at this time, the circuit of the digital block of the RAMDAC composed of the first D flip-flop 202, the RAM 204, and the second D flip-flop 206 is indirectly checked. You can check the operation status. In addition, by controlling the value of the pixel data PD applied from an external control device, it is possible to solve the problem of the digital block test method, which has been a problem in the conventional RAMDAC test, and the problem of realizing fault coverage by a few input vectors. .

So far, the digital block test circuit of the RAMDAC of the present invention has been described with reference to FIG. 2. It should be noted in FIG. 2 that the node A is not directly connected to the pins of the IC chip in order to test the RAM block's digital block, but the output of the digital block is tested through the existing data bus <7: 0> through a test circuit. Is that. Thus, the test circuit shown in FIG. 2 can be modified to perform a desired arithmetic operation. That is, another gate may be used in place of the exclusive inversion logic gate (XNOR), or may be omitted in some cases.

As described above, the digital block test circuit and the RAM digital-analog converter using the same according to the present invention can increase the fault coverage by facilitating the RAMDAC test with a simple circuit configuration without adding a plurality of pins for the test. It has an effect.

Claims (5)

And a digital block for storing an input digital signal and arbitrarily outputting the stored value in response to a clock signal, and an analog block for converting and outputting the output of the digital block into an analog signal. In the test circuit used to test the digital block, Computing means for inputting the output of the digital block as one input and inputting the previous calculation result as another input to perform a predetermined operation; Data storage means for storing an output of the computing means in response to the clock signal and outputting the stored value as the other input of the computing means; And Output control means for outputting a final calculation result of the calculation means stored in the data storage means to an input terminal of the digital block in response to an output enable signal, And a digital block test circuit of a RAM digital-to-analog converter for testing the output of the digital block from a signal applied to an input of the digital block. A RAM digital-analog converter for converting a digital signal into an analog signal and outputting the analog signal to a display device, A RAM for inputting and storing the digital signal; Digital-to-analog conversion means for converting the output of the RAM into the analog signal and outputting the analog signal; And RAM digital-to-analog conversion characterized in that it comprises a test means for sequentially inputting the output of the RAM to perform a predetermined operation, and outputs the final operation results to the input terminal of the RAM to test the abnormality of the RAM Device. The method of claim 2, wherein the test means Computing means for inputting the output of the RAM as one input and inputting the previous calculation result as another input to perform a predetermined operation; Data storage means for storing an output of the computing means and outputting the stored value as the other input of the computing means; And And output control means for outputting a final calculation result of the calculation means stored in the data storage means to an input terminal of the digital block in response to an output enable signal. The RAM digital-to-analog converter of claim 2, wherein A first D flip-flop that latches pixel data for the digital signal in response to a clock signal and outputs the latched result to the RAM as a read address of the digital signal; And And a second D flip-flop for latching an output of the RAM in response to the clock signal and outputting the latched result to the digital-analog converter and the test means. . The method of claim 4, wherein the test means Arithmetic means for inputting the output of the first D flip-flop as one input and inputting a previous calculation result as another input to perform a predetermined operation; Data storage means for storing an output of the computing means in response to the clock signal and outputting the stored value as the other input of the computing means; And And an output control means for outputting a final operation result of the operation means stored in the data storage means to an input terminal of the RAM in response to an output enable signal.

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