JPH06138180A - Logic circuit unit testing machine - Google Patents

Abstract

PURPOSE:To provide a logic circuit unit testing machine which can execute various kinds of scan test type tests for testing a logic circuit unit without changing circuits and can improve testing efficiency and reduce test expenses. CONSTITUTION:This logic circuit testing machine incorporating a scan circuit is constituted of a pattern memory 1 storing test pattern data and test results, a test condition register 2 retaining test types etc., a microprogram memory 3 storing microprogram instructions, a micro control circuit 4 interpreting and executing the instructions, and a test processing circuit 5 for converting a logic signal to an electrical signal and then inputting it to a body 17 to be tested or converting the electrical signal output from the body 17 to be tested to a logic signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a logic circuit unit tester. In particular, to provide a logic circuit unit tester capable of executing tests by various scan test methods in a logic circuit unit test without changing the circuit and achieving improvement in test efficiency and reduction in test cost. Related to the improvement.

[0002]

2. Description of the Related Art In a logic function test of a logic circuit element such as an LSI or a printed wiring board on which the logic circuit element is mounted, it is tested whether or not a device under test logically functions normally. In the logic function test of a high-density, large-scale printed wiring board, the number of test patterns is large, the test time becomes long, and there is a strong demand for shortening the test time.

By the way, in the logical function test of the printed wiring, a scan test method is adopted for the purpose of executing the test in smaller units in order to facilitate the test. A special signal is required for this scan test method, and therefore a dedicated test circuit is required for each scan test method.

For example, the boundary scan test method requires special signals such as test data in (TDI), test data out (TDO), test clock (TCK) and test mode (TMS), and the above-mentioned signal TD.
Although I and TDO are obtained as a result of logic simulation, the signals TCK and TMS must be controlled by the tester at the time of testing, and a dedicated test control circuit is required. Similarly, in the case of other scan test methods as well, a signal to be specially controlled is required, and the control content of the signal also differs due to the difference in each scan test method.

A logic circuit unit tester according to the prior art will be described below.

FIG. 2 is an explanatory diagram of the configuration of a logic circuit unit tester according to the prior art.

In FIG. 2, reference numeral 11 is a disk device in which a test pattern is stored, and 12 is a test machine control computer for controlling the test machine. A test condition register 13 stores a test condition. Reference numeral 14 is a pattern memory, and this pattern memory 14 comprises a memory (scan-in pattern memory 141, scan-out pattern memory 142, comparison prohibition pattern memory 143) for storing a test pattern and a fail pattern memory 144 for storing a test result. . Reference numeral 15 is a test control circuit that controls the generation / input / output of control signals (hereinafter referred to as special signals) that differ depending on the test pattern transfer and scan test method. Reference numeral 16 converts the logic signal output from the test control circuit 15 into an electric signal and outputs the electric signal to the device under test 17, and also converts it into an electric signal of the test result input from the device under test 17 to perform the above test control. It is a test processing circuit that outputs to the circuit 15. A logic circuit unit tester is constituted by the above 13 to 16.

Next, the operation of this logic circuit unit tester will be described. The test conditions and test patterns read from the disk device 11 by the test machine control computer 12 are stored in the test condition register 13 and the pattern memory 14 in the test machine. This stored test condition,
The test control circuit 15 generates a required special signal based on the test pattern. The test processing circuit 16 converts this special signal into an electric signal and outputs it to the device under test 17. The test result is output from the device under test 17 to the test processing circuit 16, where the electrical signal is converted into a logical signal and compared with the expected pattern. As a result of the comparison, the data determined to be defective without matching the expected pattern is input to the fail pattern memory 14 via the test control circuit 15.

[0009]

In the logic circuit unit tester according to the prior art, when the scan test method is changed or a new scan test method is adopted, a dedicated dedicated test method corresponding to each scan test method is used. Since the above test control circuit is required, the circuit must be changed or added, and each time a design change or modification work is required, resulting in a decrease in test efficiency and an increase in test cost. .

An object of the present invention is to eliminate this drawback, and it is possible to execute the test by various scan test methods in the test of the logic circuit unit without changing the circuit, thereby improving the test efficiency and reducing the test cost. It is to provide a logic circuit unit tester capable of achieving reduction.

[0011]

The above-mentioned object is a pattern memory (1) for storing test pattern data and test results in a logic circuit tester incorporating a scan circuit.
A test condition register (2) for holding a test type, a microprogram memory (3) for storing a microprogram instruction, a microcontrol circuit (4) for decoding and executing the instruction, and a logic signal for electricity. Contents set in the test condition register (2), which is composed of a test processing circuit (5) that converts a signal into an input to the DUT and an electrical signal output from the DUT into a logical signal Based on the above, an instruction is read from the micro program memory (3), and a control signal for operating the scan circuit of the device under test is generated according to the instruction content, a read sequence of the pattern memory, and the content of the read pattern data. Input signal generation, comparison of the content of the read pattern data with the output logic from the DUT, and the comparison result to the pattern memory Paid, and is achieved by a logic circuit testing apparatus and controls the execution sequence of the microprogram.

In the above-mentioned logic circuit test apparatus, an execution control unit of a microprogram which operates independently of each other,
By having a test signal generation unit, a pattern memory consisting of a plurality of sets, a pattern signal sequence generation unit, and a processing unit, generation of a test control signal, reading of the pattern memory, generation of a signal sequence, storage, and micro The program execution control can be performed in parallel, and the microprogram memory can be a rewritable RAM or the like, and an external memory write circuit can be provided to rewrite the microprogram from the outside.

[0013]

The logic circuit unit tester according to the present embodiment controls the input / output of the test pattern and the generation / input / output of the scan control signal based on the microprogram. Without doing
By rewriting the microprogram, various scan test methods can be easily supported.

That is, the micro control circuit recognizes the scan test method and the type of pattern read from the disk device by the test machine control computer and stored in the pattern memory and the test condition register, and calls the corresponding micro program. . The micro control circuit starts control based on the called micro program. First, the micro control circuit fetches the pattern from the pattern memory according to the instruction of the micro program,
Data processing (serial / parallel conversion, bit inversion, bit shift, etc.) of the extracted pattern is performed, and a special signal such as a scan control signal is generated by instruction processing. In this way, the micro control circuit outputs the test pattern and the like suitable for the respective scan test method to the test processing circuit. The test processing circuit converts this output (logic signal) into an electric signal and applies it to the device under test. When a defect is found by the test, the scan fail pattern is stored in the pattern memory and one test cycle is completed. The test of the device under test is executed by repeating the above test cycle.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A logic circuit unit testing machine according to an embodiment of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, reference numeral 1 denotes a pattern memory for storing a test pattern and a fail pattern which is a test result. The test pattern is, for example, a scan-in pattern, a scan-out pattern, or a comparison prohibition pattern. Reference numeral 2 is a test condition register that stores a test condition. Reference numeral 3 is a microprogram memory for storing a microprogram. Reference numeral 4 is a test stored in the pattern memory 1 which reads out a necessary microprogram from the microprogram memory 3 based on the contents set in the test condition register 2 and based on the read microprogram. It is a micro control circuit that reads out a pattern, processes data, and generates a special signal such as a scan control signal. The reference numeral 5 converts a test signal, which is a logic signal output from the micro control circuit 4, into an electric signal and outputs the electric signal to the device under test 17, and converts an electric signal, which is a test result, into a logic signal to output the test result. Is a test processing circuit that outputs the comparison result to the micro control circuit 4. Reference numeral 11 is a disk device in which the test pattern is stored, and 12 is this disk device 1
It is a tester control computer that reads test patterns from 1.

Next, the operation of this embodiment will be described. The test pattern read from the disk device 11 by the test machine control computer 12 is stored in the pattern memory 1, and the test machine control computer 12 sets the test conditions and the like in the test condition register 2. The micro control circuit 4 reads out and executes a necessary micro program from the micro program memory 3 based on the contents set in the test condition register 2, and reads out the test pattern stored in the pattern memory 1, processes the data, and specializes the data. A signal is generated and output to the test processing circuit 5. The test processing circuit 5 executes the test of the device under test 17 based on the test signal input from the micro control circuit 4.
The test result is input from the device under test 17 to the test processing circuit 5, and the test processing circuit 5 compares the test result with the expected pattern. If they do not match, it is recognized as a defect and a fail pattern is created. It is sent to the micro control circuit 4. The micro control circuit 4 stores this fail pattern in the pattern memory 1 and completes one test. The test of the DUT 17 is executed by repeating the above processing.

FIG. 3 This figure shows the details of the micro control circuit according to the present invention. The micro control circuit includes a program control unit 41 that controls the execution of the micro program and a program memory control unit 4 that controls the reading of the micro program.
2. An instruction register 43 for storing instructions of a micro program, pattern memory control sections 44a to 44x for controlling reading or writing of a pattern memory, a pattern converting section 45a for converting a pattern from serial format to parallel format or vice versa. .About.45x, a test signal generator 46 for generating a special signal such as a scan control signal, the test pattern is stored in the pattern memory, the test condition register 13 stores the scan length, the entry address of the microprogram to be executed, and the like. After the information indicating the contents of the test is set, a start command is given to start the operation.

The program control unit 41 fetches the entry address of the program corresponding to the test set in the test condition register 2 and issues a command to the memory control unit 42 to read the microinstruction at the address, the memory control unit 42. Reads the microinstruction at the specified entry address into the instruction register 43 from the microprogram memory 3 in accordance with the instruction. The micro instruction is composed of a sequence control instruction, a pattern control instruction, and a test signal generation instruction. The sequence control instruction is sent to the program control unit 41, and the pattern control instruction is made up of a plurality of pattern memories and pattern conversion units. The commands corresponding to the respective patterns and related to the pattern memory access of the pattern control commands are memory control units 44a to 44a.
x, a command related to pattern conversion is sent to the pattern conversion units 45a to 45x, a test signal generation command is sent to the test signal generation unit 46, and the respective commands are processed simultaneously and in parallel.

The pattern memory control units 44a to 44x decode the given instruction and read or write the memory of the pattern memories 1a to 1x. The pattern conversion units 45a to 45x can switch the input / output direction of data, leave the pattern in parallel without any operation, or perform parallel / serial conversion by performing a shift operation according to an instruction. The pattern data is converted from parallel to serial from the pattern memories 1a to 1x or output to the test processing circuit 5 without conversion. Alternatively, the output signal or fail signal from the device under test sent from the test processing circuit 5 is converted from serial to parallel or is transferred to the pattern memories 1a to 1x without conversion.

The test signal generator 46 generates a scan control signal and the like in accordance with the supplied test signal generation instruction and outputs it to the test processing circuit 5.

The program control unit 41 decodes the given sequence control instruction, determines the address with the next microinstruction by processing such as conditional branching, and outputs the determined instruction address to the program memory control unit 42. The program memory control unit 42 fetches the next microinstruction from the instructed instruction address.

A test process is executed by repeating the above series of cycle operations until a STOP (end) command of the sequence control commands appears. The reading of the next instruction is stopped by the STOP (end) instruction, and one test process is completed.

The microprogram memory 3 is RA
It may be configured by M or ROM. The pattern memories 1a to 1x and the pattern memory control unit 44a to
The number of 44x and the pattern conversion units 45a to 45x is not limited. The pattern memories 1a to 1x and the test condition register 2 may have a capacity for one test or a capacity for a plurality of tests.

[0025]

As described above, the logic circuit unit tester according to the present invention reads a necessary microprogram from the microprogram memory based on the contents of the pattern memory, the test condition register, the microprogram memory, and the test condition register. However, based on this micro program, I / O is controlled, a micro control circuit that generates a special signal that is a scan control signal, and the output of this micro control circuit is converted into an electrical signal and applied to the device under test. Since it has a test processing circuit for converting an electric signal of to a logic signal, it is possible to control the input / output of the test pattern and the generation / input / output of the scan control signal based on the microprogram. Easy rewriting of microprograms without any changes or additions It is possible to correspond to the scan test method.

Therefore, according to the present invention, a test by various scan test methods in the logic circuit unit test can be executed without changing the circuit, and the test efficiency can be improved and the test cost can be reduced. A unit tester can be provided.

[Brief description of drawings]

FIG. 1 is a configuration explanatory diagram of a logic circuit unit tester according to an embodiment of the present invention.

FIG. 2 is a configuration explanatory diagram of a logic circuit unit tester according to a conventional technique.

FIG. 3 is a configuration explanatory diagram of a test control circuit in the logic circuit unit tester according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a configuration of a test control circuit in a logic circuit unit tester according to a conventional technique.

FIG. 5 is a flowchart conceptually illustrating a processing flow of a micro control circuit unit according to an embodiment of the present invention.

FIG. 6 is a time chart for explaining the operation of the micro control circuit unit according to the embodiment of the present invention.

[Explanation of symbols]

 1, 1a to 1x pattern memory (present invention) 2 test condition register (present invention) 3 micro program memory 4 micro control circuit 5 test processing circuit (present invention) 11 disk device 12 test machine control computer 13 test condition register (prior art) ) 14 pattern memory (prior art) 15 test control circuit 16 test processing circuit (prior art) 17 device under test 41 program control unit 42 micro program memory control unit 43 micro program instruction register 44a-44x pattern memory control unit 45a-45x pattern Conversion unit 46 Test signal generation unit (present invention) 51 Test sequence control unit 52 Test signal generation unit (prior art) 141 Scan-in pattern memory 142 Scan-out pattern memory 143 Comparison prohibited pattern memory 144 Fail pattern memory 531 to 534 Pattern memory control unit 541 to 544 Shift register

Front page continuation (72) Inventor Etsuo Ikoma 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Automation Limited

Claims (3)

[Claims] 1. A logic circuit tester incorporating a scan circuit, a pattern memory (1) for storing test pattern data and a test result, a test condition register (2) for holding a test type and the like, and a microprogram A micro program memory (3) for storing instructions, a micro control circuit (4) for decoding and executing the instructions, an input to the device under test by converting a logic signal into an electric signal, and an output from the device under test. Is composed of a test processing circuit (5) for converting an electric signal to a logic signal, and reads an instruction from the micro program memory (3) based on the content set in the test condition register (2), and the instruction content Of the control signal for operating the scan circuit of the device under test, the read sequence of the pattern memory, and the read pattern data It is characterized by generating an input signal from the memory, comparing the contents of the read pattern data with the output logic from the device under test, storing the comparison result in the pattern memory, and controlling the microprogram execution sequence. Logic circuit tester. 2. The logic circuit tester according to claim 1, wherein a microprogram execution control unit that operates independently of each other, a test signal generation unit, a pattern memory including a plurality of sets, and a pattern signal sequence generation unit, and processing A logic circuit tester capable of performing parallel processing of generation of a test control signal, reading of a pattern memory, generation and storage of a signal sequence, and execution control of a microprogram by having a unit. 3. The logic circuit tester according to claim 1, wherein the microprogram memory is a rewritable RAM or the like, and a memory writing circuit from the outside is provided so that the microprogram can be rewritten from the outside.