JP2660028B2 - LSI test equipment - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to an apparatus for performing an operation test of a logic circuit, and particularly to an LSI test apparatus for testing a large-scale logic LSI. .

(Prior Art) In recent years, with the increase in the scale of LSI, the scale of a logic circuit to be inspected has increased, and the target circuit itself has become more complicated, which makes the test very difficult. Also, the test equipment becomes more expensive as the number of pins and the speed of the LSI increase.

To solve this problem, a self-test method (BIST), a scan design method, and the like have been proposed. However, in the self-test method, since a self-test circuit is included in the LSI chip, the chip size becomes large and is not practical. Furthermore, in the scan design method, the test vector becomes enormous, the test time is long, and it is necessary to use an expensive external tester, which increases the test cost.

(Problems to be Solved by the Invention) As described above, in the conventional test method, the specification required for the external tester becomes complicated as the LSI becomes more complicated.
You will need an expensive tester. Further, if a self-test circuit is incorporated in the LSI itself to avoid this, there is a problem that the chip size of the LSI becomes large.

The present invention has been made in view of the above circumstances, and a purpose thereof is to use an inexpensive external tester for an LSI.
An object of the present invention is to provide an LSI test apparatus capable of performing an operation test of a circuit and minimizing the chip area of the LSI.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention resides in that the test circuit is integrated not on the same chip as the LSI circuit but on another chip.

That is, the present invention relates to an LSI test apparatus for driving an LSI circuit and testing its operation state, wherein the LSI test apparatus is formed on a separate chip from the LSI circuit to be tested and connected to the LSI circuit.
Generate test data for SI circuit operation test
A test circuit for supplying the LSI circuit at a high speed, comparing the output of the LSI circuit with an expected value, and outputting the comparison result at a low speed, and a test circuit connected to the test circuit for instructing the test circuit to generate the test data. And an external tester for inputting the comparison result output from the test circuit.

(Operation) According to the present invention, when designing and manufacturing a logic LSI circuit to be tested, a test circuit dedicated to the circuit is separately designed and manufactured. Since the test logic circuit can be manufactured by the same technology as the LSI circuit to be tested, it can have the same performance. Therefore, it is possible to easily realize a high-speed timing waveform and to have a storage capacity sufficient for testing a large-scale circuit. Since a conventional external tester may be used for the purpose of activating and managing the test circuit, a high-speed, multi-pin tester is not required.

The test circuit includes a test pattern generation circuit for the tester, a comparison circuit, a timing generation circuit, a ROM / RAM as a memory circuit for storing test data, and a microprocessor for communication and control with an external tester. . When these circuits are integrated on the same chip as the LSI circuit, the chip size of the LSI circuit increases. However, by integrating the test circuit on another chip, an increase in the chip size of the LSI circuit can be prevented. Furthermore, LSI circuits are generally large-scale, with 100K gates or more, and test circuits are easier to design.

According to the present invention, the test circuit is formed on a separate LSI chip, and includes a standardized portion and a specialized portion corresponding to the circuit under test, so that the test circuit can be easily created by the standard design procedure. it can. Since simple commands and data can be transferred from the external tester to the test circuit,
All you need is a very inexpensive tester. That is, according to the test apparatus, it is a very expensive part of the external tester. A high-speed timing circuit and a comparison circuit are to be created for each circuit under test by a circuit under test manufacturing technique in the same manner as the circuit under test.

If a small amount of instructions and test data are transferred from the external tester, the test circuit interprets them, generates a large amount of test data at high speed, outputs it to the circuit under test, and outputs the test circuit and the test circuit. Compare with the expected value within. These series of processing procedures are commonly used in a general test method, and are not claimed by the present invention.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples.

FIG. 1 is a schematic diagram showing an LSI test apparatus according to one embodiment of the present invention. In the figure, 10 is the LSI circuit to be tested, 2
Reference numeral 0 denotes a dedicated test circuit having a test function of the LSI circuit 10, and reference numeral 30 denotes an external tester. The test circuit 20 is inserted between the LSI circuit 10 and the external tester 30. here,
The test circuit 20 is designed at the same time as the design of the LSI circuit 10, but is formed on a separate chip from the LSI circuit 10.

A test pattern generation command or the like is supplied from the external tester 30 to the test circuit 20, and the test circuit 20 develops a test pattern based on the command, and the developed test pattern is supplied to the LSI circuit 10. Then, the output of the LSI circuit 10 that operates by inputting this pattern is supplied to the test circuit 20. In the test circuit 20, this output is compared with a preset expected value, and the comparison result (evaluation data) is supplied to the external tester 30. Here, data transfer between the LSI circuit 10 and the test circuit 20 is high speed, and data transfer between the test circuit 20 and the external tester 30 is low speed. That is, the test circuit 20 receives the test instruction sequence and generates an actual test pattern, so that the low-speed external tester 30 can perform a high-speed test of the LSI circuit 10 (high-speed device). Here, when the external tester 30 is set to a hexadecimal code parallel and the LSI circuit 10 is set to a binary code serial, a device simulation at 16 times higher speed is possible.

In order to maximize the effects of the present invention, it is important to reduce the amount of information by abstracting or upgrading the information exchange between the test circuit 20 and the external tester 30. For example, the tester 30 passes a test execution instruction to the test circuit 20, and the test circuit 20 generates and edits a test pattern according to the execution instruction. Alternatively, processing such as forming an actual waveform by adding timing information to the logical value vector is performed. The test pattern editing includes, for example, development into a loop and development of a subtest pattern.

FIG. 2 is a block diagram of a circuit necessary for the test circuit 20. In the figure, 21 is a CPU for interpreting a test generation instruction and generating a test pattern, 22 is a memory (ROM / RAM) for storing test programs and test results, 23 is a memory (ROM) for storing basic test pattern data, 24 is a pattern development circuit for developing test patterns, 25 is a memory (ROM) storing basic timing data, 26 is a timing generation circuit, 27 is a synthesis circuit, 28 is a pin connection matrix,
29 is a comparison circuit.

The CPU 21 is used for exchanging data with a tester, generating a test pattern inside, and the like. The memory 22 stores a basic pattern used for generating a test pattern, a dedicated test pattern required for evaluating a circuit under test, control information required for generating the pattern, and the like. Other subcircuits are also commonly found in testers, and standard circuit configurations are possible. The test pattern in the memory, control information of the pin connection matrix circuit, and the like are tested in accordance with the circuit under test. Therefore, the self-test circuit can be standardized, and a part of the circuit may be modified for each circuit under test. The output signals of the pattern development circuit 24, the timing generation circuit 26, and the synthesis circuit 27 are, for example, as shown in FIG.

Here, the operation of the test circuit 20 shown in FIG. 2 will be briefly described. The macro test pattern (test instruction sequence and test data sequence) is read from the external tester 30 by the CPU 21 and the test program and the memory stored in the memory 22 are read.
A hexadecimal macro test pattern is converted to a binary code test pattern based on the basic test pattern data stored in 23. This test pattern is
The pattern is expanded by the pattern expansion circuit 24, and the synthesis circuit 27 generates a test signal. Then, it is supplied to the LSI circuit 10 via the pin connection matrix 28. On the other hand, after the end of the test operation, the output data of the LSI circuit 10 is input to the comparison circuit 29 via the pin connection matrix 28, and is compared with a preset expected value. Then, the comparison result (evaluation data) by the comparison circuit 29 is stored in the memory 22 and then sent to the external tester 30.

Thus, according to the present embodiment, it is possible to prevent an increase in chip size caused by embedding a test circuit in the same chip, and to perform a complicated test. Although scan design signature analysis and the like are practical only inside and outside the 10K gate, this embodiment enables a huge amount of tests at low cost, so that a circuit test at the 100K gate level can be performed at the same time. Instead of an expensive external tester, a test start, analysis of test results, and the like may be performed by an inexpensive external tester or the like, and a test circuit performs high-speed timing waveform generation and waveform stroke performed by the expensive tester. This test circuit can be manufactured in large quantities by using the VISI technology and the gate array technology, so that a large number of circuits under test can be simultaneously measured in large quantities.

The present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the invention. For example, the apparatus of the present invention can be incorporated into a test line as shown in FIG. In FIG. 4, 31 is a test starter for inputting basic test patterns and the like to the test circuit 20, 32 is a test result analyzer for reading and evaluating test results in the test circuit 20, 40 is a test line that flows automatically,
Reference numeral 50 denotes a test bed which electrically connects the LSI circuit 10 and the test circuit 20 and has pads connected to the testers 31, 32 and the like. In this method, each time the test is completed, only the LSI circuit 10 is replaced, and the test can be performed using the test circuit 20 repeatedly.

[Effects of the Invention] As described above in detail, according to the present invention, the test circuit
Since the I circuit is not integrated on the same chip but on a separate chip, it is possible to test the LSI circuit using an inexpensive external tester and minimize the chip area of the LSI circuit. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an LSI test device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a test circuit in the above device, and FIG. 3 explains the operation of the test circuit shown in FIG. FIG. 4 is a schematic diagram for explaining a modified example of the present invention. 10 LSI circuit (tested circuit), 20 test circuit, 30 external tester, 40 test line, 50 test bed.

Claims (2)

(57) [Claims] 1. An LSI test apparatus for driving an LSI circuit by using an external tester and testing its operation state, wherein the LSI circuit is provided between the LSI circuit and the external tester according to the same design rule as that of the LSI circuit. A test circuit formed on a separate chip is inserted, and the test circuit generates test data for an operation test of the LSI circuit based on a test data generation command input at a low speed from the external tester. Supplying the test data to the LSI circuit at a high speed, inputting the output data of the LSI circuit at a high speed, comparing the input data with an expected value, and supplying the comparison result to the external tester at a low speed. Characteristic LSI test equipment. 2. A data generator for generating a large amount of test data at high speed based on a test data generation command input from the external tester, and a high-speed generator for generating a clock synchronized with an operation clock of the LSI circuit. 2. The LSI test apparatus according to claim 1, further comprising a timing generator, and a comparator for comparing the output of the LSI circuit with a preset expected value.