JPH11202026A - Method for failure analysis - Google Patents

Abstract

PROBLEM TO BE SOLVED: To locate a failure in an LSI to be tested using BEST(built-in self test) method by subdividing all test patterns equally, reading out an SA (encoded compressor) value upon finishing application of pattern of each Gr and comparing it with an expected code. SOLUTION: At first, a system clock SC is driven to prepare for generation of pseudorandom numbers from an RPG (random number generator) 20 in an LSI 9 to be tested. When scan-in clock is driven continuously by total number of patterns PA, the RPG 20 generates pseudorandom numbers sequentially and input latches (a) are shifted sequentially before the pseudorandom numbers are applied to a circuit 19 to be tested. Output data from the LSI 9 is captured by each output latch (b) and a scan-out clock SOCK is driven to scan out an SA 21. When the SC is driven upon finishing clock control of total number of patterns PA, a comparator (d) compares an output value with an expected code and the comparison results are described in a fail memory 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an LSI chip.
As a diagnostic method for determining a defect, there is a device relating to a defect analysis method in the BIST method which has been recently implemented by each company.

[0002]

2. Description of the Related Art FIG. 1 shows the principle of an LSI diagnosis system. For example, if there is a simple circuit under test as shown in the figure, there is a possibility that nodes A, B, C, D, E, and F have 0 stack fault and 1 stack fault, respectively.
With the 0/1 pattern input to C and D, it can be observed from the output F side. For example, A = B = C = D =
When test # 1 of 0 is input, if there is no particular failure in the circuit, E = 1 and F = 0 should be satisfied. However, when there is a 0-stack fault in E or a 1-stack fault in F, the output value from F becomes 1, and the existence of the fault can be recognized. However, in all other faults, the output of F remains at 0, and the existence of the fault cannot be recognized.

That is, in the pattern of test # 1, a 0-stack fault of E and a 1-stack fault of F can be detected. Similarly, in test # 2, only one stack failure of F can be detected.
Detectable / undetectable faults up to test # 16 are shown in FIG.
The result is shown in the truth table.

However, it is not necessary to use all 16 patterns to detect faults at all nodes of this circuit. For example, if only 5 patterns indicated by Y1 in the table are used, the fault detection rate becomes 100%. . As described above, in the diagnosis of the circuit under test, a “stored method” is often used in which a failure is assumed in each node, and a test pattern aimed at the failure is extracted and used by DA technology. As the circuit under test becomes more complex,
Since the number of test patterns required to achieve a failure detection rate of 100% is enormous, a pattern that guarantees a detection rate of about 95% is generally used.

Specifying a specific fault location in the circuit under test from the execution results of the above five patterns is referred to as fault location indication. For example, in the case of the circuit of FIG. 1, if test # 7 fails, there are three types of failures indicated by “Y2”. However, if test # 11 passes, it is considered that 0 stack of E and 1 stack of F are defective. That is, one stack failure of A is detected. Such an analysis is generally obtained by executing a simulation for indicating a failure position.

FIG. 2 shows an input / output configuration of a tester for realizing the above-described principle. When the logical file 1 of the LSI under test is input to the diagnostic system 2, the diagnostic file 3
Within the input pattern 4 generated based on the above principle
And the expected value 5 are developed. When these are transferred into the tester 6, they are separately stored in the input pattern 7 and the expected value 8, respectively. When the test is started, the input pattern 7 is applied to the internal logic from the input pin 10 of the LSI 9 to be tested.

After that, the data appearing from the output pin 11 is taken into the tester 6, compared with the expected value 8, and the result is stored in the fail memory 12 as fail information of the pattern. This is performed for all test patterns. Since the fail memory 12 is represented by a matrix of a tester channel and a test pattern, by reading it back after the test is completed, it is possible to know which pin of which pattern and which channel is connected to which failure has been detected. Therefore, the LS under test failed.
Failure analysis of I was easy.

[0008]

In the above-described diagnosis using the stored method, the data amount required for the diagnosis increases as the degree of integration of the LSI under test increases and the number of gates increases. When a 1M gate-scale logic LSI appears in the future, the time required for test pattern generation will become impractical, and the amount of data will not be able to be held in a buffer memory in a general tester, which will increase test costs. It is expected that this will be a major factor.

In recent years, the BIST method has been frequently used as a method for solving this problem. B in FIG.
The outline of the IST system will be described. In this method, since a test pattern is generated not by DA but by an RPG incorporated in the LSI under test in advance, it is not necessary to prepare a large-scale diagnostic input pattern from DA. Also, the output data does not capture all the patterns on the tester side, but only compares the code values sequentially compressed in the SA built in the LSI under test with the final expected codes. There is no need to prepare a special expected value pattern.

Therefore, the data output from the diagnostic system 2 to the diagnostic file 3 to which the logical file 1 has been input need only be a small amount of data such as the number of patterns 13, the initial value 14, and the expected code 15. When these are taken into 16 to 18 in the tester 6, the test preparation is completed. When the test is started, the initial value 17 is set to the RPG2 in the LSI 9 to be tested.
0, and RP according to the clock generated from tester 6.
G20 generates a pseudorandom number and applies it to the circuit under test 19. The output from the circuit under test 19 is
And compressed and held.

When the application of the number of patterns is completed, the tester 6 reads the code of SA 21 and compares it with the expected code 18 to determine whether the LSI under test is good or defective. In the method described above, the amount of data prepared on the DA side and held in the buffer memory in the tester is st
Although it is greatly reduced as compared with that of the ored system, the feature is that the number of patterns increases because the tester pattern generated by the RPG is a pseudorandom number and is not aimed at a failure.

As described above, in the BIST system,
It is characterized in that the determination of a defect is made based on the final code compressed and held in the SA. Therefore, unlike the stored method, it is not possible to perform comparison determination for all patterns for each pattern or to record data in a fail memory. If this is to be realized, it is necessary to provide a comparison / judgment mechanism for each pattern and a fail memory for each pin in the LSI under test, which significantly increases the chip area overhead, which is not practical. In other words, while the BIST method has the effect of suppressing the increase in the amount of diagnostic data due to the high integration of chips, there is no means for obtaining detailed information necessary for analysis for identifying the position of a defect when there is a defect. A device to deal with this is a major issue.

[0013]

FIG. 4 shows a failure analysis method when the BIST method is used. (A) in the figure is RPG
Is a pseudo-random pattern generated by the tester C in the horizontal direction.
H #, the vertical direction is the pattern #. Assuming that a failure occurs in (a), (b), and (c) in the figure when this pattern is applied to the circuit under test in order from pattern # 1 to n, according to the principle of the BIST method, Reads SA for the first time after the application of all patterns is completed, and when this is different from the expected code, it can be recognized that a failure exists somewhere. When it is not necessary to specify a defective portion as in the selection step, this chip may be regarded as defective and may be popped out. However, in the case of a failure analysis by an LSI designer, detailed information cannot be obtained by this alone. In this case, a second test is performed as shown in FIG.

At this time, all the test patterns are equally divided into k pieces, and Gr # 1, 2,..., K are provided. On the tester side, an expected SA code for each pattern application of each Gr is prepared.
In this state, first, the Gr # 1 pattern is applied, and after completion, the SA value is read out and compared with the expected code. Gr # 1
No failure occurs in the pattern of
When the pattern of r # 2 is applied, here (a) and (b)
Since the failure is included in two places, the Gr value is determined by comparing the SA value with the expected value after the pattern application is completed.
It can be recognized that 2 includes a fail pattern.

"Gr # 2" is recorded based on the result of this determination. At this stage, the SA is in a state different from the expected code, so the tester writes the expected code to the SA, as if no failure occurred, and then proceeds to Gr # 3 pattern application. In this manner, Gr # at which a failure occurs is recorded while repeating the pattern application and the determination of the SA value for each Gr #.

[0016] The second test is completed after finishing Gr # k. According to the above procedure, in this case, “Gr #
2 "and" Gr # (k-1) "are recorded.

Thereafter, in the third test shown in (c), only Gr # 2 and Gr # (k-1) are tested. First, the SA expected code at the end of Gr # 1 is written into the SA from the tester, and the test of Gr # 2 is started. At this time, the tester reads the output latch before compression by SA for each pattern and stores it in the fail memory.
The result of executing all the patterns of Gr # 2 enters the fail memory. When this is collected, Gr is then performed in the same manner.
For # (k-1), the execution results of all patterns can be collected. That is, since information including a fail is provided for Gr # 2 and Gr # (k-1), and information of "pass" is provided for other Gr, if this is input to the simulator for indicating a failure position, the circuit under test is obtained. The fault location in the inside can be specifically known.

That is, as described above, it is possible to point out a fault position even in the diagnosis by the BIST method.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
FIG. 2 is a block diagram illustrating a configuration of an SI tester. In FIG. 5, reference numeral 30 denotes an LSI tester main body.
Is connected to the host computer 31 and further connected to the LSI under test 47 via the performance board 46, thereby enabling the test of the LSI under test 47. The LSI under test 47 includes the LSI under test 19
In addition, there are an RPG 20 for generating and inputting a pseudo random number pattern and an SA 21 for storing output data from the LSI 19 to be tested. The test is controlled from a control screen 32 connected to the host computer 31.

The host computer 31 is used for compiling a test ++ program created by a user, displaying a test result of the LSI under test 47, and creating a database. The performance board 46 is a board that functions as an interface between the LSI tester 6 and the LSI under test 47 and includes a socket that can be connected to external terminals of the LSI under test 47 so that the LSI 47 to be tested is coupled to this socket. Has become.

The system bus 3 is provided in the LSI tester body 6.
And a host interface 34, a processor 35, and a buffer memory 3 via the system bus 33.
6, the test controller 37, the timing generator 38, the reference power supply 39, the device power supply controller 40, and the work register 47 are interconnected to exchange various data and signals.

The host interface 34 is connected to the host computer 31 so that data can be exchanged between the LSI tester 6 and the host computer 31. The buffer memory 36 stores data transferred from the host computer 31,
Used to hold data for transfer to
The data held in the buffer memory 36 includes object data JD, test results TE, the total number of test patterns PA, the number of test patterns PG, RPG per Gr.
SA initial value TI and SA expected value codes SA1 to SA corresponding to pseudo random numbers Gr # 1 to k generated by RPG
Ak is included.

The tester user creates a test control program by the host computer 31, generates object data by compiling the test control program, and stores it on a magnetic disk or the like. When the test of the LSI under test 47 is performed, the control screen 3 of the host computer 31
2. Start the test program from 2. When the test program is started, the object data stored in the magnetic disk or the like is expanded in the buffer memory 36 via the host interface 34, and is executed by the processor 35, so that the object data described in the test program is written. An environment is formed.

An example of failure analysis when the BIST shown in FIG. 4 is executed in such an LSI test system is shown below. FIG. 6 shows the relationship between the test pattern memory 41, the fail memory 42, and the LSI under test 47. When executing the first test, first, the initial value T in the buffer memory 36 is set.
I is developed into a scan-in sequence of the SID pin of the test pattern memory 41. Thereafter, when the system clock SC is driven by the timing generator 38, the RPG 20 in the LSI 9 to be tested is ready for pseudorandom number generation. Thereafter, when the scan-in clock SICK is driven, the pseudo random number generated from the RPG 20 is taken into the first input latch a. After that, S for all patterns PA
By continuously driving ICK, the RPG 20 sequentially
A pseudorandom number is generated, which in turn shifts the input latch and is applied to the circuit under test 50.

The data output from the LSI 19 to be tested is taken into each output latch b. Therefore, if the scan-out clock SOCK is driven, the data is scanned out to the SA 21. When the clock control for the total number of patterns PA is completed, the final expected SA code SAk is developed into the scan-out sequence of the SOD pin of the test pattern memory 41, and the system clock SC is driven. And the expected sign can be compared, and the determination result is described in the fail memory 12.
In the case of the example of FIG. 4, "fail" is written.

As described above, in the first test, the test result based on the input of all the patterns is determined. In the second test, the same process is executed for each of the divided Gr. In this case, the SA is read by the number of patterns P in Gr units.
Perform every G minutes. If Gr # n is judged as failed, n is saved in the work register 47 and Gr
SA initialization is performed using the SA expected value code SAn after #n ends. Therefore, in the example of FIG. 4, after the second test is completed, Gr # 2 and Gr # (k-1) are evacuated to the work area 51.

In the third test, the above Gr # 2 and Gr #
Only test again for (k-1). In this case, the SA is initialized by the SA expected value code SA1 after the end of Gr # 1, and a test pattern for PG is applied. In this case, the contents of the output latch b are not shifted out to SA21, but each output is output. The comparator c corresponding to the latch determines the expected value for each pattern by the comparator c, and writes the result to the fail memory 12. When the result of each pattern is determined in this way, the expected value of each pin cannot be held for each pattern. Therefore, the output expected values of all pins are fixed to 1 or 0 for all patterns, and this is compared with the output data. The result of the determination may be written in the fail memory 12.
The fail information obtained in this way is input to the failure location indication simulation as a detailed result of Gr # 2.
The same applies to Gr # (k-1).

[0028]

According to the conventional BIST method, it has been impossible to point out the fault location of the LSI under test, but this can be done. In a normal production process, it is only necessary to be able to select good / defective products, so a GO / NG test may be performed. However, in a failure analysis or the like by a designer, the mode is changed by implementing the present invention by changing the mode. Can be pointed out.

[Brief description of the drawings]

FIGS. 1A and 1B are a circuit diagram showing a principle of LSI diagnosis and a diagram showing a truth table.

FIG. 2 is a diagram showing a diagnosis procedure based on a stored method which is conventionally mainstream.

FIG. 3 is a diagram showing a diagnosis procedure according to the BIST method.

FIG. 4 is a diagram showing details of a failure analysis method using a BIST method according to an embodiment of the present invention.

FIG. 5 is a block diagram for explaining the structure of an LSI tester used to realize the present invention.

FIG. 6 is a diagram illustrating a procedure for using a test pattern memory and a fail memory when implementing the present invention.

[Explanation of symbols]

1. Logical file, 2. Diagnostic system, 3.
Diagnostic file, 4 ... Input pattern on file, 5 ...
Expected value on file, 6 ... LSI tester, 7 ... Input pattern on tester, 8 ... Expected value pattern on tester, 9 ... LS under test, 10 ... Input pin, 11 ...
Output pins, 12: Fail memory, 13: Number of patterns on file, 14: Initial value on file, 15:
Expected code on file, 16 ... number of patterns on tester, 17 ... initial value on tester, 18 ... expected code on tester, 19 ... circuit under test, 20 ... RPG, 2
Reference Signs List 1 SA, 31 Host computer, 32 Control screen, 33 System bus, 34 Host interface, 35 Processor, 36 Buffer memory, 37 Test controller, 38 Timing generator, 39 Reference power supply Reference numeral 40: Device power controller, 41: Test pattern memory, 43: Pin controller, 44: Pin electronics, 45: Device power, 46: Performance board, 47: Work register, JD: Object data, TE: Test result, PA: All Number of patterns, PG: Number of patterns in Gr units, TI: Initial value, SAn: Expected value code after completion of Gr # n, SC:
System clock, SID ... Scan-in data, SICK ... Scan-in clock, SOCK ... Scan-out clock, SOD ... Scan-out data, a ... Input latch, b ... Output latch, c, d ...
comparator.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toyoto Ikeya 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. Within technology

Claims (5)

[Claims] 1. A failure analysis method characterized in that a failure position necessary for failure analysis can be pointed out in LSI diagnosis by a built-in self-test (BIST) method. 2. An RPG (Ra) embedded in an LSI chip.
The huge number of pseudo-random patterns generated by the ndom pattern generator (random number generator) is divided into n groups, and the groups that contain the failed pattern are narrowed down by comparing the groups with expected values. A failure analysis method characterized by the following. 3. A failure analysis method wherein a BIST operation is performed again using only all test patterns in a narrowed group, and at this time, only a detailed output result for each test pattern is collected in a tester. 4. When the test of the group in which the fail exists is completed and the next group is started, the SA (Signature Analyze) is performed as if the fail did not exist.
A defect analysis method characterized by performing this after initializing a code compressor (code compressor). 5. A failure analysis method characterized in that a failure location in an LSI chip is specified by inputting an output result collected by the tester to a failure location simulator.