JPH02159585A - Testing device of lsi - Google Patents

Abstract

PURPOSE:To enable testing of an LSI circuit and reduction of a chip area of the LSI circuit to the minimum by integrating a test circuit on a chip separate from the one of the LSI circuit. CONSTITUTION:A test pattern generation instruction is supplied from an external tester 30 to a test circuit 20, a test pattern is developed in the circuit 20 on the basis of this instruction, and this pattern is supplied to an LSI circuit 10. An output of the circuit 10, which receives said pattern as an input and operates, is supplied to the circuit 20. In this circuit 20, said output is compared with an expected value set beforehand and the result of comparison is supplied to the tester 30. In this constitution, transmission of data between the circuits 10 and 20 is executed at a high speed, while transmission of data between the circuit 20 and the tester 30 is executed at a low speed. By generating a real test pattern is the circuit 20 according to a test instruction string, in other words, a high-speed test of the circuit 10 can be executed by the low-speed tester 30.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an apparatus for testing the operation of a logic circuit.
In particular, the present invention relates to an LSI test device for testing large-scale logic LSIs.

(Prior Art) In recent years, with the increase in the scale of LSIs, the scale of logic circuits to be tested has increased, and the target circuits themselves have become more complex, making testing extremely difficult. Furthermore, test equipment has also become more expensive as LSIs have more pins and higher speeds.

To solve this problem, we used the Self-Testing Method (BIST).
and scan design methods have been proposed. However, in the self-test method, since a self-test circuit is included in the LSI chip, the chip size increases and is not practical. Furthermore, the scan design method requires a large number of test vectors, requires a large amount of testing time, and requires the use of an expensive external tester, resulting in high testing costs.

(Problems to be Solved by the Invention) As described above, in conventional testing methods, as LSIs become more complex, the specifications required of external testers become more complex.
Requires an expensive tester. Furthermore, if a self-test circuit is built into the LSI itself in order to avoid this, there is a problem in that the chip size of the LSI increases.

The present invention has been made in consideration of the above circumstances, and its purpose is to test LSI using an inexpensive external tester.
An object of the present invention is to provide an LSI test device that can perform a circuit operation test and also minimize the LSI chip area.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to integrate the test circuit and the LSI circuit on a separate chip, rather than on the same chip.

That is, the present invention provides an LSI test device that drives an LSI circuit and tests its operating state.
It is formed on a separate chip from the SI circuit and connected to the LSI circuit, generates test data for testing the operation of the LSI circuit, supplies it to the LSI circuit at high speed, and outputs the LSI circuit to an expected value. A test circuit that compares and outputs the comparison result at low speed; and a test circuit that is connected to this test circuit, supplies the test circuit with a command for generating the test data, and inputs the comparison result output from the test circuit. An external tester is also provided.

(Function) According to the present invention, when designing and manufacturing a logic LSI circuit to be tested, a dedicated test circuit is separately designed and manufactured for the circuit. This test logic circuit can be manufactured using the same technology as the LSI circuit that is the circuit under test, so it can have the same performance. Therefore, it is possible to easily realize high-speed timing waveforms and to have a storage capacity sufficient to test large-scale circuits.

Since a conventional external tester can be used to start and manage this test circuit, a high-speed, multi-bin tester is not required.

The test circuit includes a test pattern generation circuit dedicated to the tester, a comparison circuit, a timing generation circuit, and a ROM/RAM as a memory circuit for storing test data.
and a microprocessor for communication and control with external testers. If these circuits are integrated on the same chip as the LSI circuit, the chip size of the LSI circuit will increase, but by integrating the test circuit on a separate chip, the LSI
It is possible to prevent an increase in the chip size of the circuit. Furthermore, LSI circuits are generally large-scale, with 100K gates or more, and compared to this, designing a test circuit is easy.

Furthermore, in the present invention, the test circuit is created on a separate LSI chip and consists of a standardized part and a specialized part corresponding to the circuit under test, so the test circuit can be easily created using standard design procedures. can. Since the external tester only needs to transfer simple instructions and data to the test circuit,
All you need is a very cheap tester. That is, according to this test device, the high-speed timing circuit and comparison circuit, which are extremely expensive parts of an external tester, are created for each circuit under test using the same manufacturing technology as the circuit under test. .

From the external tester side, if a small amount of instructions and test data are transferred, the test circuit interprets them, generates a large amount of test data at high speed, outputs it to the circuit under test, and outputs the output from the circuit under test and the test circuit. Compare with the expected value within. These series of processing procedures are commonly used in general testing techniques and are not claimed by the present invention.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a schematic diagram showing an LSI test device according to an embodiment of the present invention. In the figure, 10 is the LS1 circuit to be tested, 20 is a dedicated test circuit with a test function for the LSI circuit 10, and 30 is an external tester, and the test circuit 20 is inserted between the LSI circuit 10 and the external tester 30. has been done. Here, the test circuit 20 is the LSI circuit 10
Although it is designed at the same time as the LSI circuit 10, it is formed on a separate chip from the LSI circuit 10.

The external tester 30 supplies a test pattern generation command and the like to the test circuit 20, the test circuit 20 develops a test pattern based on this command, and the developed test pattern is supplied to the LSI circuit 10. and,
The output of the LSI circuit 10 which operates by inputting this pattern is supplied to the test circuit 20. In the test circuit 20, this output is compared with a preset expected value, and the comparison result (evaluation data) is supplied to the external tester 30. Here, data transfer between the LSI circuit 10 and the test circuit 20 is fast, and data transfer between the test circuit 20 and the external tester 30 is slow. In other words,
The test circuit 20 receives a test command sequence and generates an actual test pattern, so that the low-speed external tester 30 can
High-speed testing of the SI circuit 10 (high-speed device) is possible.

Here, if the external tester 30 side is hexadecimal code parallel and the LSI circuit 10 side is binary code serial,
16 times faster device simulation is possible.

In order to maximize the effects of the present invention, it is important to reduce the amount of information by abstracting or increasing the sophistication of information exchange between the test circuit 20 and the external tester 30. For example, the tester 30 passes a test execution command to the test circuit 20, and the test circuit 20 generates and edits a test pattern according to the execution command.

Alternatively, by adding timing information to the logical value vector,
For example, processing such as forming an actual waveform is performed. Test pattern editing includes expansion into loops, expansion of subtest patterns, and the like.

FIG. 2 is a block diagram of the circuitry necessary for the test circuit 20. In the figure, 21 is a CPU that interprets test generation instructions and generates test patterns, 22 is a memory (ROM/RAM) that stores test programs and test results,
23 is a memory (,
ROM), 24 is a pattern expansion circuit that expands the test pattern, 25 is a memory (ROM) that stores basic timing data, 26 is a timing generation circuit, 27 is a synthesis circuit, 28 is a pin connection matrix, and 29 is a comparison circuit. .

In addition, the CPU 21 exchanges data with the tester.

Used for internal test pattern generation, etc.

The memory 22 stores basic patterns used for test pattern generation, dedicated test patterns necessary for evaluating the circuit under test,
Control information necessary for pattern generation is also included. The other partial circuits are also circuits commonly found in testers and can have standard circuit configurations. The test pattern in the memory, the control information of the bin connection matrix circuit, etc. are tested every time according to the circuit under test. Therefore, the zero-self test circuit can be standardized, and only a portion of the circuit needs to be modified for each circuit to be tested. Note that the pattern development circuit 24, the timing generation circuit 26, and the synthesis circuit 2
Each output signal of 7 is as shown in FIG. 3, for example.

Here, the operation of the test circuit 20 shown in FIG. 2 will be briefly explained. The CPU 21 reads out a macro test pattern (a test instruction string and a test data string) from the external tester 30, and based on the test program stored in the memory 22, the basic test pattern data stored in the memory 23, etc., the macro test pattern is read out from the external tester 30. The test pattern is converted into a binary-code test pattern.

This test pattern is developed by a pattern development circuit 24, and a test signal is generated by a synthesis circuit 27.

The signal is then supplied to the LSI circuit 10 via the pin connection matrix 28.

On the other hand, after the test operation is completed, the output data of the LSI circuit 10 is input to the comparison circuit 29 via the bin connection matrix 28, and is compared with a preset expected value. The comparison result (evaluation data) by the comparison circuit 29 is stored in the memory 22 and then sent to the external tester 30.

Thus, according to this embodiment, it is possible to prevent an increase in chip size due to embedding a test circuit in the same chip, and also to perform complex tests. Scan design signature analysis and the like have been practical only for the inside and outside of the IOK gate, but this embodiment enables a huge amount of testing at low cost, making it possible to perform circuit tests at the LOOK gate level at the same time. Instead of an expensive external tester, an inexpensive external tester can be used to start the test, analyze the test results, etc., and the test circuit performs the high-speed timing waveform generation, waveform stroke, etc. that expensive testers do. This test circuit can be produced in large quantities using VLSI technology and gate array technology, so
A large number of circuits under test can be measured in bulk at the same time.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, the apparatus of the present invention can be incorporated into a test line as shown in FIG. 4, and tests can be carried out in an assembly line. 31 in FIG. 4 is a test start tester 3 for inputting basic test patterns etc. to the test circuit 20.
Reference numeral 2 denotes a test result analysis tester 40 that reads and evaluates the test results in the test circuit 20, and a test line that automatically flows. 50 electrically connects the LSI circuit 10 and the test circuit 20, and also includes testers 31, 32, etc. The test bed is shown with pads connected to it. With this method, it is possible to replace only the LSI circuit 10 every time a test is completed and to repeatedly use the test circuit 20 to perform tests.

[Effects of the Invention] As detailed above, according to the present invention, the test circuit is
Since it is not integrated on the same chip as the I circuit, but on a separate chip, it is possible to test the LSI using an inexpensive external tester.
The circuit can be tested and the chip area of the LSI circuit can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an LSI test device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a test circuit in the device, and FIG. 3 explains the operation of the test circuit shown in FIG. FIG. 4 is a schematic diagram for explaining the present invention in detail. DESCRIPTION OF SYMBOLS 10... LSI circuit (circuit under test), 20... Test circuit, 30... External tester 40... Test line, 50... Test bed. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (2)

[Claims] (1) In an LSI test device that uses an external tester to drive an LSI circuit and test its operating state, a test circuit formed on a separate chip from the LSI circuit is inserted between the LSI circuit and the external tester. The test circuit generates test data for testing the operation of the LSI circuit based on a test data generation command input at low speed from the external tester, and supplies this test data to the LSI circuit at high speed. At the same time, the LSI testing apparatus is characterized in that the output data of the LSI circuit is inputted at high speed, compared with an expected value, and the comparison result is supplied to the external tester at low speed. (2) The test circuit includes a data generation unit that generates a large amount of test data at high speed based on a test data generation command input from the external tester, and a high-speed timing generator that generates a clock synchronized with the operating clock of the LSI circuit. and a comparison section for comparing the output of the LSI circuit with a preset expected value, and is created according to the same design rules as the LSI circuit. The LSI test device described above.