JP3341772B1 - Semiconductor integrated circuit - Google Patents

Abstract

Kind Code: A1 The present invention relates to a semiconductor integrated circuit in which an independent bus connected to a CPU and a time-division bus not connected to the CPU are connected via an interface circuit. And reduce costs by reducing development costs. A time division bus (1) is provided from an interface circuit (19).
6 is provided with an address signal holding circuit 38 capable of holding the address signal output to the CPU 12 in a readable manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a built-in test circuit.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a main part of an example of a conventional semiconductor integrated circuit. In FIG. 6, reference numeral 12 denotes a central processing unit (CPU), and reference numeral 13 denotes an independent address. It is an independent bus composed of a bus 14 and a data bus 15. The address bus 14 and the data bus 15 are connected to the CPU 12.

Further, 16 is a time division bus used as an address bus or data bus in a time division manner, 17 is a peripheral circuit connected to the time division bus 16, and 18 is a time division bus 16
(Random Access Memory) connected to the RAM.

Further, reference numeral 19 denotes an independent bus 13 and a time-division bus 1
The time division bus 16 is not directly connected to the CPU 12 in this example.

In the interface circuit 19, reference numeral 20 designates a process required for transmitting to the time-division bus 16 an address signal designating an address assigned to the time-division bus 16 output from the CPU 12 to the address bus 14. This is the address processing unit that performs.

Further, 21 is a data bus 1 from the CPU 12.
5. Data processing for performing processing necessary for transmitting data output to the time division bus 5 to the time division bus 16 and processing required for transmission of data from the peripheral circuit 17 and the RAM 18 to the data bus 15 output to the time division bus 16 Department.

Reference numeral 22 denotes a selector for selectively connecting the output terminal 20A of the address processing unit 20 or the input / output terminal 21A of the data processing unit 21 on the time division bus 16 side to the time division bus 16.

In the conventional semiconductor integrated circuit shown in FIG. 6, especially when the interface circuit 19 does not operate normally,
Peripheral circuit 17 and RAM connected to time-division bus 16
The interface circuit 19 needs to be tested because it cannot operate normally.

[0009]

SUMMARY OF THE INVENTION Interface circuit 1
9 is, for example, the RAM 18
If all bits of the written data can be accurately read, it can be determined that the data is normal.

However, as described above, for example, the RAM 18
Even if the normal operation of the data processing unit 21 can be confirmed by writing and reading data to and from the CPU, in this case, it is determined that the content of the address signal output from the CPU 12 has not been changed in the address processing unit 20. It is not possible.

[0011] In this regard, for example, 0000 in the case of the _H address to 03FF _H addresses are assigned to RAM 18, the address processing unit 20, CPU 12
A case where there is a failure that changes the value of the least significant bit of the address signal output from “0” from “0” to “1” will be described.

In this case, a write cycle is performed and the CPU
An address signal designating the 0000 _H from address 12, 0
000 If the data DA is output to be written to the _H address, address signal for designating the 0000 _H address is changed to the address signal for designating the 0001 _H street address processing unit 20, the data DA to 0001 _H addresses the RAM18 Will be written.

Subsequently, a read cycle is performed, and the CPU 1
When the address signal from the 2 specifies the 0000 _H address is output, the address signal for designating the 0000 _H address is changed to the address signal for designating the 0001 _H street address processing unit 20, 0001 of the RAM 18 _H The data DA written at the address is read.

As described above, in the conventional semiconductor integrated circuit shown in FIG.
If there is a failure that changes the value of the first bit of the address signal output from 2 from “0” to “1”, it may not be possible to detect this.

[0015] Therefore, in the conventional semiconductor integrated circuit shown in FIG. 6, the address other than the address of interest, in terms of the previous example, previously written in advance different data to the address other than the 0000 _H address, after the test of the address of interest It is necessary to confirm that the data of the other addresses have not changed.

However, in such a case, the test time is increased, and when a series of products having different circuits connected to the time division bus 16 is manufactured, a different test pattern is required for each series. It has to be created, and there has been a problem that the product price rises due to an increase in development costs.

In view of the above, the present invention is a semiconductor integrated circuit in which an independent bus connected to a CPU and a time-division bus not connected to a CPU are connected via an interface circuit. It is an object of the present invention to provide a semiconductor integrated circuit capable of shortening the test time of an address processing unit of a circuit and reducing the cost by reducing the development cost.

[0018]

A semiconductor integrated circuit according to the present invention comprises a CPU and an independent address bus and data bus.
U, an independent bus which is used as an address bus or a data bus in a time sharing manner and is not directly connected to the CPU, and an interface circuit which connects the independent bus and the time sharing bus. In the semiconductor integrated circuit provided with the above, an address signal holding means capable of holding an address signal output from the interface circuit to the time-division bus so that the CPU can read the address signal is provided.

[0019]

According to the present invention, an address signal holding means for holding an address signal output from the interface circuit to the time-division bus so that the CPU can read the address signal is provided.

Therefore, an address signal for making a write access to the address signal holding means is held in the address signal holding means, and the held address signal is read out, so that an address processing section constituting the interface circuit is provided. Can be detected.

Further, according to the present invention, even when manufacturing series products in which circuits connected to the time-division bus are different, it is not necessary to create different test patterns for each series product, and the test patterns are common to the series products. Can be

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
An embodiment to a third embodiment will be described.

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention. The first embodiment of the present invention , Interface circuit 1
9 is connected to an address signal holding circuit 38 for testing the address processing unit 20, and the rest is configured similarly to the conventional semiconductor integrated circuit shown in FIG.

Here, in the address signal holding circuit 38, 39 is an address decoder, 40 is a latch circuit, 41
Is a flag (flag register), 42 is a front stage flag (front stage flag register), and 43 is a rear stage flag (second stage flag register).

The address decoder 39 is connected to the time division bus 16
The above address signal is decoded and read control signal RD
And a write control signal WR to control the read operation and the write operation of the latch circuit 40, and output a flag set signal SET and a flag clear signal CLR to control the setting and clearing of the flag 41. .

The latch circuit 40 is controlled by the read control signal RD and the write control signal WR output from the address decoder 39 to output the held address signal onto the time division bus 16 and to output the time division bus. 16 for holding the address signal.

The flag 41 indicates that the address decoder 3
9 instructs the latch circuit 40 to permit or prohibit the writing to the latch circuit 40. The first stage flag 42 and the second stage flag 43 operate with a shift of a half clock cycle.

FIG. 2 shows an address signal holding circuit 38.
2A shows a clock signal CLK, FIG. 2B shows a state of the time-division bus 16, and "A" shows an address signal output. The state "D" indicates a state where data is being output.

FIG. 2C shows the interface circuit 1.
9 read / write control signal, FIG. 2 (D)
2 shows a read control signal RD output from the address decoder 39, and FIG. 2E shows a write control signal WR output from the address decoder 39.

FIG. 2F shows an address decoder 39.
Clear signal CLR output from FIG. 2 (G)
Indicates a flag set signal SET output from the address decoder 39.

FIG. 2H shows the output of the front-stage flag 42, FIG. 2I shows the output of the rear-stage flag 43, and FIG.
Indicates the contents held by the latch circuit 40.

Here, the address bus 1 is sent from the CPU 12.
4. An address signal designating the address of the latch circuit 40 is output to the time-division bus 16 via the address processing unit 20 and the selector 22. When a read access is performed, the address decoder 39 decodes the address signal. Then, the read control signal RD is set to the H level to output the contents held by the latch circuit 40 to the time division bus 16.

In this case, the address decoder 39
Sets the flag set signal SET = H level, sets the flag 41, and sets the address decoder 39 to the latch circuit 4
A state is set in which writing to 0 can be permitted.

In this case, in the flag 41,
The first-stage flag 42 and the second-stage flag 43 are set in the order of the first-stage flag 42 and the second-stage flag 43 with a shift of a half clock cycle.

Thereafter, when an address signal is output from the interface circuit 19 to the time division bus 16 at the time of the first write access, the address decoder 39 sets the write control signal WR to the H level, and ,
The address signal is latched.

In this case, the flag 41 is cleared, and thereafter, the address signal on the time division bus 16 is not latched by the latch circuit 40 until data is read from the latch circuit 40.

In this case, in the flag 41,
The first-stage flag 42 and the second-stage flag 43 are cleared in order of the first-stage flag 42 and the second-stage flag 43 with a shift of a half clock cycle.

Thereafter, the address bus 1 is sent from the CPU 12.
4. An address signal for designating the address of the latch circuit 40 is output to the time-division bus 16 via the address processing unit 20 and the selector 22, and when a read access is performed, the address decoder 39 decodes the address signal. Then, the read control signal RD is set to the H level, and the content held by the latch circuit 40, that is, the previously latched address signal is output to the time division bus 16.

In this case, the address decoder 3
9 sets the cleared flag 41 to a state where a new address signal can be instructed to be latched to the latch circuit 40.

[0040] Therefore, in this first embodiment, for example, 0000 _H address ～7FFF _H addresses are assigned to the time division bus 16, when the latch circuit 40 is assigned 00FF _H street address, For example, the CPU 12 outputs an address signal as shown in FIG. 3 and causes the latch circuit 40 of the address signal holding circuit 38 to perform a read operation or a write operation.

[0041] That is, during the test, first, the read access to 00FF _H address. Thus, the contents of the latch circuit 40 are read, the flag clear signal CLR is set to the H level, and the flag 41 is set.

[0042] Next, the write access to the 0001 _H address. By doing so, the latch circuit 40 becomes 0001
The contents of the address signal designating the address _H are held, and the flag 41 is cleared.

[0043] Next, the read access to 00FF _H address. Thus, if the address processing unit 20 is normal, the address value of 0001 _H is output as data from the latch circuit 40 and the flag 41 is set.

[0044] On the contrary, there is a fault in the address processing unit 20, in the case where thus change the address output from the CPU 12, the latch circuit 40 holds the value of more than 0001 _H, 0001 _H Is not output as data.

[0045] Next, the write access to 7FFE _H address. In this case, the latch circuit 40 is set to
_While holding the address signal designating the address _H , the flag 41 is cleared.

[0046] Next, a read access to 00FF _H address. Thus, if the address processing unit 20 is normal, the address value of 7FFE _H is output as data from the latch circuit 40 and the flag 41 is set.

On the other hand, when the address processing unit 20 has a failure and changes the address output from the CPU 12, the latch circuit 40 holds a value other than 7FFE _H , so that 7FFE _H Is not output as data.

[0048] Accordingly, next, 0002 _H address (writing), 00FF _H address (read), 7FFD _H address (writing), 00FF _H address (read), 0004 _H address (writing), 00FF _H address (read), 7FFB _H address (write), 00FF _H address (read), 0008 _H address (write), 00FF _H address (read), 7FF7 _H address (write), 00FF _H address (read), 0010 _H address (write), 00FF _H address (read), 7FEF _H address (writing), 00FF _H address (read), ···, 4000 _H address (writing), 00FF _H address (read), BFFF _H address (writing), 00FF _H address (read ) Are sequentially written or read.

By doing so, it is determined whether or not there is a failure in which the address processing unit 20 of the interface circuit 19 changes the value of a specific bit of the address signal from “1” to “0”. It is possible to test whether there is a failure that changes from “0” to “1”.

As described above, in the first embodiment,
Since the test of the address processing unit 20 can be performed without previously writing different data to addresses other than the address of interest, the test time of the address processing unit 20 of the interface circuit 19 can be reduced.

Further, according to the first embodiment, even when manufacturing series products in which circuits connected to the time division bus 16 are different, it is not necessary to create a different test pattern for each series product. Can be shared by series products, so that the cost can be reduced by reducing the development cost.

In the first embodiment, the setting of the flag 41 is controlled by the address decoder 39. However, the setting of the flag 41 may be controlled by software.

In the first embodiment, the access to the target address is performed by the write operation. Alternatively, the access to the target address may be performed by the read operation.

In the first embodiment, the independent bus 13
The description has been made on the assumption that the number of bits of the data bus 15 and the number of bits of the time-division bus 16 are the same.
In the embodiment, when the number of bits of the data bus 15 of the independent bus 13 is larger than the number of bits of the time division bus 16, for example, when the data bus 15 of the independent bus 13 is 32 bits and the time division bus 16 is 16 bits Can also be applied.

That is, in this case, among the 32-bit address signals to be output from the CPU 12, the previously output 16-bit address signal is used to specify the address of the latch circuit 40. 00FF _H, and the 16-bit signal output later is latched by the latch circuit 4.
A similar test can be performed by setting the content to be held at 0.

(Second Embodiment FIG. 4) FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention. In the second embodiment, an address signal provided in the first embodiment is provided. Holding circuit 38
Instead of the address signal holding circuit 4 having a different circuit configuration.
5 are provided, and the others are configured in the same manner as in the first embodiment.

In the address signal holding circuit 45, reference numerals 46 and 47 denote latch circuits.
Are configured and controlled so that when an address signal is output from the interface circuit 19 to the time division bus 16, this is latched.

That is, in the second embodiment, when an address signal is output from the interface circuit 19 to the time division bus 16, the latch circuit 46 latches the address signal, and in the next cycle, the contents of the latch circuit 46 are changed. When the data is latched by the latch circuit 47 and the read access is performed to the latch circuit 47, the contents of the latch circuit 47 are output to the time division bus 16 and the address signal designating the latch circuit 47 is latched by the latch circuit 46. Is done.

Therefore, according to the second embodiment,
As in the case of the first embodiment, the test time of the address processing unit 20 of the interface circuit 19 can be shortened, and the test pattern can be shared. Reduction can be achieved.

According to the second embodiment, the address signal holding circuit 45 has a simpler circuit configuration than the address signal holding circuit 38 provided in the first embodiment. Simplification can be achieved.

(Third Embodiment FIG. 5) FIG. 5 is a circuit diagram showing a main part of a third embodiment of the present invention. In the third embodiment, address signals provided in the first embodiment are provided. Holding circuit 38
Instead of the address signal holding circuit 4 having a different circuit configuration.
9 are provided, and the others are configured in the same manner as in the first embodiment.

Here, in the address signal holding circuit 49, reference numeral 50 denotes a latch circuit.
When an address signal is output from the interface circuit 19 to the time division bus 16, the address signal is latched.
The output terminal is controlled by the data bus 15.
It is connected to the.

That is, in the third embodiment, when an address signal is output from the interface circuit 19 to the time-division bus 16, the latch circuit 50 latches the address signal. Data bus 15
Is output to

Therefore, according to the third embodiment,
As in the case of the first embodiment, the test time of the address processing unit 20 of the interface circuit 19 can be shortened, and the test pattern can be shared. Reduction can be achieved.

According to the third embodiment, the address signal holding circuit 49 has a simpler circuit configuration than the address signal holding circuit 45 provided in the second embodiment. Can be simplified.

[0066]

According to the present invention, an address signal for making a write access to the address signal holding means is held by the address signal holding means, and the held address signal is read, whereby the interface circuit can be implemented. The constituent address processing units can be tested, and since it is not necessary to write different data in advance to addresses other than the address of interest, the test time of the address processing unit of the interface circuit can be reduced.

Further, according to the present invention, since it is not necessary to write different data in advance to addresses other than the address of interest, even when a series product having a different circuit connected to the time-division bus is manufactured, a series product can be manufactured. There is no need to create a different test pattern for each product, the test patterns can be shared for series products, and the cost can be reduced by reducing development costs.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the address signal holding circuit provided in the first embodiment of the present invention.

FIG. 3 shows a first embodiment of the present invention;
FIG. 5 is a diagram showing an address signal output from a.

FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 A31-A0 Address D31-D0 Data

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-57122 (JP, A) JP-A-4-69756 (JP, A) JP-A-2-104450 (JP, U) (58) Survey Field (Int.Cl. ⁷ , DB name) G06F 11/22 330 G06F 13/00 301 G11C 11/413

Claims (2)

(57) [Claims] 1. An address bus and a data bus which are independent of each other and which are connected to the CPU and an address bus and a data bus which are independent of each other. A time-division bus that is not directly connected to the CPU; and an interface circuit that connects the independent bus and the time-division bus. A semiconductor integrated circuit comprising address signal holding means capable of holding the output address signal in a readable manner by the CPU. 2. The method according to claim 1, wherein said address signal holding means is configured to readably hold an address signal output from said interface circuit to said time-division bus to an address bus of said independent bus. The semiconductor integrated circuit according to claim 1.