JP2002108641A - Trace circuit, memory testing method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily generate an optional piece of bit pattern data for test to be used for a memory test of a FIFO memory. SOLUTION: In this trace circuit 1 to output trace data of a CPU, a FIFO memory 20 as a memory for output adjustment to adjust timing of output of the trace data and a developing device 11 to convert access data of the CPU into bit width for one word of the FIFO memory and to generate the bit pattern data for test to be used for the test of the FIFO memory are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tracing device having a memory test support function, a memory test method thereof, and a computer-readable recording medium storing a program for causing a computer to perform the function, and more particularly, to a trace data storage method. The present invention relates to a trace device that supports a memory test of a FIFO memory that adjusts output timing, a memory test method, and a computer-readable recording medium that stores a program that causes a computer to perform the function.

[0002]

2. Description of the Related Art FIG. 4 shows a CPU (Central Processing Unit).
microcomputer 1 having a trace circuit 101 for outputting trace data of nit (central processing unit) 102
FIG. 2 is a block diagram showing the basic configuration of the 00.

The microcomputer 100 has a CPU 1
02, an instruction bus 103 for transmitting instruction information of a program executed by the CPU 102, a data bus 104 for transmitting information of data to be processed, and a trace circuit 101 for outputting trace data of the CPU 102 to an ICE (In Circuit Emulator). The trace circuit 101 outputs a trace data generation circuit 110 for generating trace data, a FIFO memory 130 which is a two-port RAM (Random Access Memory) for adjusting the output timing of the trace data, and a signal output from the FIFO memory 130. A trace data output circuit 140 for outputting trace data to the ICE, a data write bus 150 for transmitting the generated trace data, and a data read bus 1
60.

FIG. 5 is a block diagram showing a configuration of the trace data generation circuit 110. The trace data generation circuit 110 includes an instruction address bus 103a forming the instruction bus 103, a data address bus 104a and an access data bus 104b forming the data bus 104, a control circuit 113 for determining the generation timing of the trace data and the format of the trace data, Encoder 112 for generating trace data, write pointer 114 for providing a write address of trace data, trace data write address output bus 151 for transmitting a write address of trace data to FIFO memory 130, and trace data output bus for transmitting trace data 152.

In the trace circuit 101, the CPU 102
When tracing the processing operation, the control circuit 11
3, the encoder 112 controls the CPU 1
The trace data is generated from the instruction address information, the data address information, and the access data indicating the processing operation of No. 02. The generated trace data is stored in the write pointer 114
Is set by sequentially incrementing
Are sequentially stored at the write address of the O memory 130,
The trace data stored in the FO memory 130 is output from the trace data output circuit 140 in the order of storage.
Output to E.

In one of the manufacturing tests of the trace circuit 101, a dedicated test terminal is provided in the FIFO memory 130, and a latch or the like in the FIFO memory 130 is set to a predetermined value by using this terminal. For each setting condition, there is a scan-type memory test for sequentially testing the FIFO memory 130.

However, in the case of performing a memory test by the scan method, in the scan method, a condition setting for a latch or the like in the FIFO memory 130 can be performed only at a bit rate per clock, so that the test time increases. There is a problem.

Therefore, as a memory test method that does not cause such a problem, the CPU 102 causes the encoder 112 to execute an operation of generating bit pattern data for testing such as 0x55 and 0xAA, and the generated testing bit pattern data is generated. The bit pattern data is written to the FIFO memory 130, and then the test bit pattern data read from the FIFO memory 130 is checked.
The FIFO memory 1 depends on whether the test bit pattern data matches the expected bit pattern data.
In some cases, a test method of performing a pass / fail judgment of 30 is taken.

[0009]

However, the encoder 1
The trace data generation operation performed by the CPU 12 is not under the direct control of the CPU 102, and the data address information, access data, and additional bits necessary for distinguishing between read and write of the access data are complexly arranged. It is something. Therefore, in the conventional trace circuit 101, in order to generate the specific test bit pattern data, the CPU 102 needs to control the encoder 1 that is not under its control.
Taking into account the complicated operation of T.12, an instruction must be given to the encoder 112 so that the encoder 112 can output specific test bit pattern data. There was a problem that it was very difficult.

[0010] The present invention has been made in view of the above points, and a trace apparatus and a memory test method capable of easily generating arbitrary test bit pattern data used for a memory test of a FIFO memory. It is another object of the present invention to provide a computer-readable recording medium storing a program for causing a computer to perform the function.

[0011]

According to the present invention, in order to solve the above-mentioned problems, in a trace circuit 1 for outputting trace data of a CPU in FIG. 1, an output timing adjusting circuit for adjusting an output timing of the trace data is provided. The FIFO memory 20 as a memory and the access data of the CPU are converted into a bit width of one word of the output timing adjustment memory, and test bit pattern data used for a memory test of the output timing adjustment memory is generated. A trace circuit is provided, comprising: a deployer 11;

Here, the expander converts the access data of the CPU to a bit width of one word of the output timing adjustment memory, and generates test bit pattern data used for a memory test of the output timing adjustment memory.

Further, in a memory test method of an output timing adjusting memory for adjusting an output timing of the generated trace data, the access data of the CPU is converted into a bit width of one word of the output timing adjusting memory. A memory test method is provided, wherein test bit pattern data used for a memory test of an output timing adjustment memory is generated.

By doing so, it is possible to generate the test bit pattern data from the access data of the data write processing to the user memory space performed by the CPU.

Further, the computer has a function of converting access data of the CPU into a bit width of one word of the output timing adjustment memory and generating test bit pattern data used for a memory test of the output timing adjustment memory. A computer-readable recording medium storing a program to be executed is provided.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a trace circuit 1 which is a trace device in the present embodiment.

The trace circuit 1 generates a trace data, stores the trace data in the provided write address, outputs the trace data in the stored order, and adjusts the output timing of the trace data. F which is an output timing adjustment memory to be adjusted
It comprises an IFO memory 20 and a trace data output circuit 30 for outputting trace data to the ICE.

Here, the trace data generating circuit 10 mainly includes an encoder 12 for generating trace data from instruction address information, data address information, and access data, which are processing information of the CPU as a central processing unit, and a timing for generating trace data. And a control circuit 13 for determining the format of the trace data, a write pointer 14 for providing a write address of the generated trace data, and converting the access data of the central processing unit into a bit width of one word of an output timing adjustment memory and outputting the converted data. It is composed of an expander 11 for generating test bit pattern data used for a memory test of the timing adjustment memory, a selector 15 for selecting a method of specifying a write address, and a register 16 for indicating that the trace circuit 1 is in a memory test mode. Have been.

The encoder 12 transmits an instruction address bus 17a having a bus width of 32 bits for transmitting instruction address information of a program executed by the CPU, and data address information indicating a source address or a write destination address of data handled by the CPU. It is electrically connected to the CPU via a data address bus 17b having a bus width of 32 bits, and via the expander 11 and an access data bus 17c having a bus width of 32 bits for transmitting access data as data contents to be read or written. It is connected. Further, the encoder 12 receives the write pointer 14 via the control circuit 13 and the F pointer via the trace data output bus 17e having a bus width of 69 bits for transmitting the trace data.
The write pointer 14 is electrically connected to the IFO memory 20, and the write pointer 14 is connected to the selector 15, the selector 15 is connected to the register 16 and the expander 11, and the data address bus is connected via a selector connection data address bus 17 ba having a bus width of 16 bits. 17b, and further electrically connected to the FIFO memory 20 via a trace data write address output bus 17d having a bus width of 16 bits for transmitting a write address. Also, FIFO memory 2
0 is the trace data output circuit 30, and the trace data output circuit 30 is electrically connected to the data address bus 17b, the access data bus 17c, and the ICE, respectively.

The encoder 12 is an encoder having a plurality of input terminals and output terminals. The encoder 12 converts instruction address information, data address information, and access data input from the input terminals into predetermined trace data, and converts the trace data. Output from the output terminal.

The control circuit 13 controls the timing at which the encoder 12 generates trace data (for example, the encoder 1
2, when data address information and access data are input in conflict, which data has priority, etc.), the format of trace data to be generated (format for converting all instruction addresses input to the encoder 12 into trace data) Or only the branch point on the program and the difference information from the branch point to the jump destination on the program are converted into trace data).

The write pointer 14 provides a write address on the FIFO memory 20 for storing the generated trace data. Specifically, the write pointer 14 is made to correspond to each trace data and to be sequentially incremented. The determined write address is provided as a write address of the trace data.

Register 16 is formed of a flip-flop circuit, and indicates that trace circuit 1 is in a memory test mode. The selector 15 sets the write address of the FIFO memory 20 using the write address provided by the write pointer 14, or uses an address provided from a part of a data address bus for transmitting data address information of access data. This is an element for selecting whether to set.

The FIFO memory 20 is a so-called two-port RAM, which stores trace data input from an input terminal and outputs the stored trace data from an output terminal in the order in which the data is stored. The output timing of is adjusted. In the present embodiment, a 69-bit, 128-word FIFO memory 20 is used as an example.

The trace data output circuit 30 has a FIFO
The trace data generated in the memory 20 is output to the ICE. FIG. 2 is a diagram exemplifying a format of trace data written in the FIFO memory 20.

FIG. 2 shows the format of trace data in a special format, which is special data such as at the time of instruction tracing, at the time of data tracing, and indicating a break in trace data. The trace data is 69-bit data as a whole. Specifically, in the case of the trace data at the time of instruction tracing, 0 to 31 bits indicate the instruction address of the branch destination of the executed program by 3 bits.
2 to 47 bits indicate the number of executed instructions between branch instructions by 6
Bits 6 to 68 indicate that the instruction trace data is output. In the case of trace data at the time of data tracing, the access data on the data bus is 0 to 31 bits, the data address is 32 to 63 bits, and the data read / write type is 65 bits. The access type is 66 or 67 bits.
Each data size of the access data is shown.
0 to 31 for trace data in special format
Up to the bit, the instruction address that started the trace is 3
Bits 2 to 47 indicate the number of instructions executed from the branch instruction immediately before the break to the break, 64 and 65 bits indicate the data type, and 66 to 68 bits indicate the special format.

Next, the trace operation of the trace circuit 1 will be described with reference to FIG. First, the instruction trace operation will be described. When the instruction address is transmitted to the encoder 12 via the instruction address bus 17a with the execution of the user program, the encoder 12 generates trace data using the instruction address. The generation of the trace data is performed according to the instruction of the control circuit 13,
Here, the generation of the trace data is performed by extracting the instruction address of the branch destination and the number of executed instructions between the branch instructions from the transmitted instruction address, and transmitting the information and the like to the 69-bit data as shown in FIG. This is done by arranging in bit width.

At this time, the control circuit supplies a control signal to the write pointer 14, and the write pointer 14 receiving the control signal increments the write address by one and stores the generated trace data. A write address is set, and the set write address is provided to the FIFO memory 20 via a trace data write address output bus 17d having a bit width of 16 bits. In addition,
Since the FIFO memory 20 has 128 words, only the lower 7 bits of the 16-bit address on the trace data write address output bus 17d are actually used for providing the write address.

On the other hand, the trace data generated by the encoder 12 as described above is sent to the FIFO memory 20 via the trace data output bus 17e having a bit width of 69 bits, and the FIFO memory 20 converts the sent trace data. , At the write address provided by the write pointer 14.

The trace data stored in the FIFO memory 20 is sequentially stored in the FIFO memory 2 in the order of storage.
It is read from 0 and output to the ICE via the trace data output circuit 30.

At the time of data tracing, the encoder 12
Generates trace data using the data address information transmitted by the data address bus 17b and the access data transmitted by the access data bus 17c. As in the case of the instruction trace, the generation of the trace data is performed in accordance with the instruction of the control circuit 13, and the generation of the trace data here includes the transmitted data address information, access data, and access type shown in FIG. As described above, this is performed by arranging the bit width of 69 bits. The following operation is the same as in the instruction trace operation.

Next, the operation of the trace circuit 1 when the FIFO memory 20 is used as a trace memory will be described. When the FIFO memory 20 is used as a trace memory, the trace data output circuit 30 does not operate during execution of the user program, and the FIFO memory 20 performs only writing of the trace data and does not output the trace data. At this time, the FIFO memory 20 may have a ring buffer structure, and the tracing operation may be continued until the execution of the user program is broken by a user request, or when the FIFO memory 20 becomes full. May be sent to the CPU to forcefully stop the running user program.

After the execution of the user program is broken, the trace data stored in the FIFO memory 20 is read out to the CPU through the trace data output circuit 30 by executing the emulator program. Specifically, the execution of this emulator program causes the CPU to output predetermined data address information to data address bus 17b,
The data address information output to b is input to the input terminal of the FIFO memory 20 as an address output via the trace data output circuit 30. The FIFO memory 20 to which the address output is input outputs the trace data stored in the FIFO memory 20 to the trace data output circuit 30, and the trace data output circuit 30 outputs the trace data from the output 69-bit trace data. The 32-bit access data corresponding to the data address information of the address output is selected, and is selected via the access data bus 17c.
Output to CPU. The trace data output to the CPU is output to the ICE by the tool bus.

Next, a memory test operation of the FIFO memory 20 in the trace circuit 1 will be described. When the memory test is performed, first, the register 16 is set by executing the emulator program in the emulator mode, and an instruction is given to switch the trace circuit 1 to the memory test mode. In response to this instruction, the selector 15 does not provide the write address generated by the write pointer 14 to the FIFO memory 20, but uses a part of the address of the data address bus 17b as a write address for writing the test bit pattern data. Provided to the memory 20. In this case, for example, the selector connection data address bus 17ba is connected to the data address bus 1
If the bit 7b is connected to the 0 to 15 bit portion and not connected to the 16 to 31 bit portion, the address 0 to 0xFFFF is provided as the write address.

When the trace circuit 1 enters the memory test mode, the mode is switched to the user mode for executing the user program, and the test bit pattern data is written into the FIFO memory 20.

The writing of the test bit pattern data in the trace circuit 1 is performed by writing the trace data generated as a result of tracing the execution of the user program as the test bit pattern data. Specifically, an appropriate 64 KB user memory space which does not affect other circuits even when writing arbitrary data is selected, and the CPU is executed by executing the user program.
Writes arbitrary data into this user memory space,
The access data at that time is fetched from the access data bus 17c into the expander 11, and the test bit pattern data generated by expanding the fetched access data is transferred to the selector connection data address bus 17ba.
Is connected to a portion of data address bus 17b having a bit width of 32 bits.
Write to the write address of the FO memory 20.

The generation of the test bit pattern data here is performed by converting the access data having a bit width of 32 bits transmitted through the access data bus 17c into a FIFO.
This is performed by expanding the data into 69 bits, which is the bit width of one word of the memory 20.

FIG. 3 shows test bit pattern data 42 by expanding access data 41 in this manner.
FIG. 5 is a diagram showing a state in which is generated. Here, the access data 41 and the test bit pattern data 42
Indicate the bit number in each data.

As shown in FIG. 3, the expander 11 arranges the access data 41 having a bit width of 32 bits in an area 42a of 0 to 31 bits and an area 42b of 32 to 63 bits. The access data 41 is expanded by arranging the data of the area 41a of 0 to 4 bits in the access data 41 in the area 42c.

As such test bit pattern data, for example, when 0x555555555 is written to an odd address from address 0 of the FIFO memory 20 and 0xAAAAAAAA is written to an even address, a checkered pattern is stored in the FIFO memory 20. Are arranged.

When the writing of the test bit pattern data to the entire area of the FIFO memory 20 is completed, the mode returns to the emulator mode again, and the above-described FIFO memory 20 is returned.
Is used as the trace memory.
By reading the test bit pattern data in the O memory 20 and checking whether the read test bit pattern data is the expected data,
The quality of the O memory 20 is determined.

As described above, in the present embodiment, the access data of the CPU is converted into the bit width of one word of the FIFO memory 20, and the test bit pattern data used for the memory test of the FIFO memory 20 is generated.
When the CPU writes data to an address in the user memory space, test bit pattern data can be generated from the access data, and arbitrary test bit pattern data can be easily generated.

In the present embodiment, the writing of the test bit pattern data to the FIFO memory 20 at the time of the memory test is performed not by a write command by an emulator program supplied from the ICE using a tool bus having a narrow bus width. Since the execution of the user program supplied from the external bus terminal having a wide bus width is performed as a result of tracing, the writing process of the test bit pattern data can be accelerated, and the test time can be reduced. It becomes possible.

The above processing functions can be realized by a computer. In this case, the processing contents of the functions that the trace circuit 1 should have are described in a program recorded on a computer-readable recording medium. Then, by executing this program on a computer, the above processing is realized on the computer. Computer-readable recording media include magnetic recording devices and semiconductor memories. To distribute the program to the market, the program is stored and distributed on a portable recording medium such as a CD-ROM (Compact Disk Read Only Memory) or a floppy (registered trademark) disk, or stored in a computer connected via a network. It can also be stored in the device and transferred to another computer via a network. When the program is executed by the computer, the program is stored in a hard disk device or the like in the computer, and is loaded into the main memory and executed.

In this embodiment, the expander 11 expands the access data to the bit width of the FIFO memory 20 to generate the test bit pattern data. , FIF
When the number of bits per word of the O memory 20 is small or the same, the test bit pattern data may be generated without expanding the access data.

[0046]

As described above, according to the present invention, the CPU
Is converted to a bit width of one word of the output timing adjustment memory, and test bit pattern data used for a memory test of the output timing adjustment memory is generated. Generation can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a trace circuit.

FIG. 2 is a diagram illustrating a format of trace data written to a FIFO memory;

FIG. 3 is a diagram showing how test bit pattern data is generated by expanding access data.

FIG. 4 is a block diagram showing a basic configuration of a microcomputer having a trace circuit that outputs trace data of a CPU.

FIG. 5 is a block diagram showing a configuration of a trace data generation circuit.

[Explanation of symbols]

 1, 101 trace circuit 10, 110 trace data generation circuit 11 expander 12, 112 encoder 13, 113 control circuit 14, 114 write pointer 15 selector 16 register 17a instruction address bus 17b data address bus 17c access data bus 17d trace data write address Output bus 17e Trace data output bus 20, 130 FIFO memory 30, 140 Trace data output circuit 41 Access data 42 Test bit pattern data

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G11C 29/00 653 G01R 31/28 B 657 M Q F Term (Reference) 2G032 AA07 AC03 AC10 AD06 AG02 AG07 AG10 AK16 5B018 GA03 HA22 JA12 NA10 QA13 5B042 GA13 GC08 HH17 HH30 MA08 MA13 MC03 MC09 5B048 AA19 CC02 DD05 5L106 AA11 DD22

Claims (9)

[Claims] 1. A trace circuit for outputting trace data of a CPU, comprising: an output timing adjustment memory for adjusting an output timing of the trace data; and an access timing data of the CPU for one word of the output timing adjustment memory. A developing circuit that converts the bit width into a bit width and generates test bit pattern data used for a memory test of the output timing adjustment memory. 2. The bit width of one word of the output timing adjustment memory is wider than the bit width of the access data, and the expander stores the access data in the output timing adjustment memory during the memory test. 2. The trace circuit according to claim 1, wherein the bit width is extended to a bit width of one word. 3. The CPU writes arbitrary data into a predetermined user memory space during the memory test, and the access data is access data when the arbitrary data is written into the user memory space. The trace circuit according to claim 1, wherein: 4. A write address of the output timing adjustment memory for writing the test bit pattern data during the memory test is provided from a part of a data address bus for transmitting data address information of the access data. 2. The trace circuit according to claim 1, wherein the trace circuit is an address. 5. The trace circuit according to claim 1, wherein the test bit pattern data is written into the output timing adjustment memory as a result of tracing execution of a user program. 6. A memory test method for an output timing adjustment memory for adjusting output timing of generated trace data, comprising: converting access data of a CPU into a bit width of one word of the output timing adjustment memory; A memory test method, wherein test bit pattern data used for a memory test of an output timing adjustment memory is generated. 7. The CPU writes arbitrary data in a predetermined user memory space at the time of the memory test, and determines that the access data is access data at the time of writing the arbitrary data to the user memory space. 7. The memory test method according to claim 6, wherein: 8. The memory test method according to claim 6, wherein the test bit pattern data is written to the output timing adjustment memory as a result of tracing execution of a user program. 9. Converting the access data of the CPU into a bit width of one word of the output timing adjusting memory,
A computer-readable storage medium storing a program for causing a computer to perform a function of generating test bit pattern data used for a memory test of the output timing adjustment memory.