JP2007287218A - Memory interface circuit, and memory test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate the determination of an interface circuit in a memory operation test. <P>SOLUTION: The memory interface circuit 1 is provided with: a first holding part 18 for holding write data generated by a memory controller; a delay part 10 for delaying read data generated by the memory controller 2 by a time corresponding to write delay of a memory and outputting it; a read timing signal generating part 15 for generating a read timing signal indicating that the read data is being output to the memory; a read timing control part 9 outputting read data delay-output by the delay part 10 in synchronization with the read timing signal generated by the read timing signal generating part 15; a second holding part 19 for holding read data output by the read timing control part 9; and a determination part 12 for determining whether write data held in the first holding part 18 is matched with read data held in the second holding part 19 or not. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory interface circuit and a memory test apparatus, and more particularly to a memory interface circuit that performs a memory interface test easily and at high speed, and a memory test apparatus equipped with the memory interface circuit.

  For a memory that operates at high speed, a memory test is required to determine whether the memory read and write operations are normal. A memory test apparatus that performs the memory test performs a memory interface test in order to test an interface between the memory and an external circuit of the memory.

  As shown in FIG. 2, the memory test apparatus 50 includes a memory socket 52 for inserting and removing the memory 51 on a circuit board, and a memory test unit 54 connected to the memory socket 52 via a terminal 53. The memory test unit 54 performs interface control for accessing the memory 51. The memory test unit 54 generates a data signal and a timing control signal for reading and writing data, and outputs from the memory 51. And a memory interface circuit 56 that determines the operation by synchronizing the strobe signal and the read data with the internal clock. The operator performs the memory test by connecting the memory 51 and the memory test unit 54 and monitoring the terminal 53 between the memory interface circuit 1 and the memory 51.

For example, Patent Document 1 discloses a technique for performing synchronization of a signal taken from a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) with high accuracy and stability.
JP 2005-78547 A

  However, as shown in FIG. 2, the memory test unit 54 adjusts the read / write timing using the external device 57 of the memory 51 when testing the read / write operation of the memory 51. There is a problem that it is difficult to test a high-speed interface signal between the interfaces 1. The price of a measuring instrument that can be used for a high-speed operation test is very expensive, and it is difficult to obtain an environment for a memory test using an expensive measuring instrument.

  Further, the test method using the conventional technique is to test the operation of the memory 51 in a state where the memory 51 and the memory interface 1 are connected. Therefore, there is a problem that it is difficult to test a high-speed interface signal.

  In view of such circumstances, the present invention provides a memory that can quickly and easily determine whether or not the interface between the memory and the memory controller is normal in a memory operation test that performs high-speed read / write operations. An interface circuit and a memory test apparatus are to be provided.

  In order to achieve the above object, a memory interface circuit according to the present invention is a memory interface circuit used in a memory test apparatus that performs a memory operation test under the control of a memory controller, and holds write data generated by the memory controller. A first holding unit, a delay output unit that outputs the read data generated by the memory controller to the read timing control unit by delaying a time corresponding to a write delay of the memory, and the read data is output to the memory A read timing signal generating unit that generates a read timing signal indicating that the read timing signal is present; and the read timing that the delay output unit delays and outputs the read data to the second holding unit in synchronization with the read timing signal Output from the control unit and the read timing control unit Determining whether the second holding unit holding the read data, the write data held in the first holding unit, and the read data held in the second holding unit match The first feature is that a determination unit is provided.

  The memory test apparatus of the present invention is a memory test apparatus having a memory controller and a memory interface circuit for performing a memory operation test under the control of the memory controller, wherein the memory controller receives write data and read data. A data generation unit that generates the first holding unit that holds the write data generated by the data generation unit; and the read data generated by the data generation unit corresponds to a memory write delay. A delay output unit that delays the time and outputs the read timing control unit; a read timing signal generation unit that generates a read timing signal indicating that the read data is being output to the memory; and the delay output unit The read data that has been delayed is used as the read timing signal. The read timing control unit that outputs to the second holding unit in synchronization with the read timing control unit, the second holding unit that holds the read data output from the read timing control unit, and the write that is held in the first holding unit A second feature is provided with a determination unit that determines whether or not the data matches the read data held in the second holding unit.

  The memory test apparatus according to the second aspect of the invention is characterized in that, in the second feature, the memory interface circuit includes a command analysis unit that analyzes a read command and a write command related to read / write of the memory output from the memory controller. In the third feature, the memory controller includes a timing control unit that sets the time in the delay output unit, in the second feature or the third feature.

  According to the memory interface circuit of the present invention, the function check operation can be performed quickly and easily, and the interface can be increased in speed.

  According to the memory test apparatus of the present invention, since the labor of an operator who connects the memory to be tested is reduced, the work efficiency required for the test is improved. Further, a memory test can be performed without using a conventional separation type test method that requires an expensive measuring instrument, which contributes to a reduction in cost required for the test.

Hereinafter, an embodiment of a memory test apparatus according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram for explaining the configuration of a memory test apparatus according to an embodiment of the present invention.
<Configuration>
As shown in FIG. 1, the memory test apparatus according to the present embodiment includes a memory controller 2 that outputs data to be written to a memory (not shown), a read command and a write command related to reading and writing to the memory, and a memory under control of the memory controller 2. And a memory interface circuit 1 for performing the operation test.

  The memory controller 2 includes a command generation unit 16, a delay time setting unit 17, and a read data / write data generation unit (data generation unit) 13. Here, the command generation unit 16 generates, for example, CAS (Column Address Strobe signal), RAS (Row Address Strobe Signal), and the like. Note that the command generation unit 16 may generate data for specifying a memory bank and memory address, such as chip enable, as a command. The memory controller 2 writes and sets data such as CAS in the memory interface circuit 1 as a read command and a write command.

  The delay time setting unit 17 sets a delay time of read data in a buffer in the memory interface circuit 1 described below. The delay time setting unit 17 changes the timing of the read test output data by this setting. The read data / write data generation unit 13 generates read data and write data.

  The memory interface circuit 1 according to the present embodiment is used in a memory test apparatus 3 that performs an operation test of a memory that operates at high speed, such as a DDR-SDRAM, under the control of the memory controller 2, and the operation of the memory interface is normal. It also has a function to determine whether or not. The memory interface circuit 1 includes a read data / write data storage unit (data storage unit) 14, a comparison data holding unit 8, a buffer (delay output unit) 10, a read control signal / write control signal generation unit 15, and a read The timing control unit 9 includes a read data / write data comparison unit (determination unit) 12, a read command / write command analysis unit 11, and a clock generation unit 21.

  The read data / write data storage unit 14 temporarily stores read data and write data generated by the memory controller 2.

  The comparison data holding unit 8 holds read data, write data, a read command, and a write command, and an R data holding unit (first holding) that holds write data stored in the read data / write data storage unit 14. Section) 18 and a W data holding section (second holding section) 19 that holds read data output from the read timing control section 9 described below. The comparison data holding unit 8 includes a command holding unit 20 that holds a read command and a write command from the memory controller 2.

  Each of the comparison data holding unit 8 and the read data / write data storage unit 14 includes a plurality of registers.

  The buffer 10 outputs the read data generated by the memory controller 2 to the read timing control unit 9 by delaying a time corresponding to a write delay of a memory (not shown) to be tested. The magnitude of this delay time is made substantially equal to the turnaround time required for transmitting read data from the buffer 10 to the memory under test.

  The read control signal / write control signal generation unit 15 generates a read timing signal indicating that read data is being output to the memory, and functions as a read timing signal generation unit. The read control signal / write control signal generation unit 15 writes the read data and write data generated in the memory controller 2 in the read data / write data storage unit 14. The read control signal / write control signal generation unit 15 also performs control to write the write data stored in the read data / write data storage unit 14 to the comparison data holding unit 8.

  The read timing control unit 9 outputs the read data delayed output from the buffer 10 to the W data holding unit 19 in synchronization with the read timing signal. The read timing control unit 9 shifts the phase of the read timing signal from the read control signal / write control signal generation unit 15, and the read timing signal phase-shifted by the phase shift unit 23 with the buffer 10 And a synchronization processing unit 22 for synchronizing with the read data transferred to the comparison data holding unit 8.

  The read data / write data comparison unit 12 determines whether or not the write data held in the R data holding unit 18 matches the read data held in the W data holding unit 19. Here, the fact that the write data and the read data match means that the bit values or logics of the write data such as 32 bits and the read data such as 32 bits match.

The read command / write command analysis unit 11 analyzes a read command and a write command related to read / write of the memory output from the memory controller 2.
The clock generation unit 21 supplies a common high-speed clock to each unit of the memory interface 1.
The functions of the read control signal / write control signal generation unit 15, the read timing control unit 9, the read data / write data comparison unit 12, and the read command / write command analysis unit 11 are all LSI (Large Scale Integration). CPU (Central Processing Unit), ROM (Read Only Memory), RAM and the like.
<Operation>

  With the above-described configuration, the memory controller 2 sets CAS latency or the like as the delay time of the buffer 10 in advance. Here, CAS latency is a time representing a clock difference between a clock at which the CAS signal is transmitted and a clock at which the first data is transmitted / received. The memory controller 2 according to the present embodiment switches the test output timing of the read data by setting the delay time when outputting the read command.

  The memory interface circuit 1 sets the delay time in the buffer 10. After this setting, the memory interface circuit 1 delays the read data output from the read data / write data storage unit 14 in the buffer 10 and transfers the delayed read data to the comparison data holding unit 8.

  The memory controller 2 generates read data and write data for testing, generates read commands and write commands, and outputs these read data, write data, read commands, and write commands to the memory interface circuit 1 To do. The memory interface circuit 1 stores read data and write data in the read data / write data storage unit 14.

  Here, in the memory interface circuit 1, the read command / write command analysis unit 11 analyzes a command input from the read control signal / write control signal generation unit 15, and determines that the command is a read command and a write command. In this case, the read command and the write command are written in the comparison data holding unit 8, respectively.

  Subsequently, the memory interface circuit 1 writes the write data stored in the read data / write data storage unit 14 to the W data holding unit 19 and reads the read data stored in the read data / write data storage unit 14. Write to buffer 10.

  Next, when a read command is input, the memory interface circuit 1 reads the read data from the buffer 10 at a preset delay timing and adjusts the phase of the read timing signal such as the strobe signal to read data. The read data and the read timing signal are written in the comparison data holding unit 8 in synchronization with the above. In other words, the memory interface circuit 1 wraps the read data from the read data / write data generation unit 14 in the buffer 10 and adjusts the timing of the read timing signal in the read timing control unit 9, so that the comparison data holding unit 8 is transferred. That is, the read data is looped back in the memory interface circuit 1.

  Then, the read data / write data comparison unit 12 compares the read data and the write data held in the comparison data holding unit 8 and outputs a test result indicating the match or mismatch of the read data and the write data. Thereby, the memory interface circuit 1 can know whether or not the memory interface operation is normal.

  As described above, the memory test apparatus 3 according to the present embodiment does not require a test performed by connecting a measuring instrument to a terminal (not shown) of the memory interface circuit 1 for a memory that operates at high speed such as a DDR-SDRAM.

  In addition, the memory interface circuit 1 pseudo-realizes reception of read data and a read timing signal output from a memory that is not connected by loop-back transfer of read data in the interface device 1. Therefore, the memory interface circuit 1 according to the present embodiment can easily confirm the memory interface by comparing the write data transferred inside the memory interface circuit 1 and the read data transferred in a loopback manner.

  The memory interface circuit 1 according to the present embodiment can operate even when connected to the memory 51 as in the memory interface circuit 56 (FIG. 2). In this case, the memory interface circuit 1 can self-check whether or not the operation of the memory 51 is normal.

  According to the memory interface circuit and the memory test apparatus of the present invention, the reliability of an LSI including a memory element that operates at high speed can be realized at low cost, and the test can be simplified.

The figure for demonstrating the structure of the memory test apparatus which concerns on one Embodiment of this invention. The figure for demonstrating the conventional memory test apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory interface circuit, 2 ... Memory controller, 3 ... Memory test apparatus, 8 ... Comparison data holding part, 9 ... Read timing control part, 10 ... Buffer (delay output part), 11 ... Read command / write command analysis part, DESCRIPTION OF SYMBOLS 12 ... Read data / write data comparison part (determination part), 13 ... Read data / write data generation part (data generation part) 14 ... Read data / write data storage part (data storage part), 15 ... Read control signal / write Control signal generation unit, 16 ... command generation unit, 17 ... delay time setting unit, 18 ... R data holding unit (first holding unit), 19 ... W data holding unit (second holding unit), 20 ... command holding unit, 21: Clock generation unit, 22: Synchronization processing unit, 23: Phase shift unit.

Claims (4)

A memory interface circuit used in a memory test apparatus for performing a memory operation test under the control of a memory controller,
A first holding unit for holding write data generated by the memory controller;
A delay output unit that outputs the read data generated by the memory controller to the read timing control unit by delaying a time corresponding to a write delay of the memory;
A read timing signal generating unit that generates a read timing signal indicating that the read data is being output to the memory;
The read timing control unit for outputting the read data delayed output by the delay output unit to the second holding unit in synchronization with the read timing signal;
The second holding unit for holding the read data output by the read timing control unit;
A memory interface circuit comprising: a determination unit that determines whether or not the write data held in the first holding unit matches the read data held in the second holding unit . A memory test apparatus having a memory controller and a memory interface circuit for performing a memory operation test under the control of the memory controller,
The memory controller is
A data generation unit for generating write data and read data is provided,
The memory interface circuit;
A first holding unit for holding the write data generated by the data generation unit;
A delay output unit that outputs the read data generated by the data generation unit to the read timing control unit by delaying a time corresponding to a write delay of the memory;
A read timing signal generating unit that generates a read timing signal indicating that the read data is being output to the memory;
The read timing control unit for outputting the read data delayed output by the delay output unit to the second holding unit in synchronization with the read timing signal;
The second holding unit for holding the read data output by the read timing control unit;
A memory interface circuit comprising: a determination unit that determines whether or not the write data held in the first holding unit matches the read data held in the second holding unit . The memory interface circuit;
The memory test apparatus according to claim 2, further comprising a command analysis unit that analyzes a read command and a write command related to read / write of the memory output from the memory controller. The memory controller is
4. The memory test apparatus according to claim 2, further comprising a timing control unit that sets the time in the delay output unit.

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