JP2006134374A - Semiconductor device and testing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To test operation corresponding to a fast clock only by input of a slow clock. <P>SOLUTION: A semiconductor device of the present invention is a semiconductor device equipped with a clock output portion and a delay circuit, wherein the clock output portion is set to a 1st state according to input of a 1st clock, a 2nd state according to input of a delayed clock from the delay circuit, and to a 3rd state according to input of a 2nd clock, and the delay circuit delays the 1st clock and outputs the delayed clock. In such constitution, precharging and read/write access can be tested at an operating speed corresponding to the fast clock. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for testing a semiconductor device, and more particularly to a semiconductor device that performs a test of two consecutive states and a method for testing the semiconductor device.

  With the recent increase in the speed of processors, not only a large capacity but also a high speed has been required for the memory. As memory becomes more sophisticated, more memory testing has become necessary, and memory testing has become important.

  What is required when testing a memory is that the accuracy of the test is high enough to ensure normal operation and the cost of the test is as low as possible.

  In order to increase the accuracy of the test, it is necessary to perform the test in the same environment as in actual operation as much as possible. Therefore, it is desirable that the operation clock at the time of the test is the same as the actual operation clock. However, there are many cases where a test is performed using a low-speed clock because of redundancy calculation processing.

  In view of this, a method has been proposed in which a high-speed test can be performed even when only a low-speed clock can be applied from the outside in the normal mode by using an internal delay circuit (for example, Patent Document 1).

  Prior art will be described. FIG. 1 is a diagram illustrating a configuration example and a timing example of a semiconductor device in the related art. The device shown in FIG. 1 is connected to an evaluation tester, and includes a clock / address control circuit, a function control circuit, a data control circuit, and a RAM macro capable of high-speed operation.

  The clock address system control circuit inputs two types of external clocks CLKA and CLKB from the evaluation tester, and outputs TCLK generated from CLKA and CLKB to the RAM macro. It should be noted that the two-phase clocks CLKA and CLKB are unnecessary except during the test, and a clock signal corresponding to TCLK may be directly generated and input to the RAM macro. The RAM macro operates based on TCLK output from the clock / address control circuit. The clock / address control circuit also inputs an external address, and accesses the corresponding internal address to the RAM macro.

  The function system control circuit inputs control signals such as read, write, and refresh for the RAM macro from the evaluation tester, and executes control corresponding to the control signal input to the RAM macro. The data system control circuit inputs data to be written from the evaluation tester and writes the data to the RAM macro. In addition, data to be read is input from the RAM macro and output to the evaluation test.

  In the prior art, input of an external address, access to a RAM macro corresponding to an internal address, and output of data of the RAM macro are performed at the timing of ADD, Int_ADD, and TQ shown in FIG. Among them, for access, the bit lines are precharged and balanced at the time tRP shown in FIG. In addition, the word line rises at the time of tRAS, the corresponding cell data is written or read, and the processes up to refresh and restore are performed. That is, in order to shorten tRP, the time from the rise of CLKB to the fall of CLKA may be shortened.

However, with this prior art method, only one of precharge and read / write access can be speeded up, and both cannot be speeded up simultaneously. For this reason, there has been a problem that it is not possible to detect malfunctions that occur only when both are made high-speed. Patent Document 1 describes a method for testing a high-speed RAM using a low-speed tester. However, this prior art also has only one of precharge and read / write access. It is the same as the prior art described in FIG. 1 that the speed cannot be increased and both cannot be increased simultaneously.
JP 2002-230999 A (FIG. 6 to FIG. 10)

  As described above, in the conventional memory test method, a low-speed clock is input, and the memory read / write test at the time of precharge and read / write access is performed at a higher actual operation clock at the time of precharge and read / write. There was a problem that both could not be performed simultaneously during access.

  A semiconductor device according to the present invention is a semiconductor device including a clock output unit and a delay circuit, and the clock output unit is set to a first state in response to an input of a first clock, and is supplied from the delay circuit. The delay state is set to the second state according to the input of the delay clock, and is set to the third state according to the input of the second clock. The delay circuit delays the first clock and delays the delay. A semiconductor device is characterized by outputting a clock. With such a configuration, it is possible to perform precharge and read / write access tests at an operation speed corresponding to a high-speed clock.

  According to the semiconductor device testing method of the present invention, the first state is set according to the input of the first clock, the delayed clock obtained by delaying the first clock is output, and the delayed clock is output according to the output of the delayed clock. A test method for a semiconductor device, which is set to a second state and ends the second state in response to an input of a second clock. By doing so, it is possible to perform the precharge and read / write access tests at an operation speed corresponding to a high-speed clock.

  According to the present invention, a low-speed clock is input, and a memory read / write test at the time of precharge and read / write access is performed at the same time both at the time of precharge and read / write access at a higher actual operation clock. It is possible to perform a highly accurate test without taking time.

Embodiment 1 of the Invention
FIG. 2 is a diagram illustrating a configuration example of the semiconductor device according to the first embodiment of the present invention. At the time of testing, the device shown in FIG. 2 is connected to an evaluation tester, and includes a clock / address control circuit, a function control circuit, a data control circuit, and a RAM macro capable of high-speed operation.

  The clock address system control circuit inputs two types of external clocks CLKA and CLKB from the evaluation tester, and outputs TCLK generated from CLKA and CLKB to the RAM macro. The RAM macro operates based on TCLK output from the clock / address control circuit. The clock / address control circuit also inputs an external address, and accesses the corresponding internal address to the RAM macro.

  Further, the clock / address control circuit also inputs a selector signal and a tRPmin test signal from the evaluation tester, and outputs a TCLK monitor signal and a CLKA delayed antiphase signal to the evaluation tester. Details will be described later.

  The function system control circuit inputs control signals such as read, write, and refresh for the RAM macro from the evaluation tester, and executes control corresponding to the control signal input to the RAM macro. The data system control circuit inputs data to be written from the evaluation tester and writes the data to the RAM macro. Also, data to be read is input from the RAM macro and output to the evaluation tester.

  FIG. 3 is a block diagram showing a detailed configuration of the clock / address control circuit. The clock / address control circuit includes a first clock input terminal 1, an internal address output terminal 2, a clock monitor signal output terminal 3, a delay element 4, an inverter 5, a transfer gate 6, a NAND gate 7, a feedback inverter 8, and a selector signal. An input terminal 10, a second clock input terminal 11, an external address input terminal 12, a tRPmin signal input terminal 13, a clock output terminal 20, and a delayed clock output terminal 30 are provided. The clock / address system control circuit is a circuit newly provided as a test mode dedicated circuit other than an address latch circuit, and a clock signal corresponding to TCLK is directly applied to the RAM macro from outside except during a test. It is enough to enter it.

  The first clock input terminal 1 inputs the first clock signal from the evaluation tester. The clock output terminal 20 outputs a clock TCLK generated inside the device to the RAM macro. The clock monitor signal output terminal 3 outputs the clock monitor signal M_TCLK to the evaluation tester. M_TCLK is the same as TCLK and is output for monitoring by the evaluation tester. The delay element 4 is an element that delays a signal in units of clocks.

  The inverter 5 inverts the input signal and converts it to an opposite phase. The transfer gate 6 outputs the input signal according to whether or not the signal is input from the selector. The NAND gate 7 performs a NAND operation from the input signal and outputs the result. The feedback inverter 8 causes the signal output from the inverter 5 to be input to the inverter 5 again. By doing so, the feedback inverter 8 can be used in combination with the inverter 5 to hold the signal.

  The selector signal input terminal 10 inputs a selector signal from the evaluation tester. The input selector signal is output to the transfer gate 6. A plurality of selector signal input terminals 10 are provided, and the delay time of the signal input from the first clock input unit 1 is determined according to the selected selector signal. The second clock input terminal 11 inputs a second clock signal from the evaluation tester.

  The external address input terminal 12 inputs an external address from the evaluation tester. The tRPmin test signal input terminal 13 is a test signal input terminal that is set to High when testing the tRPmin signal from the evaluation tester. The internal address output terminal 2 outputs an internal address to the RAM macro in synchronization with TCLK generated by the clock / address control circuit. The delayed clock output terminal 30 outputs the clock signal delayed by the delay element 4 to the evaluation tester.

  Next, a test process flow according to Embodiment 1 of the present invention will be described with reference to a timing chart shown in FIG.

  First, the first clock signal is input from the first clock input terminal 1. This clock is CLKA. When the clock signal CLKA is input, the input clock signal is output from the clock output terminal 20. The clock output from the clock output terminal 20 is TCLK. At the same time, TCLK is output to the outside as an M_TCLK signal from the clock monitor signal output terminal 3 and monitored by the evaluation tester. With the rise of CLKA, TCLK also rises.

  Next, the delay element 4 inputs the CLKA clock signal from the first clock input terminal 1 and delays it, and then outputs a delayed clock signal to the inverter 5. The inverter 5 receives the delayed clock signal from the delay element 4, converts it to an opposite phase, and outputs the delayed clock signal to the transfer gate 6.

  The transfer gate 6 receives the delayed clock signal converted into the reverse phase from the inverter 5. At this time, when SEL0 is selected, a selector signal is input to the transfer gate 6 from the selector signal input terminal 10 corresponding to SEL0. When the transfer gate 6 receives the selector signal, the transfer gate 6 outputs the delayed clock signal input from the inverter 5 to the delayed clock output terminal 30. When the transfer gate 6 does not receive the selector signal, the transfer gate 6 does not output the delayed clock signal input from the inverter 5 to the delayed clock output terminal 30.

  When SEL0 is not selected, the delayed clock signal output from the delay element 4 is input to another delay element 4. The delay element 4 further delays the input delayed clock signal and outputs the delayed clock signal to the inverter 5. The delayed clock signal output from the delay element 4 is similarly converted to an opposite phase by the inverter 5 and output to the transfer gate 6. Similarly, when SEL1 is selected and the selector signal is input from the corresponding selector signal input terminal 10, the transfer gate 6 outputs a delayed clock signal to the output terminal 3. On the other hand, when no selector signal is input, the delayed clock signal is not output to the output terminal 3.

  In the same manner, the delay time can be changed by changing the number of clock signals passing through the delay element 4 according to the selected selector. Which selector is selected is determined in advance by a program or the like, and a selector signal may be input from the corresponding selector signal input terminal 10 by controlling the program.

  Since the delayed clock signal output from the transfer gate 6 to the delayed clock output terminal 30 has an opposite phase, the rising edge of DLY_CLKA_B, which is a delayed antiphase clock, is synchronized with the passage of a certain delay time from the rising edge of CLKA. A fall is done. This first state is from the rising edge of CLKA to the falling edge of the delayed antiphase clock.

  This first state is used as a read / write access state. Specifically, the external address is latched in response to the rising edge of CLKA. Then, the internal address is taken in response to the rising edge of TCLK, and the word corresponding to the address is activated. TRAS, which is a read / write access time, is determined according to the delay time at this time. That is, tRAS can be set depending on which selector is selected.

  Since the clock signal of CLKA and the clock signal of the delayed anti-phase clock are also output to the NAND circuit 7 and output to the clock output terminal 20 via the NAND circuit 7, the falling edge of TCLK in response to the falling edge of DLY_CLKA_B Is also done. The second state is after the falling edge of TCLK.

  The second clock input terminal 11 inputs a clock signal of the second clock. This is CLKB. The CLKB clock signal is input so that the CLKB rises after a sufficient time has elapsed from the rise of the CLKA. The input CLKB clock signal is output to the clock output terminal 20 via the NAND circuit 7. By doing so, the rising edge of TCLK is also performed in response to the rising edge of CLKB. The second state is ended by the rise of CLKB. The subsequent state is the third state.

  This second state is used as a precharge state. Specifically, the address latched in response to the fall of TCLK is propagated to the internal address, and the word corresponding to the address is activated in response to the rise of CLKB. The time from the fall of TCLK to the rise at this time is the precharge time tRP.

  In order to perform a precharge test by high-speed operation, the rising edge of CLKB may be accelerated. That is, tRP can be adjusted by the rising edge of CLKB input from the second clock input terminal 11, so that the test can be performed with tRP equivalent to high-speed operation. When obtaining tRP corresponding to high-speed operation, a high level signal is input from the tRPmin test signal input terminal 13.

  Thereafter, TCLK also falls due to the fall of CLKA. Then CLKB falls. Thereafter, CLKA rises and the same state change is repeated.

  In this way, by using two low-speed clock inputs and a delay circuit, it is possible to change the state equivalent to the operation time of the high-speed clock. This method makes it possible to find a memory failure due to high-speed operation at the initial stage of a memory test where only a test using a low-speed clock can be performed. The yield rate can be increased. At this time, the specific circuit configuration is as shown in FIG. 6, and the waveform diagram is as shown in FIG.

Embodiment 2 of the Invention
In the first embodiment of the present invention, the read / write access time is set by the selector, but this can also be set as the precharge time. The circuit configuration is the same as that of the first embodiment of the invention shown in FIG. 3, and the description thereof is omitted here.

  The test process flow in the second embodiment of the present invention will be described with reference to the timing chart shown in FIG.

  First, the first clock signal is input from the first clock input terminal 1. This clock is CLKA. When the clock signal CLKA is input, the input clock signal is output from the clock output terminal 20. The clock output from the clock output terminal 20 is TCLK. At the same time, TCLK is output to the outside as an M_TCLK signal from the clock monitor signal output terminal 3 and monitored by an evaluation tester. TCLK falls by the rise of CLKA.

  Next, the delay element 4 receives the CLKA clock signal from the input terminal 1 and delays it, and then outputs the delayed clock signal to the inverter 5. The inverter 5 receives the delayed clock signal from the delay element 4, converts it to an opposite phase, and outputs the delayed clock signal to the transfer gate 6.

  Thereafter, similarly to the first embodiment of the invention, the selected selector performs delay processing, and the transfer gate 6 outputs a delayed clock signal. DLY_CLKA_B, which is a delayed anti-phase clock, falls in accordance with the passage of a certain delay time from the rise of CLKA. This first state is from the rising edge of CLKA to the falling edge of the delayed antiphase clock.

  This first state is used as a precharge state. That is, it is possible to set tRP which is a precharge time depending on which selector is selected. TCLK rises in response to the fall of DLY_CLKA_B. The state after the rise of TCLK is defined as a second state. That is, tRP is adjustable from the rising edge of CLKA to the falling edge of the delayed antiphase clock, and can be adjusted by the selector.

  The second state is used as a read / write access state. The time in the second state is the time from the rise of TCLK until the rise of CLKB input as the second clock. Therefore, by advancing the rising edge of CLKB, it becomes possible to perform a read / write access test in the same time as that of the high-speed clock operation.

  In this way, by using two low-speed clock inputs and a delay circuit, it is possible to change the state equivalent to the operation time of the high-speed clock. This method makes it possible to find a memory failure due to high-speed operation at the initial stage of a memory test where only a test using a low-speed clock can be performed. The yield rate can be increased. At this time, the waveform diagram is as shown in FIG.

It is a figure which shows the structural example and timing example of a semiconductor device in a prior art. It is a figure which shows the structural example and timing example of a semiconductor device in this invention. FIG. 3 is a circuit diagram showing a circuit configuration of a clock / address control circuit according to the present invention. It is the wave form diagram which simulated the circuit of the semiconductor device in this invention. 3 is a timing chart showing a flow of processing of a semiconductor device in the present invention. FIG. 3 is a circuit diagram showing a circuit configuration of a clock / address control circuit according to the present invention. 3 is a timing chart showing a flow of processing of a semiconductor device in the present invention. It is the wave form diagram which simulated the circuit of the semiconductor device in this invention.

Explanation of symbols

1 First clock input terminal 2 Internal address output terminal 3 Clock monitor signal output terminal 4 Delay element 5 Inverter 6 Transfer gate 7 NAND gate 8 Feedback inverter 10 Selector signal input terminal 11 Second clock input terminal 12 External address input terminal 13 tRPmin Signal input terminal 20 Clock output terminal 30 Delayed clock output terminal

Claims (6)

A semiconductor device including a clock output unit and a delay circuit,
The clock output unit
The first state is set according to the input of the first clock, the second state is set according to the input of the delayed clock from the delay circuit, and the third state is set according to the input of the second clock. Set to
The delay circuit is
A semiconductor device, wherein the first clock is delayed and a delayed clock is output.   The semiconductor device according to claim 1, wherein the delay circuit includes a selector that switches a delay time. The semiconductor device further includes a memory circuit,
2. The first state is a state in which precharging is performed on the memory circuit, and the second state is a state in which reading or writing is performed on the memory circuit. Or the semiconductor device of 2. A method for testing a semiconductor device,
Set to the first state according to the input of the first clock,
Outputting a delayed clock obtained by delaying the first clock;
Set to the second state according to the output of the delay clock,
A test method for a semiconductor device, wherein the semiconductor device is set to the third state in response to an input of a second clock.   5. The method of testing a semiconductor device according to claim 4, wherein the delay time of the delay clock can be switched by a selector. The semiconductor device further includes a memory circuit,
5. The first state is a state in which precharging is performed on the memory circuit, and the second state is a state in which reading or writing is performed on the memory circuit. Or a test method for a semiconductor device according to 5;

Images