KR20080009554A - Input circuit of a semiconductor memory device and test system having the same - Google Patents

Abstract

An input circuit of a semiconductor memory device and a test system having the same are provided to generate data of various patterns in a test mode, and to perform high speed test by using a low speed tester. A data input part buffers and samples first data inputted from the outside in response to a write DQS signal, and generates second data by perform serial/parallel conversion of the first data. A data pattern setting circuit(1700) sets a pattern of the second data and generates third data in response to a test mode signal and a data pattern selection signal. The data pattern setting circuit generates the third data as maintaining logic state of bits of the second data in a normal mode, and generates the third data as maintaining logic state of even data and setting logic state of odd data of the bits of the second data in a test mode.

Description

INPUT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND TEST SYSTEM HAVING THE SAME

1 is a block diagram illustrating an input circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of an input circuit of the semiconductor memory device shown in FIG. 1 in a normal mode.

3 is a timing diagram illustrating one operation of an input circuit of the semiconductor memory device illustrated in FIG. 1 in a test mode.

FIG. 4 is a timing diagram illustrating another operation of an input circuit of the semiconductor memory device shown in FIG. 1 in a test mode.

FIG. 5 is a circuit diagram illustrating an example embodiment of a data pattern setting circuit included in an input circuit of the semiconductor memory device of FIG. 1.

6 is a block diagram illustrating an input circuit of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an example embodiment of a data pattern setting circuit included in an input circuit of the semiconductor memory device of FIG. 6.

FIG. 8 is a timing diagram illustrating an operation of an input circuit of the semiconductor memory device shown in FIG. 6 in a test mode.

FIG. 9 is a timing diagram illustrating another operation of an input circuit of the semiconductor memory device shown in FIG. 6 in a test mode.

10 is a block diagram illustrating an embodiment of a semiconductor memory device including an input circuit of the present invention.

Figure 11 is a block diagram illustrating one embodiment of a test system for testing a semiconductor memory device having an input circuit of the present invention.

* Description of the symbols for the main parts of the drawings *

100, 220: semiconductor memory device

110, 1000, 2000: input circuit

120: memory core

200: test system of semiconductor memory device

210: Automated Test Equipment

1010, 2010: RDQS Pins

1020, 2020: DQ pin

1030, 2030: WDQS pin

1040, 2040: data input unit

1100, 2100: RDQS input buffer

1200, 2200: Data input buffer

1300, 2300: WDQS input buffer

1400, 2400: Sampler

1500, 2500: delay circuit

1600, 2600: loader circuit

1700, 2700: Data pattern setting circuit

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of generating various patterns of data in a test mode.

In general, memory is a general term for a device used for temporarily or permanently storing data or instructions used in a computer, a communication system, an image processing system, and the like, and there are various forms such as a semiconductor, a tape, a disk, and an optical system. Currently, semiconductor memory is the majority.

Such semiconductor memory devices may be classified into dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (Flash memory), and read only memory (ROM) according to data storage methods. Is improving rapidly.

In general, such a semiconductor memory device is released through a series of processes, such as the design, production process, and test of a semiconductor circuit, the essential element that determines the reliability of the product is a test process of the semiconductor memory device.

In the test of the semiconductor memory device, a test pattern is written to memory cells of the semiconductor memory device through a write operation using an external test device, and then the memory cells are read. Read) and compare the read data with the written data to determine whether the semiconductor memory device is good or bad.

(The test equipment inputs an external clock signal to the semiconductor memory device and receives an output signal corresponding to the data written to the memory cell from the semiconductor memory device to determine whether there is a defect.)

In order to transmit more data using an external clock signal of the same speed, a double data rate (DDR) method is currently used, which transmits two data in one clock cycle. In addition, a quad data rate (QDR) method for transmitting four data for one clock cycle and an octal data rate (ODR) method for transmitting eight data for one clock cycle have been studied.

In general, the speed of development of test equipment is slower than that of semiconductor memory devices. Currently, the speed of operation of semiconductor memory devices is rapidly increasing beyond 500 MHz, but the speed of clock and data that test equipment can provide cannot match the speed at which semiconductor memory devices can operate.

For example, when the clock frequency of the semiconductor memory device is 500 MHz, but the clock frequency of the test device is only 250 MHz, the test of the semiconductor memory device may be performed according to the clock frequency of the test equipment. Since test equipment for testing semiconductor memory devices is very expensive, developing test equipment for new semiconductor memory devices is not an easy task.

Accordingly, a method of increasing a frequency of an external clock signal by doubling the frequency multiplier in a semiconductor memory device in a test mode has been conventionally used. For example, the frequency of the clock signal input from an external XOR (exclusive OR) gate or phase synchronous loop (Phase) can be compensated to compensate for the disadvantage that the test equipment measuring the speed of the semiconductor memory is slower than that of the semiconductor memory. It uses a Locked Loop (PLL) circuit to multiply and generate a high frequency internal clock signal.

However, even when the frequency of the clock signal is doubled, the high speed test of the semiconductor memory device is impossible unless the transfer speed of the input data to be written into the memory cell of the semiconductor memory device, that is, the bit rate, is increased.

Accordingly, there is a need for a semiconductor memory device capable of quickly implementing a transfer rate of input data in a test mode.

An object of the present invention is to provide an input circuit of a semiconductor memory device capable of generating various patterns of data in a test mode.

Another object of the present invention is to provide a semiconductor memory device having an input circuit capable of generating data of various patterns in a test mode and performing a high speed test using a low speed tester.

It is still another object of the present invention to provide a test system capable of performing a high speed test using a low speed tester.

Another object of the present invention is to provide a data input method of a semiconductor memory device capable of generating data of various patterns in a test mode and performing a high speed test using a low speed tester.

In order to achieve the above object, an input circuit of a semiconductor memory device according to one embodiment of the present invention includes a data input unit and a data pattern setting circuit.

The data input unit generates second data by buffering, sampling, and serial / parallel conversion of the first data input from the outside in response to the write DQS signal. The data pattern setting circuit sets the pattern of the second data and generates third data in response to a test mode signal and a data pattern selection signal.

According to one embodiment of the invention, the data pattern setting circuit generates the third data while maintaining the logic state of the bits of the second data in the normal mode, the bits of the second data in the test mode The logic state of the even data is maintained, the logic state of the odd data is set in response to the data pattern selection signal, and the third data is generated.

According to an embodiment of the present invention, the data pattern selection signal is input through the RDQS pin.

According to one embodiment of the present invention, the data pattern setting circuit includes a first data pattern setting unit, a second data pattern setting unit, a third data pattern setting unit, and a fourth data pattern setting unit.

The first data pattern setting unit generates a first bit and a second bit of the third data based on the first bit and the second bit of the second data in response to the test mode signal and the data pattern selection signal. The second data pattern setting unit generates third and fourth bits of the third data based on the third and fourth bits of the second data in response to the test mode signal and the data pattern selection signal. The third data pattern setting unit generates the fifth and sixth bits of the third data based on the fifth and sixth bits of the second data in response to the test mode signal and the data pattern selection signal. The fourth data pattern setting unit generates the seventh and eighth bits of the third data based on the seventh and eighth bits of the second data in response to the test mode signal and the data pattern selection signal.

According to an embodiment of the present invention, the data pattern selection signal includes a first data pattern selection signal having a first logic state, a second data pattern selection signal having a second logic state, and a third having a third logic state. And a fourth data pattern selection signal having a fourth logic state.

According to one embodiment of the present invention, the data pattern setting circuit includes a first data pattern setting unit, a second data pattern setting unit, a third data pattern setting unit, and a fourth data pattern setting unit.

The first data pattern setting unit generates a first bit and a second bit of the third data based on the first bit and the second bit of the second data in response to the test mode signal and the first data pattern selection signal. Let's do it. The second data pattern setting unit generates a third bit and a fourth bit of the third data based on the third and fourth bits of the second data in response to the test mode signal and the second data pattern selection signal. Let's do it. The third data pattern setting unit generates the fifth and sixth bits of the third data based on the fifth and sixth bits of the second data in response to the test mode signal and the third data pattern selection signal. Let's do it. The fourth data pattern setting unit generates the seventh and eighth bits of the third data based on the seventh and eighth bits of the second data in response to the test mode signal and the fourth data pattern selection signal. Let's do it.

A semiconductor memory device according to one embodiment of the present invention includes an input circuit and a memory core.

The input circuit samples the first data in response to the write DQS signal and performs serial / parallel conversion to generate second data having a plurality of bits, and sets the pattern of the second data in response to a test mode signal and a data pattern selection signal. And generate third data. The memory core writes the third data into memory cells included therein and reads data stored in the memory cells.

A test system for a semiconductor memory device according to one embodiment of the present invention includes a semiconductor memory device and a tester.

The semiconductor memory device samples the first data in response to the write DQS signal and serially / parallel converts the second data having a plurality of bits, and generates the second data having a plurality of bits, and generates the second data pattern in response to a test mode signal and a data pattern selection signal. The third data is generated and provided to the memory cells included therein. The tester provides the test mode signal, the write DQS signal, the data pattern selection signal, and the first data to the semiconductor memory device and tests the semiconductor memory device.

A data input method of a semiconductor memory device according to an embodiment of the present invention comprises the steps of: receiving first data, a first write DQS signal, and a first data pattern selection signal; Generating a second data pattern selection signal, buffering the first data to generate second data, maintaining a logic state of bits of the second data in a normal mode, and outputting the second data in a test mode Maintaining and outputting a logic state of even data among the bits of data, and setting a logic state of odd data among the bits of the second data in response to the second data pattern selection signal in the test mode. Include.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an input circuit of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, an input circuit 1000 of a semiconductor memory device includes an RDQS input buffer 1100, a data input unit 1040, and a data pattern setting circuit 1700.

The RDQS input buffer 1100 receives and buffers the data pattern selection signal DSP through the RDQS pin 1010. The data input unit 1040 receives the first data DIN through the DQ pin 1020 and the write DQS signal WDQS through the WDQS pin 1030. The data input unit 1040 buffers the first data DIN, samples the first data DIN in response to the write DQS signal WDQS, and serializes / parallel converts the second data BODIN <0: 7>. Generates. The data pattern setting circuit 1700 sets the pattern of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS, and sets the third data FDIN <0. : 7>).

In the normal mode, logic states of even data and odd data among the second data BODIN <0: 7> are not inverted. In the test mode, the logic state of the even data among the second data BODIN <0: 7> is not inverted, and the logic state of the odd data is set in response to the buffered data pattern selection signal BDPS.

The data input unit 1040 includes a data input buffer 1200, a WDQS input buffer 1300, a sampler 1400, a delay circuit 1500, and an ordering circuit 1600.

The data input buffer 1200 buffers the first data DIN to generate fourth data BDIN. The WDQS input buffer 1300 buffers the write DQS signal WDQS to generate the first write DQS signal PDQS. The sampler 1400 performs sampling on the fourth data BDIN in response to the first write DQS signal PDQS and generates even data PDIN_F and odd data PDIN_S. The delay circuit 1500 delays the first write DQS signal PDQS and generates the second write DQS signal DPDQS. The ordering circuit 1600 serially / parallel converts the even data PDIN_F and the odd data PDIN_S in response to the second write DQS signal DPDQS, determines the data order, and determines the second data BODIN <0: 7>. ).

FIG. 2 is a timing diagram illustrating an operation of an input circuit of the semiconductor memory device shown in FIG. 1 in a normal mode.

3 is a timing diagram illustrating one operation of an input circuit of the semiconductor memory device illustrated in FIG. 1 in a test mode.

FIG. 4 is a timing diagram illustrating another operation of an input circuit of the semiconductor memory device shown in FIG. 1 in a test mode.

Hereinafter, an operation of an input circuit of the semiconductor memory device according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 1 to 4.

1 and 2, the write DQS signal WDQS is generated in synchronization with the clock signal CLK. In the example of FIG. 2, the write DQS signal WDQS has a frequency twice the frequency of the clock signal CLK. The fourth data BDIN is data in which the first data DIN input from the outside is buffered by the data input buffer 1200. The first write DQS signal PDQS is a signal in which the write DQS signal WDQS is buffered by the WDQS input buffer 1300. The sampler 1400 samples the fourth data BDIN in response to the first write DQS signal PDQS and generates even data PDIN_F and odd data PDIN_S. As can be seen from the timing diagram of FIG. 2, in the normal mode, data PDIN having 8 bits D0 to D7 is output without distinguishing between even data PDIN_F and odd data PDIN_S. The ordering circuit 1600 performs serial / parallel conversion on the output data PDIN of the sampler 1400 in response to the second write DQS signal DPDQS delayed by the first write DQS signal PDQS, and determines the data order. 2 Generates data (BODIN <0: 7>). In the normal mode, the data pattern setting circuit 1700 generates the third data FDIN <0: 7> without changing the data pattern of the second data BODIN <0: 7>.

1 and 3, the write DQS signal WDQS is generated in synchronization with the clock signal CLK. In the example of FIG. 3, the write DQS signal WDQS and the data pattern selection signal DPS have the same frequency as that of the clock signal CLK. The first data DIN input from the outside has four bits D0, D2, D4, and D6. The fourth data BDIN is data in which the first data DIN input from the outside is buffered by the data input buffer 1200. The first write DQS signal PDQS is a signal in which the write DQS signal WDQS is buffered by the WDQS input buffer 1300. The sampler 1400 performs sampling on the fourth data BDIN in response to the first write DQS signal PDQS and generates even data PDIN_F and odd data PDIN_S. In the timing diagram of FIG. 2, the bits of the even data PDIN_F in the test mode are D0, D2, D4, and D6, and the bits of the odd data PDIN_S are D1, D3, D5, and D7, respectively. Indicated. The ordering circuit 1600 is serial / parallel to the even data PDIN_F and the odd data PDIN_S, which are outputs of the sampler 1400, in response to the second write DQS signal DPDQS to which the first write DQS signal PDQS is delayed. Convert, determine the data order, and generate second data BODIN <0: 7>.

In the test mode, each bit of the even data D0, D2, D4, D6 of the second data BODIN <0: 7> and the odd data D1, D3, D5, D7 is input from the outside. Each bit and logic state of the first data DIN are the same. As can be seen in Figure 3, the buffered data pattern selection signal BDPS is a pulse signal having a logic "high" state and a logic "low" state. For example, the logic "high" state of the buffered data pattern selection signal BDPS means non-inverting, and the logic "low" state of the buffered data pattern selection signal BDPS is inverting (INVERSION). May mean. The data pattern setting circuit 1700 sets the pattern of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS, and sets the third data FDIN <0. : 7>). In the test mode, each bit of the even data D0, D2, D4, and D6 of the third data FDIN <0: 7> is a bit and logic of each of the first data DIN input from the outside. The state is the same. However, each bit of the odd data D1, D3, D5, and D7 of the third data FDIN <0: 7> may have even data D0, D2, D4, in response to the buffered data pattern selection signal BDPS. Each bit of D6) has a logic state inverted or non-inverted. In the example of FIG. 3, bits D1 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> are bits D0 of even data D0, D2, D4, and D6. Has the same logic state as Bits D3 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> invert logic states of bits D2 of even data D0, D2, D4, and D6. Has a logic state. Bits D5 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> are the same as logic states of bits D4 of even data D0, D2, D4, and D6. Has a logic state. Bits D7 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> invert logic states of bits D6 of even data D0, D2, D4, and D6. Has a logic state.

The phase of the data pattern selection signal DPS shown in the timing diagram of FIG. 4 is opposite to the phase of the data pattern selection signal DPS shown in the timing diagram of FIG. 3.

1 and 4, the buffered data pattern selection signal BDPS is a pulse signal having a logic "high" state and a logic "low" state. For example, the logic "high" state of the buffered data pattern selection signal BDPS means non-inverting, and the logic "low" state of the buffered data pattern selection signal BDPS is inverting (INVERSION). May mean. The data pattern setting circuit 1700 sets the pattern of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS, and sets the third data FDIN <0. : 7>). In the test mode, each bit of the even data D0, D2, D4, and D6 of the third data FDIN <0: 7> is a bit and logic of each of the first data DIN input from the outside. The state is the same. However, each bit of the odd data D1, D3, D5, and D7 of the third data FDIN <0: 7> may have even data D0, D2, D4, in response to the buffered data pattern selection signal BDPS. Each bit of D6) has a logic state inverted or non-inverted. In the example of FIG. 4, the bit D1 of the odd data D1, D3, D5, and D7 of the third data FDIN <0: 7> is the bit D0 of the even data D0, D2, D4, and D6. Has a logic state inverting the logic state. Bits D3 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> are the same as logic states of bits D2 of even data D0, D2, D4, and D6. Has a logic state. Bits D5 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> invert logic states of bits D4 of even data D0, D2, D4, and D6. Has a logic state. Bits D7 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> are the same as logic states of bits D6 of even data D0, D2, D4, and D6. Has a logic state.

As described above, the input circuit 1000 of the semiconductor memory device illustrated in FIG. 1 may generate various patterns of input signals according to a logic state of the data pattern selection signal DPS. The data pattern selection signal DPS may be received through the RDQS pin 1010.

FIG. 5 is a circuit diagram illustrating an embodiment of a data pattern setting circuit 1700 included in an input circuit of the semiconductor memory device of FIG. 1.

Referring to FIG. 5, the data pattern setting circuit 1700 may include a first data pattern setting unit 1710, a second data pattern setting unit 1720, a third data pattern setting unit 1730, and a fourth data pattern setting. The unit 1740 is provided.

The first data pattern setting unit 1710 may generate a first bit D0 and a second bit of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS. The first bit FD0 and the second bit FD1 of the third data FDIN <0: 7> are generated based on the bit D1. The second data pattern setting unit 1720 may include the third bits D2 and the fourth of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS. The third bit FD2 and the fourth bit FD3 of the third data FDIN <0: 7> are generated based on the bit D3. The third data pattern setting unit 1730 includes the fifth bit D4 and the fifth bit of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS. The fifth bit FD4 and the sixth bit FD5 of the third data FDIN <0: 7> are generated based on the six bit D5. The fourth data pattern setting unit 1740 may include the seventh bit D6 and the eighth bit of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS. The seventh bit FD6 and the eighth bit FD7 of the third data FDIN <0: 7> are generated based on the bit D7.

The first data pattern setting unit 1710 includes a delay circuit 1711, an inverter 1712, a first multiplexer 1713, and a second multiplexer 1714.

The delay circuit 1711 delays the first bits D0 of the second data BODIN <0: 7> and generates the first bits FD0 of the third data FDIN <0: 7>. The inverter 1712 inverts the phase of the first bit D0 of the second data BODIN <0: 7>. The first multiplexer 1713 selects one of an output signal of the inverter 1712 and a first bit D0 of the second data BODIN <0: 7> in response to the buffered data pattern selection signal BDPS. Output The second multiplexer 1714 selects one of a second bit D1 of the second data BODIN <0: 7> and an output signal of the first multiplexer 1713 in response to the test mode signal HSC_EN. The second bit FD1 of the three data FDIN <0: 7> is generated.

The second data pattern setting unit 1720 includes a delay circuit 1721, an inverter 1722, a first multiplexer 1723, and a second multiplexer 1724.

The delay circuit 1721 delays the third bit D2 of the second data BODIN <0: 7> and generates the third bit FD2 of the third data FDIN <0: 7>. The inverter 1722 inverts the phase of the third bit D2 of the second data BODIN <0: 7>. The first multiplexer 1723 selects one of an output signal of the inverter 1722 and a third bit D2 of the second data BODIN <0: 7> in response to the buffered data pattern selection signal BDPS. Output The second multiplexer 1724 selects one of the fourth bit D3 of the second data BODIN <0: 7> and an output signal of the first multiplexer 1723 in response to the test mode signal HSC_EN. The fourth bit FD3 of the third data FDIN <0: 7> is generated.

The third data pattern setting unit 1730 includes a delay circuit 1731, an inverter 1732, a first multiplexer 1735, and a second multiplexer 1734.

The delay circuit 1731 delays the fifth bit D4 of the second data BODIN <0: 7> and generates the fifth bit FD4 of the third data FDIN <0: 7>. The inverter 1732 inverts the phase of the fifth bit D4 of the second data BODIN <0: 7>. The first multiplexer 1735 selects one of an output signal of the inverter 1732 and a fifth bit D4 of the second data BODIN <0: 7> in response to the buffered data pattern selection signal BDPS. Output The second multiplexer 1734 selects one of the sixth bit D5 of the second data BODIN <0: 7> and the output signal of the first multiplexer 1733 in response to the test mode signal HSC_EN. The sixth bit FD5 of the third data FDIN <0: 7> is generated.

The fourth data pattern setting unit 1740 includes a delay circuit 1741, an inverter 1742, a first multiplexer 1743, and a second multiplexer 1744.

The delay circuit 1741 delays the seventh bit D6 of the second data BODIN <0: 7> and generates the seventh bit FD6 of the third data FDIN <0: 7>. The inverter 1742 inverts the phase of the seventh bit D6 of the second data BODIN <0: 7>. The first multiplexer 1743 selects one of an output signal of the inverter 1742 and a seventh bit D6 of the second data BODIN <0: 7> in response to the buffered data pattern selection signal BDPS. Output The second multiplexer 1744 selects one of an eighth bit D7 of the second data BODIN <0: 7> and an output signal of the first multiplexer 1743 in response to the test mode signal HSC_EN. The eighth bit FD7 of the third data FDIN <0: 7> is generated.

The data pattern setting circuit 1700 illustrated in FIG. 5 generates bits of the third data FDIN <0: 7> in response to one buffered data pattern selection signal BDPS having a waveform in the form of a pulse.

6 is a block diagram illustrating an input circuit of a semiconductor memory device according to a second embodiment of the present invention. In the input circuit 2000 of the semiconductor memory device shown in FIG. 6, the data pattern selection signals DPS <0: 3> are different from the data pattern selection signals DPS used in the circuit of FIG. 1. It is a signal having 4 bits received through.

Referring to FIG. 6, the input circuit 2000 of the semiconductor memory device includes an RDQS input buffer 2100, a data input unit 2040, and a data pattern setting circuit 2700.

The RDQS input buffer 2100 receives and buffers the data pattern selection signals DPS <0: 3> through the RDQS pin 2010. The data input unit 2040 receives the first data DIN through the DQ pin 2020 and a write DQS signal WDQS through the WDQS pin 2030. The data input unit 2040 buffers the first data DIN, samples the first data DIN in response to the write DQS signal WDQS, and serializes / parallel converts the second data BODIN <0: 7>. Generates. The data pattern setting circuit 2700 sets a pattern of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS <0: 3> and sets the third pattern. Generates data FDIN <0: 7>.

In the normal mode, logic states of even data and odd data among the second data BODIN <0: 7> are not inverted. In the test mode, the logic state of the even data among the second data BODIN <0: 7> is not inverted, and the logic state of the odd data is set in response to the buffered data pattern selection signal BDPS <0: 3>. .

The data input unit 2040 includes a data input buffer 2200, a WDQS input buffer 2300, a sampler 2400, a delay circuit 2500, and an ordering circuit 2600.

The data input buffer 2200 buffers the first data DIN to generate fourth data BDIN. The WDQS input buffer 2300 buffers the write DQS signal WDQS to generate the first write DQS signal PDQS. The sampler 2400 samples the fourth data BDIN in response to the first write DQS signal PDQS and generates even data PDIN_F and odd data PDIN_S. The delay circuit 2500 delays the first write DQS signal PDQS and generates a second write DQS signal DPDQS. The ordering circuit 2600 serially / parallel converts the even data PDIN_F and the odd data PDIN_S in response to the second write DQS signal DPDQS, determines the data order, and determines the second data BODIN <0: 7>. ).

FIG. 7 is a circuit diagram illustrating an example embodiment of a data pattern setting circuit included in an input circuit of the semiconductor memory device of FIG. 6.

Referring to FIG. 7, the data pattern setting circuit 2700 may include a first data pattern setting unit 2710, a second data pattern setting unit 2720, a third data pattern setting unit 2730, and a fourth data pattern setting. The unit 2740 is provided. One bit of the buffered data pattern selection signal BDPS <0: 3> is applied to each of the data pattern setting units 2710, 2720, 2730, and 2740 of the data pattern setting circuit 2700 of FIG. 7. The buffered data pattern selection signals BDPS <0: 3> have four bits BDPS0, BDPS1, BDPS2, and BDPS3.

The first data pattern setting unit 2710 may include the first bits D0 of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the first buffered data pattern selection signal BDPS0. The first bit FD0 and the second bit FD1 of the third data FDIN <0: 7> are generated based on the second bit D1. The second data pattern setting unit 2720 may include the third bits D2 of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the second buffered data pattern selection signal BDPS1. The third bit FD2 and the fourth bit FD3 of the third data FDIN <0: 7> are generated based on the fourth bit D3. The third data pattern setting unit 2730 is connected to the fifth bits D4 of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the third buffered data pattern selection signal BDPS2. The fifth bit FD4 and the sixth bit FD5 of the third data FDIN <0: 7> are generated based on the sixth bit D5. The fourth data pattern setting unit 2740 may include the seventh bit D6 of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the fourth buffered data pattern selection signal BDPS3. And the seventh bit FD6 and the eighth bit FD7 of the third data FDIN <0: 7> are generated based on the eighth bit D7.

The first data pattern setting unit 2710 includes a delay circuit 2711, an inverter 2712, a first multiplexer 2713, and a second multiplexer 2714.

The delay circuit 2711 delays the first bits D0 of the second data BODIN <0: 7> and generates the first bits FD0 of the third data FDIN <0: 7>. The inverter 2712 inverts the phase of the first bit D0 of the second data BODIN <0: 7>. The first multiplexer 2713 may select one of an output signal of the inverter 2712 and a first bit D0 of the second data BODIN <0: 7> in response to the first buffered data pattern selection signal BDPS0. Select and print. The second multiplexer 2714 selects one of a second bit D1 of the second data BODIN <0: 7> and an output signal of the first multiplexer 2713 in response to the test mode signal HSC_EN. The second bit FD1 of the three data FDIN <0: 7> is generated.

The second data pattern setting unit 2720 includes a delay circuit 2721, an inverter 2722, a first multiplexer 2723, and a second multiplexer 2724.

The delay circuit 2721 delays the third bit D2 of the second data BODIN <0: 7> and generates the third bit FD2 of the third data FDIN <0: 7>. The inverter 2722 inverts the phase of the third bit D2 of the second data BODIN <0: 7>. The first multiplexer 2723 receives one of an output signal of the inverter 2722 and a third bit D2 of the second data BODIN <0: 7> in response to the second buffered data pattern selection signal BDPS1. Select and print. The second multiplexer 2724 selects one of the fourth bit D3 of the second data BODIN <0: 7> and the output signal of the first multiplexer 2723 in response to the test mode signal HSC_EN. The fourth bit FD3 of the third data FDIN <0: 7> is generated.

The third data pattern setting unit 2730 includes a delay circuit 2731, an inverter 2732, a first multiplexer 2731, and a second multiplexer 2734.

The delay circuit 2731 delays the fifth bit D4 of the second data BODIN <0: 7> and generates the fifth bit FD4 of the third data FDIN <0: 7>. The inverter 2732 inverts the phase of the fifth bit D4 of the second data BODIN <0: 7>. The first multiplexer 2729 may select one of an output signal of the inverter 2732 and a fifth bit D4 of the second data BODIN <0: 7> in response to the third buffered data pattern selection signal BDPS2. Select and print. The second multiplexer 2734 selects one of the sixth bit D5 of the second data BODIN <0: 7> and the output signal of the first multiplexer 2733 in response to the test mode signal HSC_EN. The sixth bit FD5 of the third data FDIN <0: 7> is generated.

The fourth data pattern setting unit 2740 includes a delay circuit 2741, an inverter 2742, a first multiplexer 2743, and a second multiplexer 2744.

The delay circuit 2471 delays the seventh bit D6 of the second data BODIN <0: 7> and generates the seventh bit FD6 of the third data FDIN <0: 7>. The inverter 2742 inverts the phase of the seventh bit D6 of the second data BODIN <0: 7>. The first multiplexer 2743 may select one of an output signal of the inverter 2742 and a seventh bit D6 of the second data BODIN <0: 7> in response to the fourth buffered data pattern selection signal BDPS3. Select and print. The second multiplexer 2744 selects one of an eighth bit D7 of the second data BODIN <0: 7> and an output signal of the first multiplexer 2743 in response to the test mode signal HSC_EN. The eighth bit FD7 of the third data FDIN <0: 7> is generated.

The data pattern setting circuit 1700 illustrated in FIG. 7 is configured to convert the third data FDIN <0: 7> in response to the plurality of buffered data pattern selection signals BDPS <0: 3> having waveforms in the form of levels. The bits are generated.

FIG. 8 is a timing diagram illustrating one operation of an input circuit of the semiconductor memory device shown in FIG. 6 in a test mode.

FIG. 9 is a timing diagram illustrating another operation of an input circuit of the semiconductor memory device shown in FIG. 6 in a test mode.

Hereinafter, an operation of an input circuit of the semiconductor memory device according to the second embodiment of the present invention shown in FIG. 6 will be described with reference to FIGS. 6 to 9.

In the input circuit 2000 of the semiconductor memory device illustrated in FIG. 6, unlike the input circuit 1000 of the semiconductor memory device illustrated in FIG. 1, the data pattern selection signal DPS <0: 3> has 4 bits. The data pattern setting circuit 2700 sets a pattern of the second data BODIN <0: 7> in response to the test mode signal HSC_EN and the buffered data pattern selection signal BDPS <0: 3> and sets the third pattern. Generates data FDIN <0: 7>.

In Fig. 8, each bit of the data pattern selection signal DPS <0: 3> is represented by DPS0, DPS1, DPS2, and DPS3. Each bit of the buffered data pattern selection signal BDPS <0: 3> is represented by BDPS0, BDPS1, BDPS2, and BDPS3. Referring to FIG. 8, the first bits BDPS0 of the buffered data pattern selection signals BDPS <0: 3> have a level of logic “high” state, and the second bit BDPS1 has a logic “low” state. In level, the third bit BDPS2 has a level that is in a logic "high" state, and the fourth bit BDPS3 has a level that is in a logic "low" state. In the test mode, each bit of the even data D0, D2, D4, and D6 of the third data FDIN <0: 7> is a bit and logic of each of the first data DIN input from the outside. The state is the same. However, each bit of the odd data D1, D3, D5, and D7 of the third data FDIN <0: 7> may have even data D0, D2, D4, in response to the buffered data pattern selection signal BDPS. Each bit of D6) has a logic state inverted or non-inverted. In the example of FIG. 8, the bit D1 of the odd data D1, D3, D5, and D7 of the third data FDIN <0: 7> is the bit D0 of the even data D0, D2, D4, and D6. Has the same logic state as Bits D3 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> invert logic states of bits D2 of even data D0, D2, D4, and D6. Has a logic state. Bits D5 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> are the same as logic states of bits D4 of even data D0, D2, D4, and D6. Has a logic state. Bits D7 of odd data D1, D3, D5, and D7 of third data FDIN <0: 7> invert logic states of bits D6 of even data D0, D2, D4, and D6. Has a logic state.

FIG. 9 is a timing diagram showing that third data FDIN <0: 7> having 8 bits of data D0 to D7 is generated from the first data of two bits D0 and D4.

In Fig. 9, each bit of the data pattern selection signal DPS <0: 3> is represented by DPS0, DPS1, DPS2, and DPS3. Each bit of the buffered data pattern selection signal BDPS <0: 3> is represented by BDPS0, BDPS1, BDPS2, and BDPS3. Referring to FIG. 9, the first bits BDPS0 of the buffered data pattern selection signals BDPS <0: 3> have a level of logic “high” state, and the second bit BDPS1 has a logic “low” state. In level, the third bit BDPS2 has a level that is in a logic "high" state, and the fourth bit BDPS3 has a level that is in a logic "low" state. Among the even data D0, D2, D4, and D6 of the output PDIN_F of the sampler 2400, the bits D0 and D2 are generated from the bit D0 of the first data DIN input from an external source. The fields D4 and D6 are generated from the bit D4 of the first data DIN input from the outside. The bits of the odd data D1, D3, D5, and D7 that are the output PDIN_S of the sampler 2400 are the same as the respective bits of the corresponding even data D0, D2, D4, and D6, respectively.

In the test mode, the bits D0 of the third data FDIN <0: 7> have the same logic state as the bits D0 of the first data DIN input from the outside, and the third data Bits D1 of (FDIN <0: 7>) have a logic state D0B in which the logic state of bit D0 of the first data DIN input from the outside is inverted, and the third data FDIN <0. The bit D2 of (7) has the same logic state as the bit D0 of the first data DIN input from the outside, and the bit D3 of the third data FDIN <0: 7> is external. The logic state of the bit D0 of the first data DIN inputted from the reversed state has a logic state D0B. Further, in the test mode, the bits D4 of the third data FDIN <0: 7> have the same logic state as the bits D4 of the first data DIN input from the outside. Bits D5 of the third data FDIN <0: 7> have a logic state D4B in which the logic state of the bit D4 of the first data DIN input from the outside is inverted, and the third data FDIN Bits D6 of <0: 7> have the same logic state as bits D4 of the first data DIN input from the outside, and bits D7 of the third data FDIN <0: 7>. Has a logic state D4B in which the logic state of the bit D4 of the first data DIN input from the outside is inverted.

For example, the bits D0 of the third data FDIN <0: 7> are generated from the bits D0 of the first data DIN in response to the buffered data pattern selection signal BDPS0, and the third Bits D1 of the data FDIN <0: 7> are generated from bits D0 of the first data DIN in response to the buffered data pattern selection signal BDPS1, and the third data FDIN <0: 7> bit D2 is generated from the bit D0 of the first data DIN in response to the buffered data pattern selection signal BDPS2, and the bit D3 of the third data FDIN <0: 7> is generated. D3 is generated from the bit D0 of the first data DIN in response to the buffered data pattern selection signal BDPS3. In addition, the bits D4 of the third data FDIN <0: 7> are generated from the bits D4 of the first data DIN in response to the buffered data pattern selection signal BDPS0, and the third data FDIN <0: 7> is generated from the bits D4 of the first data DIN. Bits D5 of FDIN <0: 7> are generated from bits D4 of the first data DIN in response to the buffered data pattern selection signal BDPS1, and the third data FDIN <0: 7>. Bit (D6) is generated from bit (D4) of first data (DIN) in response to the buffered data pattern selection signal (BDPS2), and bit (D7) of third data (FDIN <0: 7>). Is generated from bit D4 of the first data DIN in response to the buffered data pattern selection signal BDPS3.

In the example of FIG. 9, each bit of the third data FDIN <0: 7> is D0 = D0, D1 = D0B, D2 = D0, D31 = D0B, D4 = D4, D5 = D4B, D6 = D4, D7. It has a value of = D4B.

As described above, the input circuit 2000 of the semiconductor memory device illustrated in FIG. 6 may generate input signals of various patterns according to logic states of the data pattern selection signals DPS <0: 3>. The data pattern selection signals DPS <0: 3> may be received through the RDQS pins 2010.

10 is a block diagram illustrating an embodiment of a semiconductor memory device including an input circuit of the present invention.

Referring to FIG. 10, the semiconductor memory device 100 includes an input circuit 110 and a memory core 120.

The input circuit 110 receives the data pattern selection signal DSP, the first data DIN, the write DQS signal WDQS, and the test mode signal HSC_EN and responds to the write DQS signal WDQS in response to the write DQS signal WDQS. Sampling and serially / parallel converting the data DIN to generate second data having a plurality of bits, and setting a pattern of the second data in response to the test mode signal HSC_EN and the data pattern selection signal DSP. Generates data FDIN <0: 7>. In the normal mode, the logic states of the bits of the second data BODIN <0: 7> are not inverted. In the test mode, the logic state of the even data is not inverted among the bits of the second data BODIN <0: 7>, and the logic state of the odd data is buffered data pattern selection signal BDPS. Is set in response to

The memory core 120 writes the third data FDIN <0: 7> to memory cells provided therein and reads data stored in the memory cells.

Figure 11 is a block diagram illustrating one embodiment of a test system for testing a semiconductor memory device having an input circuit of the present invention.

Referring to FIG. 11, the test system 200 includes an automatic test equipment (ATE) 210 and a semiconductor memory device 220.

The automatic test equipment (ATE) 210 stores the test mode signal HSC_EN, the clock signal CLK, the write DQS signal WDQS, the data pattern selection signal DSP, and the first data DIN. And the semiconductor memory device 220 is tested.

The semiconductor memory device 220 generates the second data having a plurality of bits by sampling and serializing / parallel converting the first data DIN in response to the write DQS signal WDQS, and generating a test mode signal HSC_EN and a data pattern. In response to the selection signal DSP, a pattern of the second data is set and third data FDIN <0: 7> is generated. In the normal mode, the logic states of the bits of the second data BODIN <0: 7> are not inverted. In the test mode, the logic state of even data is not inverted among the bits of the second data BODIN <0: 7>, and the logic state of odd data is a buffered data pattern selection signal BDPS. Is set in response to In addition, the semiconductor memory device 220 writes the third data FDIN <0: 7> into memory cells provided therein and reads data stored in the memory cells.

As described above, the semiconductor memory device having the input circuit according to the present invention can generate various patterns of data in the test mode, and can perform a high speed test using a low speed tester.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

Claims (31)

A data input unit for buffering, sampling, serially / parallel converting first data input from an external device in response to a write DQS signal to generate second data; And And a data pattern setting circuit for setting the pattern of the second data and generating third data in response to a test mode signal and a data pattern selection signal. The data pattern setting circuit of claim 1, wherein the data pattern setting circuit comprises: In the normal mode, the third data is generated while maintaining the logic state of the bits of the second data, and in the test mode, the logic state of the even data (even data) is maintained among the bits of the second data and the odd data ( and setting the logic state of the odd data in response to the data pattern selection signal and generating the third data. The method of claim 1, And the data pattern selection signal is input through an RDQS pin. The method of claim 1, And each of the bits of the odd data of the second data has the same logic state as the bits of the even data of the second data. The method of claim 1, And the second data is 8 bits of data. The method of claim 5, wherein And the first data is 4 bits of data. The data pattern setting circuit of claim 6, wherein the data pattern setting circuit comprises: A first data pattern setting unit generating a first bit and a second bit of the third data based on the first bit and the second bit of the second data in response to the test mode signal and the data pattern selection signal; A second data pattern setting unit configured to generate a third bit and a fourth bit of the third data based on the third and fourth bits of the second data in response to the test mode signal and the data pattern selection signal; A third data pattern setting unit configured to generate fifth and sixth bits of the third data based on the fifth and sixth bits of the second data in response to the test mode signal and the data pattern selection signal; And A fourth data pattern setting unit configured to generate the seventh and eighth bits of the third data based on the seventh and eighth bits of the second data in response to the test mode signal and the data pattern selection signal. An input circuit of a semiconductor memory device, characterized in that. The method of claim 7, wherein the first data pattern setting unit A delay circuit for delaying the first bit of the second data and generating the first bit of the third data; An inverter for inverting the phase of the first bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the first bit of the second data in response to the data pattern selection signal; And And a second multiplexer for selecting one of the second bit of the second data and the output signal of the first multiplexer in response to the test mode signal and generating the second bit of the third data. An input circuit of a semiconductor memory device. The method of claim 7, wherein the second data pattern setting unit A delay circuit for delaying the third bit of the second data and generating the third bit of the third data; An inverter for inverting the phase of the third bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the third bit of the second data in response to the data pattern selection signal; And And a second multiplexer for selecting one of the fourth bit of the second data and an output signal of the first multiplexer in response to the test mode signal and generating the fourth bit of the third data. An input circuit of a semiconductor memory device. The method of claim 7, wherein the third data pattern setting unit A delay circuit for delaying the fifth bit of the second data and generating the fifth bit of the third data; An inverter for inverting the phase of the fifth bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the fifth bit of the second data in response to the data pattern selection signal; And And a second multiplexer for selecting one of the sixth bit of the second data and the output signal of the first multiplexer in response to the test mode signal and generating the sixth bit of the third data. An input circuit of a semiconductor memory device. The method of claim 7, wherein the fourth data pattern setting unit A delay circuit for delaying the seventh bit of the second data and generating the seventh bit of the third data; An inverter for inverting the phase of the seventh bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the seventh bit of the second data in response to the data pattern selection signal; And And a second multiplexer for selecting one of the eighth bit of the second data and the output signal of the first multiplexer in response to the test mode signal and generating the eighth bit of the third data. An input circuit of a semiconductor memory device. The method of claim 5, wherein The data pattern selection signal may include a first data pattern selection signal having a first logic state, a second data pattern selection signal having a second logic state, a third data pattern selection signal having a third logic state, and a fourth logic state. And a fourth data pattern selection signal having a semiconductor memory device. The method of claim 12, And the first to fourth data pattern selection signals each have a logic level until all the bits constituting the second data are output. The method of claim 12, And the first data is 4 bits of data. The data pattern setting circuit of claim 14, wherein the data pattern setting circuit comprises: A first data pattern setting generating a first bit and a second bit of the third data based on the first bit and the second bit of the second data in response to the test mode signal and the first data pattern selection signal part; A second data pattern setting for generating third and fourth bits of the third data based on the third and fourth bits of the second data in response to the test mode signal and the second data pattern selection signal; part; A third data pattern setting for generating fifth and sixth bits of the third data based on fifth and sixth bits of the second data in response to the test mode signal and the third data pattern selection signal; part; And A fourth data pattern setting for generating the seventh and eighth bits of the third data based on the seventh and eighth bits of the second data in response to the test mode signal and the fourth data pattern selection signal; An input circuit of a semiconductor memory device, characterized in that it comprises a portion. The method of claim 15, wherein the first data pattern setting unit A delay circuit for delaying the first bit of the second data and generating the first bit of the third data; An inverter for inverting the phase of the first bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the first bit of the second data in response to the first data pattern selection signal; And And a second multiplexer for selecting one of the second bit of the second data and the output signal of the first multiplexer in response to the test mode signal and generating the second bit of the third data. An input circuit of a semiconductor memory device. The method of claim 15, wherein the second data pattern setting unit A delay circuit for delaying the third bit of the second data and generating the third bit of the third data; An inverter for inverting the phase of the third bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the third bit of the second data in response to the second data pattern selection signal; And And a second multiplexer for selecting one of the fourth bit of the second data and an output signal of the first multiplexer in response to the test mode signal and generating the fourth bit of the third data. An input circuit of a semiconductor memory device. The method of claim 15, wherein the third data pattern setting unit A delay circuit for delaying the fifth bit of the second data and generating the fifth bit of the third data; An inverter for inverting the phase of the fifth bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the fifth bit of the second data in response to the third data pattern selection signal; And And a second multiplexer for selecting one of the sixth bit of the second data and the output signal of the first multiplexer in response to the test mode signal and generating the sixth bit of the third data. An input circuit of a semiconductor memory device. The method of claim 15, wherein the fourth data pattern setting unit A delay circuit for delaying the seventh bit of the second data and generating the seventh bit of the third data; An inverter for inverting the phase of the seventh bit of the second data; A first multiplexer configured to select and output one of an output signal of the inverter and the seventh bit of the second data in response to the fourth data pattern selection signal; And And a second multiplexer for selecting one of the eighth bit of the second data and the output signal of the first multiplexer in response to the test mode signal and generating the eighth bit of the third data. An input circuit of a semiconductor memory device. The method of claim 12, And the first data is two bits of data. The method of claim 1, wherein the data input unit A data input buffer buffering the first data to generate fourth data; A WDQS input buffer for buffering the write DQS signal to generate a first write DQS signal; A sampler configured to sample the fourth data and generate even data and odd data in response to the first write DQS signal; A delay circuit for delaying the first write DQS signal and generating a second write DQS signal; And And an ordering circuit for serially / parallel converting the even data and the odd data and determining a data order in response to the second write DQS signal. The method of claim 1, wherein the input circuit of the semiconductor memory device And an RDQS input buffer for buffering the data pattern selection signal and providing the buffer to the data pattern setting circuit. Sampling the first data in response to the write DQS signal and serial / parallel converting to generate second data having a plurality of bits, and setting a pattern of the second data in response to a test mode signal and a data pattern selection signal. An input circuit for generating data; And And a memory core for writing the third data into memory cells included therein and reading data stored in the memory cells. The method of claim 23, wherein the input circuit A data input unit configured to generate the second data by buffering, sampling, and serial / parallel conversion of the first data in response to the write DQS signal; And And a data pattern setting circuit for setting the second data pattern and generating the third data in response to the test mode signal and the data pattern selection signal. The method of claim 23, wherein the input circuit In the normal mode, the third data is generated while maintaining the logic state of the bits of the second data, and in the test mode, the logic state of the even data (even data) is maintained among the bits of the second data and the odd data ( and setting a logic state of an odd data in response to the data pattern selection signal and generating the third data. The method of claim 23, The data pattern selection signal is input through the RDQS pin. The method of claim 23, wherein the input circuit And an RDQS input buffer for buffering the data pattern selection signal and providing the buffer to the data pattern setting circuit. Sampling the first data in response to the write DQS signal and serial / parallel converting to generate second data having a plurality of bits, and setting a pattern of the second data in response to a test mode signal and a data pattern selection signal. A semiconductor memory device generating data and providing the data to memory cells included therein and outputting data stored in the memory cells; And And a tester configured to provide the test mode signal, the write DQS signal, the data pattern selection signal, and the first data to the semiconductor memory device and test the semiconductor memory device. . 29. The semiconductor memory device of claim 28, wherein the semiconductor memory device is In the normal mode, the third data is generated while maintaining the logic state of the bits of the second data, and in the test mode, the logic state of the even data (even data) is maintained among the bits of the second data and the odd data ( and a logic state of an odd data) is set in response to the data pattern selection signal and generates the third data. The method of claim 28, The data pattern selection signal is input through the RDQS pin. Receiving a first data, a first write DQS signal, and a first data pattern selection signal; Receiving the first data pattern selection signal and generating a second data pattern selection signal; Buffering the first data to generate second data; Maintaining and outputting a logic state of the bits of the second data in a normal mode; Maintaining and outputting a logic state of even data among the bits of the second data in a test mode; And And setting a logic state of odd data among the bits of the second data in response to the second data pattern selection signal in the test mode.

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