KR100920846B1 - Data input circuit in semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A data input circuit of a semiconductor memory device is provided to improve test efficiency by diversifying patterns of data in a DBI test through a patterning signal of a plurality of bits. CONSTITUTION: A data input circuit(1) of a semiconductor memory device includes a DBI(Data Bus Inversion) control unit(10) and a data input unit(20). The DBI control unit latches and aligns a DBI set signal. The DBI control unit responds to a data input strobe signal and a patterning signal of a plurality of bits. The DBI control unit generates a DBI control signal from the aligned DBI set signal. The data input unit latches and aligns an input data. The data input unit responds to a data input strobe signal and a DBI control signal according to an enable state of a test mode signal. The data input unit generates a global data, and delivers the global data to a core circuit(30).

Description

Data input circuit in semiconductor memory device {Data Input Circuit in Semiconductor Memory Apparatus}

The present invention relates to a semiconductor memory device, and more particularly, to a data input circuit of a semiconductor memory device.

In general, a semiconductor memory device includes a plurality of data input buffers and a plurality of data strobe clock buffers. In advanced types of semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), a plurality of data inputted serially through a data input buffer is latched in a plurality of latch circuits under the control of a data strobe clock. It is then aligned in parallel and delivered to the core circuit area via the global data bus.

Meanwhile, in the semiconductor integrated circuits such as the semiconductor memory device and the memory control device according to the related art, some of the data of a predetermined number unit (for example, eight) during the data transmission and reception flows current to the transistor of the data input / output buffer. In order to determine whether or not to generate a large amount of data, a technique called data bus inversion (DBI) is introduced that reduces the current loss by transmitting data having a logic value that generates a current flow. For example, when the NMOS transistor is provided in the data output buffer, if the high level data is less than 5 out of the 8 data, it is inverted and transferred to the data output buffer, and the high level data out of the 8 data is 5 If more than, invert it and pass it to the data output buffer.

After the DBI technology is applied, the semiconductor memory device applying the DBI technology must determine whether the DBI is applied through the DBI enable signal transmitted with the data, and then invert the input data again when the DBI is applied. To this end, the data input path has circuitry for inverting or non-inverting the data after the data are aligned in parallel and before being transferred to the global data bus. In addition, a circuit configuration for controlling the inversion or non-inversion driving of the data after receiving the DBI setting signal transmitted from the memory control device or the test device through the input buffer, latching and aligning the same, and the like is provided.

In order to test DBI technology in such a semiconductor memory device, a method of generating an arbitrary data pattern using a test mode signal and applying the data pattern to a data input path has been conventionally adopted. However, this conventional method has provided a limited data pattern, and has revealed a problem that the occupation area of the data input path increases. Since the semiconductor memory device has as many data input paths as the data input pins, such an increase in the occupied area in the data input paths serves as a factor preventing high integration of the semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and there is a technical problem to provide a data input circuit of a semiconductor memory device which diversifies a test pattern in testing a DBI technology during data input.

In addition, another object of the present invention is to provide a data input circuit of a semiconductor memory device which reduces the occupied area of a data input path to improve area efficiency.

According to an embodiment of the present invention, a data input circuit of a semiconductor memory device may latch and align a DBI setting signal and perform the alignment in response to a data input strobe signal and a multi-bit patterning signal. DBI control means for generating a DBI control signal from the DBI setting signal; And data input means for latching and aligning input data and generating global data in response to the data input strobe signal and the DBI control signal according to whether the test mode signal is enabled, and delivering the global data to a core circuit.

In addition, the data input circuit of the semiconductor memory device according to another embodiment of the present invention, when the test mode signal is disabled, amplifying driving by receiving a plurality of data each received in parallel aligned in response to the data input strobe signal A data driver having a plurality of amplification drivers; A DBI controller for generating a plurality of DBI control signals from a plurality of DBI setting signals that are aligned and transmitted in parallel in response to the data input strobe signal and a plurality of bit patterning signals; And a DBI execution unit for inverting or non-inverting the plurality of data output from the data driver in response to the plurality of DBI control signals and transferring the inverted or non-inverted data to a core circuit.

The data input circuit of the semiconductor memory device of the present invention creates an effect of improving test efficiency by diversifying a pattern of data during a DBI test using a plurality of bit patterning signals.

In addition, the data input circuit of the semiconductor memory device of the present invention creates an effect of improving the area efficiency by reducing the number of elements included in the data input path.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a configuration of a data input circuit of a semiconductor memory device according to an exemplary embodiment of the present invention. For convenience of description, only one data input path is shown.

As shown, the data input circuit 1 comprises a DBI control means 10 and a data input means 20.

The DBI control means 10 latches and aligns the DBI setting signal dbist in response to a DBI enable signal dbien, and sets the DBI enable signal dbien, the data input strobe signal dinst, and n bits. In response to the patterning signal ptn <1: n>, m DBI control signals dbicnt <1: m> are generated from the aligned DBI setting signals. The data input means 20 latches and aligns m bits of input data din <1: m>, and the data input strobe signal dinst and the data according to whether the test mode signal tmd is enabled. In response to the m DBI control signals dbicnt <1: m>, m global data dgio <1: m> are generated and transmitted to the core circuit 30.

The DBI control means 10 includes a first input buffer 110, a DBI signal latch unit 120, a DBI signal alignment unit 130, and a DBI control unit 140.

When the DBI enable signal dbien is enabled, the first input buffer 110 buffers the DBI configuration signal dbist and outputs a DBI buffering signal dbibf. The DBI signal latch unit 120 latches the DBI buffering signal dbibf in response to the rising strobe clock rsdqs and the falling strobe clock fsdqs to generate m DBI latch signals dbilt <1: m>. do. The DBI signal alignment unit 130 generates m DBI alignment signals dbial <1: m> by aligning the m DBI latch signals dbilt <1: m> in parallel. The DBI control unit 140 may receive the m DBI alignment signals dbial in response to the DBI enable signal dbien, the data input strobe signal dinst, and the n-bit patterning signal ptn <1: n>. M DBI control signals dbicnt <1: m> are generated from <1: m>.

The data input unit 20 includes a second input buffer 210, a data latch unit 220, a data alignment unit 230, a data driver 240, and a DBI execution unit 250.

The second input buffer 210 buffers the m bits of input data din <1: m> and outputs m bits of buffering data dbuf <1: m>. The data latch unit 220 latches each bit of the buffering data dbuf <1: m> in response to the rising strobe clock rsdqs and the falling strobe clock fsdqs, thereby m latching data dlat < 1: m>) The data alignment unit 230 generates m alignment data (daln <1: m>) by arranging the m latch data dlat <1: m> in parallel.

Thereafter, the data driver 240 amplifies the m alignment data (daln <1: m>) in response to the data input strobe signal dinst according to whether the test mode signal tmd is enabled. Drive m to generate m drive data ddrv <1: m> or all of the m drive data ddrv <1: m> having a logic value of a first level (for example, High Level). ) That is, when the test mode signal tmd is disabled, the data driver 240 amplifies and drives the m alignment data daln <1: m>, respectively, so that the m driving data ddrv <1: m>), and when the test mode signal tmd is enabled, the m driving data ddrv <1: are independent of the input of the m alignment data daln <1: m>. m>) are all at the first level. In this case, the data driver 240 includes m amplification drivers, and each amplification driver is configured to receive and amplify only one of m alignment data (daln <1: m>).

The DBI execution unit 250 inverts or non-inverts the m driving data ddrv <1: m> in response to the m DBI control signals dbicnt <1: m> to drive the m global data. (dgio <1: m>) to the core circuit 30.

The data input strobe signal dinst is a signal generated by using a write command and a clock inside the semiconductor memory device. The data input strobe signal dinst performs a function of controlling the input timing of data through the data input circuit. The rising strobe clock rsdqs and the falling strobe clock fsdqs are clock signals generated using the write data strobe clock.

In fact, the data input circuit of the semiconductor memory device includes a plurality of data input means 20 per DBI control means 10. However, here, one DBI control means 10 and one data input means 20 are shown for convenience of description.

The n-bit patterning signal ptn <1: n> is a signal input through a pin that is not used during a write operation, and preferably a signal input through n address input pins. As described above, the DBI control unit 140 of the DBI control unit 10 generates a pattern of data during the DBI test operation by using the n-bit patterning signal pat <1: n>. Conventionally, since the data driver 240 of the data input unit 20 generates a data pattern using only the test mode signal tmd, the pattern of data that can be tested is limited. Since the data pattern is generated using the n-bit patterning signals pat <1: n>, more various data patterns can be tested.

In addition, since the DBI controller 140 replaces the function of the data driver 240 which has previously generated a data pattern, the occupied area of the data driver 240 can be significantly reduced. Of course, although the occupation area of the DBI controller 140 is increased, since the data driver 240 is provided in the semiconductor memory device as compared with the DBI controller 140, the overall area efficiency is greatly improved.

FIG. 2 is a detailed configuration diagram of the DBI control unit shown in FIG. 1, assuming that m is 4 and n is 2. FIG. Accordingly, the m DBI alignment signals dbial <1: m> are represented by the first to fourth DBI alignment signals dbial1 to dbial4, and the m DBI control signals dbicnt <1: m> are represented by The first to fourth DBI control signals dbicnt1 to dbicnt4 are represented, and the n-bit patterning signals ptn <1: 2> are represented by first and second patterning signals ptn1 and ptn2.

As shown, the DBI controller 140 includes a DBI control signal generator 141 and first to fourth DBI drivers 143 to 149.

The control signal generator 141 receives the data input strobe signal dinst and the first and second patterning signals ptn1 and ptn2 to receive an operation control signal opcnt and first to fourth driving control signals create drvcnt1 ~ drvcnt4) The first to fourth DBI drivers 143 to 149 respectively include two driving control terminals DCNT1 and DCNT2, and generate the DBI enable signal dbien, the operation control signal opcnt, and the control signal. In response to the signals transmitted from the unit 141 to the respective drive control terminals DCNT1 and DCNT2, the first to fourth DBI alignment signals dbial1 to dbial4 are respectively driven to respectively drive the first to fourth. DBI control signals (dbicnt1 ~ dbicnt4) are generated.

The operation control signal opcnt and the ground power supply VSS are input to the driving control terminals DCNT1 and DCNT2 of the first DBI driver 143. The first driving control signal drvcnt1 and the second driving control signal drvcnt2 are input to the driving control terminals DCNT1 and DCNT2 of the second DBI driver 145. The first driving control signal drvcnt1 and the third driving control signal drvcnt3 are input to the driving control terminals DCNT1 and DCNT2 of the third DBI driver 147. The first driving control signal drvcnt1 and the fourth driving control signal drvcnt4 are input to the driving control terminals DCNT1 and DCNT2 of the fourth DBI driver 149.

As such, the DBI controller 140 combines the data input strobe signal dinst with the first and second patterning signals ptn1 and pnt2 to control the operation control signal opcnt and the first to fourth driving control signals. Create (drvcnt1 ~ drvcnt4). In addition, the driving scheme for the first to fourth DBI alignment signals dbial1 to dbial4 of the first to fourth DBI drivers 143 to 149 may be combined by variously combining the generated signals in a preset manner. By varying, the enable or disable pattern of the first to fourth DBI control signals dbicnt1 to dbicnt4 can be varied. Therefore, the implementation of the present invention makes it possible to improve the test efficiency by diversifying the pattern of input data during DBI testing.

3 is a circuit diagram illustrating a detailed configuration of a control signal generator shown in FIG. 2.

As illustrated, the control signal generator 141 includes a first NOR gate NR1, first to fourth NAND gates ND1 to ND4, and first to seventh inverters IV1 to IV7.

The first NOR gate NR1 receives the first and second patterning signals ptn1 and ptn2. The first NAND gate ND1 receives the data input strobe signal dinst and the output signal of the first NOR gate NR1. The first inverter IV1 receives the output signal of the first NAND gate ND1 and outputs the first driving control signal drvcnt1.

The second inverter IV2 receives the output signal of the first NOR gate NR1. The second NAND gate ND2 receives the data input strobe signal dinst and the output signal of the second inverter IV2. The third inverter IV3 receives the output signal of the second NAND gate ND2 and outputs the second driving control signal drvcnt2.

The third NAND gate ND3 receives the data input strobe signal dinst and the first patterning signal ptn1. The fourth inverter IV4 receives the output signal of the third NAND gate ND3 and outputs the third driving control signal drvcnt3.

The fourth NAND gate ND4 receives the data input strobe signal dinst and the second patterning signal ptn2. The fifth inverter IV5 receives the output signal of the fourth NAND gate ND4 and outputs the fourth driving control signal drvcnt4.

The sixth inverter IV6 receives the data input strobe signal dinst. The seventh inverter IV7 receives the output signal of the sixth inverter IV6 and outputs the operation control signal opcnt.

By the configuration of the control signal generator 141, the operation control signal opcnt is enabled when the data input strobe signal dinst is enabled. The first to fourth driving control signals drvcnt1 to drvcnt4 are enabled or disabled according to the states of the first and second patterning signals ptn1 and ptn2 when the data input strobe signal dinst is enabled. It is implemented in the form of being enabled.

FIG. 4 is a circuit diagram showing a detailed configuration of the first DBI driver shown in FIG. 2. The first to fourth DBI drivers 143 to 149 have the same structure, and thus, the first DBI driver 143 of FIG. The configuration will be described to omit the description of the configuration of the remaining DBI drivers 145 to 149.

As illustrated, the first DBI driver 143 includes a first power supply 1432, a first amplifier 1434, and a first latch driver 1434.

The first power supply 1432 supplies power to the first node N1 in response to the operation control signal opcnt. The first power supply 1432 includes first to third transistors TR1 to TR3.

In the first transistor TR1, the operation control signal opcnt is input to a gate terminal, an external supply power supply VDD is applied to a source terminal, and a drain terminal thereof is connected to the second node N2. In the second transistor TR2, the operation control signal opcnt is input to a gate terminal, the external power supply VDD is applied to a source terminal, and a drain terminal thereof is connected to the first node N1. The third transistor TR3 receives the operation control signal opcnt at a gate terminal and is disposed between the first node N1 and the second node N2.

The first amplifier 1434 amplifies and drives the first DBI alignment signal dbial1 in response to signals input to the first driving control terminal DCNT1 and the second driving control terminal DCNT2. The potential of the node N1 is controlled. The first amplifier 1434 includes the fourth to thirteenth transistors TR4 to TR13 and an eighth inverter IV8.

A gate terminal of the fourth transistor TR4 is connected to the first node N1, an external supply power VDD is applied to a source terminal, and a drain terminal of the fourth transistor TR4 is connected to the second node N2. A gate terminal of the fifth transistor TR5 is connected to the second node N2, an external supply power VDD is applied to a source terminal, and a drain terminal of the fifth transistor TR5 is connected to the first node N1. In the sixth transistor TR6, a gate terminal thereof is connected to the first node N1, a drain terminal thereof is connected to the second node N2, and a source terminal thereof is connected to the third node N3. In the seventh transistor TR7, a gate terminal thereof is connected to the second node N2, a drain terminal thereof is connected to the first node N1, and a source terminal thereof is connected to the fourth node N4.

The eighth inverter IV8 receives the first DBI alignment signal dbial1.

In the eighth transistor TR8, the first DBI alignment signal dbial1 is input to a gate terminal thereof, a drain terminal thereof is connected to the third node N3, and a source terminal thereof is connected to the fifth node N5. In the ninth transistor TR9, an output signal of the eighth inverter IV8 is input to a gate terminal thereof, a drain terminal thereof is connected to the fourth node N4, and a source terminal thereof is connected to the fifth node N5. . In the tenth transistor TR10, a gate terminal thereof is connected to the first driving control terminal DCNT1, a drain terminal thereof is connected to the fifth node N5, and a source terminal thereof is grounded.

The output signal of the eighth inverter IV8 is input to the gate terminal of the eleventh transistor TR11, the drain terminal thereof is connected to the third node N3, and the source terminal thereof is connected to the sixth node N6. In the twelfth transistor TR12, the first DBI alignment signal dbial1 is input to a gate terminal, a drain terminal thereof is connected to the fourth node N4, and a source terminal thereof is connected to the sixth node N6. The thirteenth transistor TR13 has a gate terminal connected to the second driving control terminal DCNT2, a drain terminal connected to the sixth node N6, and a source terminal grounded.

The first latch driver 1434 generates the first DBI control signal dbicnt1 by latching and driving a potential applied to the first node N1 in response to the DBI enable signal dbien. The first latch driver 1434 includes ninth to eleventh inverters IV9 to IV11, fourteenth and fifteenth transistors TR14 and TR15, and a fifth NAND gate ND5.

The ninth inverter IV9 receives a potential applied to the first node N1. In the fourteenth transistor TR14, an output signal of the ninth inverter IV9 is input to a gate terminal, the external supply power VDD is applied to a source terminal, and a drain terminal thereof is connected to a seventh node N7. In the fifteenth transistor TR15, an output signal of the ninth inverter IV9 is input to a gate terminal thereof, a drain terminal thereof is connected to the seventh node N7, and a source terminal thereof is grounded.

The fifth NAND gate ND5 receives the DBI enable signal dbien and the potential of the seventh node N7. The tenth inverter IV10 forms a latch structure with the fifth NAND gate ND5. The eleventh inverter IV11 receives the output signal of the fifth NAND gate ND5 and outputs the first DBI control signal dbicnt1.

Due to this configuration, the first DBI control signal dbicnt1 differentially amplifies the first DBI alignment signal dbial1 when the DBI enable signal dbien and the operation control signal opcnt are enabled. Is generated accordingly. In this case, since the operation control signal opcnt and the ground power supply VSS are applied to the first driving control terminal DCNT1 and the second driving control terminal DCNT2, the first DBI control signal dbicnt1 is applied. ) Is implemented as a form in which the first DBI alignment signal dbial1 is non-inverted.

However, the first to fourth DBI drivers 143 to 149 are configured to receive different signals from the two driving control terminals DCNT1 and DCNT2, respectively. Accordingly, the first to fourth drivers 143 to 149 are enabled or disabled in various forms, respectively, based on logic values of the first and second patterning signals ptn1 and ptn2. 4 DBI control signals (dbicnt1 ~ dbicnt4) can be generated.

FIG. 5 is a detailed configuration diagram of the data driver shown in FIG. 1, wherein each configuration is assuming that m is 4. FIG. Accordingly, the m pieces of alignment data (daln <1: m>) are represented by the first through fourth alignment data (daln1 through daln4), and the m pieces of driving data (ddrv <1: m>) are represented by the first through the first through fourth alignment data (daln <1: m>). Represented by the fourth driving data ddrv1 to ddrv4.

As illustrated, the data driver 240 includes a drive control signal generator 241 and first to fourth amplification drivers 243 to 249.

The driving control signal generator 241 receives the data input strobe signal dinst and generates a driving control signal dcnt. The first to fourth amplification drivers 243 to 249 may be configured to respectively control the first to fourth amplification drivers 243 to 249 from the first to fourth alignment data daln1 to daln4 in response to the driving control signal dcnt and the test mode signal tmd. The first to fourth driving data ddrv1 to ddrv4 are generated.

As described above, the first to fourth amplification drivers 243 to 249 of the data driver 240 of the present invention are configured to receive one piece of alignment data (daln1 to daln4), respectively. It is not configured to implement data patterns. Therefore, since the structure for generating the data pattern is not provided, the structure may be simpler than in the related art, thereby improving the area efficiency of the semiconductor memory device.

FIG. 6 is a circuit diagram illustrating a detailed configuration of a drive control signal generator shown in FIG. 5.

As shown, the drive control signal generator 241 includes twelfth and thirteenth inverters IV12 to IV13.

The twelfth inverter IV12 receives the data input strobe signal dinst. The thirteenth inverter IV13 receives the output signal of the twelfth inverter IV12 and outputs the driving control signal dcnt.

By the configuration of the driving control signal generator 241 as described above, the driving control signal dcnt is implemented as a form in which the data input strobe signal dinst is non-inverted.

FIG. 7 is a circuit diagram illustrating a detailed configuration of the first amplification driver illustrated in FIG. 5. Since the first to fourth amplification drivers 243 to 249 are all configured in the same structure, the first amplification driver 243 of FIG. The configuration will be described to omit the description of the configuration of the remaining amplification drivers 245 to 249.

As illustrated, the first amplification driver 243 includes a second power supply 2432, a second amplifier 2434, and a second latch driver 2436.

The second power supply unit 2432 supplies power to the eighth node N8 in response to the driving control signal dcnt. The second power supply unit 2432 includes sixteenth to eighteenth transistors TR16 to TR18.

In the sixteenth transistor TR16, the driving control signal dcnt is input to a gate terminal, the external supply power supply VDD is applied to a source terminal, and a drain terminal thereof is connected to a ninth node N9. The driving control signal dcnt is input to a gate terminal of the seventeenth transistor TR17, the external supply power VDD is applied to a source terminal thereof, and a drain terminal thereof is connected to the eighth node N8. The driving control signal dcnt is input to a gate terminal of the eighteenth transistor TR18 and disposed between the eighth node N8 and the ninth node N9.

The second amplifier 2434 amplifies and drives the first alignment data daln1 in response to the driving control signal dcnt to control the potential of the eighth node N8. The second amplifier 2434 includes 19th to 25th transistors TR19 to TR25 and a 14th inverter IV14.

The nineteenth transistor TR19 has a gate terminal connected to the eighth node N8, an external supply power supply VDD applied to a source terminal, and a drain terminal connected to the ninth node N9. A gate terminal of the twentieth transistor TR20 is connected to the ninth node N9, an external supply power VDD is applied to a source terminal, and a drain terminal thereof is connected to the eighth node N8. A gate terminal of the twenty-first transistor TR21 is connected to the eighth node N8, and a drain terminal thereof is connected to the ninth node N9. A gate terminal of the twenty-second transistor TR22 is connected to the ninth node N9, and a drain terminal thereof is connected to the eighth node N8.

The fourteenth inverter IV14 receives the first alignment data daln1.

In the twenty-third transistor TR23, the first alignment data daln1 is input to a gate terminal, a drain terminal is connected to a source terminal of the twenty-first transistor TR21, and a source terminal is connected to a tenth node N10. . The twenty-fourth transistor TR24 has an output signal of the fourteenth inverter IV14 at a gate terminal thereof, a drain terminal thereof is connected to a source terminal of the twenty-second transistor TR22, and a source terminal thereof is the tenth node N10. Is connected to. The driving control signal dcnt is input to a gate terminal of the twenty-fifth transistor TR25, a drain terminal thereof is connected to the tenth node N10, and a source terminal thereof is grounded.

The second latch driver 2436 generates the first driving data ddrv1 by using the potential applied to the eighth node N8 or the test mode signal tmd. The second latch driver 2436 includes the fifteenth to seventeenth inverters IV15 to IV17, the 26th and 27th transistors TR26 and TR27, and the second NOR gate NR2.

The fifteenth inverter IV15 receives a potential applied to the eighth node N8. In the 26th transistor TR26, an output signal of the fifteenth inverter IV15 is input to a gate terminal, the external supply power VDD is applied to a source terminal, and a drain terminal thereof is connected to an eleventh node N11. In the twenty-seventh transistor TR27, an output signal of the thirteenth inverter IV13 is input to a gate terminal thereof, a drain terminal thereof is connected to the eleventh node N11, and a source terminal thereof is grounded.

The second NOR gate NR2 receives the test mode signal tmd and the potential of the eleventh node N11. The sixteenth inverter IV16 forms a latch structure with the second NOR gate NR2. The seventeenth inverter IV17 receives the output signal of the second NOR gate NR2 and outputs the first driving data ddrv1.

As described above, when the test mode signal tmd is enabled, the first amplification driver 243 causes the logic level of the first driving data ddrv1 to become a high level. On the other hand, when the test mode signal tmd is disabled, the first alignment data daln1 is amplified and output as the first driving data ddrv1 when the data input strobe signal dinst is enabled. In this case, the first amplification driver 243 does not include a configuration for generating a pattern of data in the test mode. Accordingly, the occupied area of the first amplification driver 243 is reduced compared to the prior art, and the occupied area of the second to fourth amplification drivers 2 to 249 as well as the first amplification driver 243 is also the same. Reduced in principle.

As described above, the data input circuit of the semiconductor memory device of the present invention diversifies the pattern of data using a plurality of bits of the patterning signal during the DBI test. Table 1 below shows a pattern of data generated by two-bit patterning signals ptn1 and ptn2. Through this, it will be easier to understand the data patterns generated by the present invention in various ways.

TABLE 1

dbial1 dbial2 dbial3 dbial4 ptn1 ptn2 dgio1 dgio2 dgio3 dgio4 0 0 0 0 0 0 One One One One One One 0 0 0 0 0 0 One One 0 0 One One 0 0 One One 0 0 One One One One 0 0 0 0 0 0 One One 0 0 One 0 0 One 0 One 0 0 One One One 0 One 0 One 0 One One 0 0 0 One 0 One One 0 0 0 One One 0 One One 0 0 One

As described above, in the data input circuit of the semiconductor memory device of the present invention, the DBI controller 140 uses m number of DBI alignment signals dbial <1: m> using the n-bit patterning signal ptn <1: n>. ) Generates a data pattern of the m global data (dgio <1: m>) by generating m DBI control signals dbicnt <1: m>. Therefore, a variety of data patterns can be generated as compared with the prior art in which data patterns are generated using one bit of the test mode signal.

In addition, as the DBI controller 140 performs an operation for generating a data pattern, the data driver 240 does not need to generate the data pattern as in the related art, so that the circuit configuration of the data driver 240 is improved. It is simple. Since the data driver 240 is provided more in the semiconductor memory device than in the DBI controller 140, the overall area efficiency of the semiconductor memory device is improved.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram showing a configuration of a data input circuit of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a detailed configuration diagram of the DBI control unit shown in FIG. 1;

3 is a circuit diagram showing a detailed configuration of a control signal generation unit shown in FIG. 2;

4 is a circuit diagram showing a detailed configuration of a first DBI driver shown in FIG. 2;

5 is a detailed configuration diagram of the data driver shown in FIG. 1;

6 is a circuit diagram showing a detailed configuration of a drive control signal generation unit shown in FIG. 5;

FIG. 7 is a circuit diagram showing the detailed configuration of the first amplification driver shown in FIG. 5.

<Description of the symbols for the main parts of the drawings>

10: DBI control means 20: data input means

110: first input buffer 120: DBI signal latch unit

130: DBI signal alignment unit 140: DBI control unit

210: second input buffer 220: data latch unit

230: data alignment unit 240: data driver

250: DBI execution unit

Claims (17)

Data bus inversion (DBI) control means for latching and aligning a DBI setting signal and generating a DBI control signal from the aligned DBI setting signal in response to a data input strobe signal and a multi-bit patterning signal; And Data input means for latching and aligning input data and generating global data in response to the data input strobe signal and the DBI control signal according to whether the test mode signal is enabled or not, and transmitting the generated global data to a core circuit; Data input circuit of a semiconductor memory device comprising a. The method of claim 1, And the plurality of bits of the patterning signal are signals input through pins which are not used during a write operation. The method according to claim 1 or 2, The DBI control signal is made of a combination of a plurality of signals, The DBI control means, An input buffer configured to output the DBI buffering signal by buffering the DBI setting signal when a DBI enable signal is enabled; A DBI signal latch unit configured to generate the plurality of DBI latch signals by latching the DBI buffering signal; A DBI signal alignment unit for generating a plurality of DBI alignment signals by aligning the plurality of DBI latch signals in parallel; And A DBI controller generating the plurality of DBI control signals from the plurality of DBI alignment signals in response to the DBI enable signal, the data input strobe signal, and the plurality of bit patterning signals; And a data input circuit of the semiconductor memory device. The method of claim 3, wherein The DBI control unit, A control signal generator configured to receive the data input strobe signal and the plurality of patterning signals and generate an operation control signal and a plurality of driving control signals; And Two driving control terminals, each driving the respective DBI alignment signals in response to the DBI enable signal, the operation control signal, and signals transmitted from the control signal generator to the respective driving control terminals; A plurality of DBI drivers for generating each of the DBI control signals; And a data input circuit of the semiconductor memory device. The method of claim 4, wherein Each of the plurality of DBI drivers, A power supply unit supplying power to a first node in response to the operation control signal; An amplifier configured to amplify and drive a corresponding DBI alignment signal in response to signals input to the two driving control terminals to control the potential of the first node; And A latch driver configured to latch and drive a potential applied to the first node in response to the DBI enable signal to generate a corresponding DBI control signal; And a data input circuit of the semiconductor memory device. The method according to claim 1 or 2, The data input means, when the test mode signal is disabled, amplifies and drives the aligned data to generate a plurality of driving data, and when the test mode signal is enabled, the plurality of driving data having a first logic value. And inverting or non-inverting the plurality of driving data in response to the DBI control signal to output the global data as the global data. The method of claim 6, The data input means, An input buffer for buffering the input data to output buffering data; A data latch unit configured to generate a plurality of latch data by latching each bit of the buffering data; A data alignment unit for generating a plurality of alignment data by aligning the plurality of latch data in parallel; A data driver configured to generate the plurality of driving data in response to the data input strobe signal according to whether the test mode signal is enabled; And A DBI execution unit for inverting or non-inverting the plurality of driving data in response to the DBI control signal and transferring the plurality of driving data to the core circuit as the global data; And a data input circuit of the semiconductor memory device. The method of claim 7, wherein The data driver, A drive control signal generator configured to receive the data input strobe signal and generate a drive control signal; And A plurality of amplification drivers configured to generate each of the drive data from each of the alignment data in response to the drive control signal and the test mode signal; And a data input circuit of the semiconductor memory device. The method of claim 8, Each of the plurality of amplification drivers, A power supply unit supplying power to a first node in response to the driving control signal; An amplifier configured to amplify and drive corresponding alignment data in response to the driving control signal to control the potential of the first node; And A latch driver configured to latch and drive a potential applied to the first node or to generate corresponding driving data using the test mode signal; And a data input circuit of the semiconductor memory device. A data driver including a plurality of amplification drivers configured to amplify and drive each of a plurality of pieces of data which are aligned and transmitted in parallel in response to the data input strobe signal when the test mode signal is disabled; A data bus inversion (DBI) controller configured to generate a plurality of DBI control signals from a plurality of DBI setting signals that are aligned and transmitted in parallel in response to the data input strobe signal and a plurality of bit patterning signals; And A DBI execution unit for inverting or non-inverting driving the plurality of data output from the data driver in response to the plurality of DBI control signals and transferring the plurality of data to the core circuit; Data input circuit of a semiconductor memory device comprising a. The method of claim 10, And the data driver is configured to generate and output a plurality of data having a logic value of a first level when all of the test mode signals are enabled. The method of claim 11, The data driver further includes a driving control signal generator for generating a driving control signal by receiving the data input strobe signal, Each of the plurality of amplification drivers, A power supply unit supplying power to a first node in response to the driving control signal; An amplifier configured to amplify and drive the aligned data in response to the driving control signal to control the potential of the first node; And A latch driver to generate driving data by using the potential applied to the first node or the test mode signal; And a data input circuit of the semiconductor memory device. The method of claim 12, And the plurality of bits of the patterning signal are signals input through pins which are not used during a write operation. The method according to claim 11 or 13, The DBI control unit, A control signal generator configured to receive the data input strobe signal and the plurality of patterning signals and generate an operation control signal and a plurality of driving control signals; And Two driving control terminals, each of the aligned plurality of DBI setting signals in response to a DBI enable signal, the operation control signal, and signals transmitted from the control signal generator to the respective driving control terminals; A plurality of DBI drivers for driving each of the allocated DBI setting signals to generate each of the DBI control signals; And a data input circuit of the semiconductor memory device. The method of claim 14, Each of the plurality of DBI drivers, A power supply unit supplying power to a first node in response to the operation control signal; An amplifier configured to amplify and drive the allocated DBI setting signal in response to the signals input to the two driving control terminals to control the potential of the first node; And A latch driver configured to latch and drive a potential applied to the first node in response to the DBI enable signal to generate a corresponding DBI control signal; And a data input circuit of the semiconductor memory device. The method of claim 14, An input buffer configured to output a DBI buffering signal by buffering a DBI configuration signal when the DBI enable signal is enabled; And A DBI signal latch unit configured to generate the plurality of DBI latch signals by latching the DBI buffering signal; And A DBI signal alignment unit for arranging the plurality of DBI latch signals in parallel and delivering the same to the DBI controller; The data input circuit of the semiconductor memory device further comprising. The method of claim 11, An input buffer that buffers the input data and outputs buffered data; A data latch unit configured to generate a plurality of latch data by latching each bit of the buffering data; And A data alignment unit for aligning the plurality of latch data in parallel and transferring the latch data to the data driver; The data input circuit of the semiconductor memory device further comprising.

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