KR101057193B1 - Data control circuit and semiconductor memory device using same - Google Patents

Abstract

The present invention generates a read block signal for blocking the transmission of the read data during the read operation, and receives the external mask signal and the read-write signal, and generates a light block signal for blocking the transmission of the write data during the write operation. An output driver for buffering read data input through a control circuit, a global lead line, and transferring the read data to a data pad, and blocking transmission of the read data in response to the read blocking signal, and write data input through a global light line. The present invention provides a semiconductor memory device including a write driver that buffers a signal and transmits the data to a local line pair, and blocks transmission of the write data in response to the write blocking signal.

Light, lead, mask, bus width, data

Description

Data control circuit and semiconductor memory device using the same {DATA CONTROL CIRCUIT AND SEMICONBDUCTOR MEMORY DEVICE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a data control circuit and a semiconductor memory device using the same data mask signal that can be selectively used in a read operation or a write operation.

In recent years, semiconductor memory devices have been continuously integrated with high speed and high speed according to the development of technology, and are used in various products ranging from large home appliances to small mobile products. Such a semiconductor memory device is composed of a plurality of memory cells that store data.

Generally, a word address is selected as a low address in an address path of a semiconductor memory device, and a low address is a path for amplifying a sense amplifier by loading data stored in all cells connected to the selected word line in a pair of bit lines. There is a path and a column address path, which is a path for selecting one of a plurality of pairs of bit lines by the column address and reading or writing the selected data.

Again, this column address path is a data access path that selectively enables any one of a plurality of output enable signals to select any one of a plurality of pairs of bit lines carrying data, and reads or writes selected data. Is classified as a data transmission path. The operation of controlling the data access path (hereinafter, referred to as 'data access operation') is performed by a data access control circuit including a column decoder. The data access control circuit decodes the column address to enable a plurality of outputs. Selectively enable one of the signals so that the selected data is read or written.

Meanwhile, the semiconductor memory device provides a data masking function that blocks a data transfer path by a desired period during a read operation or a write operation, thereby preventing the progress of some data. Such data masking is used to read or write only desired data among consecutive input / output data, or to mask the data of a predetermined period before interrupt generation so as not to move to the next operation while data is being read or written. If the data of the predetermined period is not masked, the process proceeds to the next operation while the data is incompletely processed.

On the other hand, the semiconductor memory device is a circuit for generating a read blocking signal for blocking the transmission of the read data by receiving the data mask signal and a circuit for generating a write blocking signal for blocking the transmission of the write data by receiving the data mask signal Each is provided with the same data mask signal input from the outside to control them.

Therefore, the toggling of the data mask signal changes both the level of the read blocking signal and the write blocking signal, thereby failing a read operation fail due to coupling to the global line adjacent to the transmission line of the read blocking signal and the write blocking signal. There is a problem that causes the write operation to fail. That is, when the read blocking signal and the write blocking signal are also toggled by the data mask signal toggling, this indicates a change in the level of data carried on the global line used by the coupling of the lead blocking signal or the light blocking signal with the transmission line. Trigger a lead fail or write fail.

Accordingly, the present invention provides a data control circuit for preventing a level change of data carried on a global line to be used by coupling with a read cutoff signal or a write cutoff signal whose level is changed by toggling the data mask signal. And a semiconductor memory device using the same.

To this end, the present invention provides a read block signal generation unit for generating a read block signal for controlling transmission of read data from a data mask signal in response to a read-write signal, and the data mask in response to the read-write signal. Provided is a data control circuit including a light blocking signal generation unit configured to generate a light blocking signal for controlling transmission of write data from a signal.

The present invention also provides a data control circuit for generating a read blocking signal and a write blocking signal from a data mask signal in response to a read-write signal, and buffers read data input through a global lead line to a data pad. An output driver for controlling the transmission of the read data in response to a read cutoff signal, and buffers the write data input through a global lightline to transmit to the local line pair, and transmits the write data in response to the write cutoff signal. A semiconductor memory device including a write driver for controlling is provided.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are merely for illustrating the present invention, and the scope of protection of the present invention is not limited to these embodiments.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, a semiconductor memory device according to an exemplary embodiment of the present invention includes a data control circuit 1, an output driver 2, a data pad unit 3, and a write driver 4.

The data control circuit 1 includes a buffer unit 10, a read blocking signal generator 12, and a write blocking signal generator 14.

The buffer unit 10 generates the first to fourth internal mask signals IDQM <1: 4> by buffering the first to fourth external mask signals DQM <1: 4>. Here, the first to fourth external mask signals DQM <1: 4> are pulse signals applied as high pulses to block data transmission.

As shown in FIG. 2, the read blocking signal generator 12 may respectively include first to fourth internal mask signals IDQM <1: 4> in response to the read-write signal RW and the SDR mode signal SDRM. ), The first through fourth read blocking signal generators 120 through 123 generating the first through fourth read blocking signals RBL <1: 4>. Here, the read-write signal RW is a level signal that transitions to a high level during a write operation and transitions to a low level during a read operation, and the SDR mode signal SDRM is a signal that is enabled to a high level in the SDR mode.

As described above, the first to fourth read blocking signal generators 120 to 123 buffer the first to fourth internal mask signals IDQM <1: 4> during the read operation in the SDR mode, and thus the first to fourth read blocking signals. The blocking signals RBL <1: 4> are generated, and the first to fourth read blocking signals RBL <1: 4> are fixed at a low level when the signal is not in the SDR mode or during the write operation.

Meanwhile, as illustrated in FIG. 3, the write blocking signal generator 14 includes a bus width signal generator 140 and a transfer controller 145.

As illustrated in FIG. 4, the bus width signal generator 140 may include a delay unit 141, a first bus width signal generator 142, a second bus width signal generator 143, and a third bus width signal. Generation unit 144 is included.

The delay unit 141 includes an inverter chain that delay-buffers the read-write signal RW to generate the read-write delay signal RWD.

The first bus width signal generation unit 142 inverts the first bus width by inverting the first bus width mode signal X32M, the read-write delay signal RWD, and the inversion signal of the test mode signal TM. A NAND gate ND5 for generating the signal X32B, and an inverter IV2 for inverting the first bus width inversion signal X32B to generate the first bus width signal X32. Here, the first bus width mode signal X32M is a signal enabled at a high level to support the X32 mode, and the test mode signal TM transitions from the normal mode to the low level and transitions from the test mode to the high level. Is a signal. The first bus width signal generator 142 may enable the first bus width signal X32 to be enabled at a high level and a low level, respectively, when the first bus width mode signal X32M is at a high level during a normal mode write operation. A first bus width inversion signal X32B is generated.

Next, the second bus width signal generation unit 143 performs a negative logic sum operation on the first and third bus width mode signals X32M and X8M to generate a second bus width mode signal X16M and the NOR gate NR1. The NAND gate generates a second bus width inversion signal X16B by performing a negative logic operation on the read-write delay signal RWD, the second bus width mode signal X16M and the inversion signal of the test mode signal TM. ND6 and an inverter IV4 for inverting the second bus width inversion signal X16B to generate the second bus width signal X16. Here, the second bus width mode signal X16M is a signal enabled at a high level to support the X16 mode, and is a combination of the first bus width mode signal X32M and the third bus width mode signal X8M. Is generated. That is, when both the first bus width mode signal X32M and the third bus width mode signal X8M are low level, they are enabled to a high level. The second bus width signal generator 143 may enable the second bus width signal X16, which is enabled at a high level and a low level, respectively, when the second bus width mode signal X16M is at the high level during the normal operation of the write mode. A second bus width inversion signal X16B is generated.

The third bus width signal generation unit 144 performs a negative logic sum operation on the inverted signal of the third bus width mode signal X8M and the test mode signal TM, and an output signal of the noah gate NR2. And a non-gate NR3 for generating a third bus width signal X8 by performing a negative logic operation on the inverted signal of the read-write delay signal RWD and the third bus by inverting the third bus width signal X8. An inverter IV7 for generating a width inversion signal X8B. Here, the third bus width mode signal X8M is a signal that is enabled at a high level to support the X8 mode. The third bus width signal generator 144 may enable the third bus width signal X8 which is enabled at the high level and the low level, respectively, when the third bus width mode signal X8M is at the high level during the normal operation of the write mode. A third bus width inversion signal X8B is generated.

As such, the bus width signal generator 140 generates first to third bus width signal pairs X32, X32B, X16, X16B, X8, and X8B which are selectively enabled according to the data bus width.

As shown in FIG. 5, the delivery control unit 145 includes first to fourth delivery control units 146 to 149.

The first transfer control unit 146 receives the first internal mask signal IDQM <1> and transfers the inverter IV8 to the node nd1 in response to the first bus width signal pairs X32 and X32B. Inverter IV9 which receives the internal mask signal IDQM <2> and transmits it to the node nd1 in response to the second bus width signal pairs X16 and X16B, and the third internal mask signal IDQM <3>. Inverter IV10 and the node nd1 are inverted and delayed in response to the third bus width signal pair X8 and X8B and transmitted to the node nd1 in response to the third bus width signal pairs X8 and X8B. And a PMOS transistor P1 for pulling up the node nd1 in response to the read-write delay signal RWD. Here, since the node nd1 is pulled up during the read operation, the first write blocking signal WBL <1> is fixed at a low level.

The second transfer control unit 147 receives the second internal mask signal IDQM <2> and transfers the inverter IV11 to the node nd2 in response to the third bus width signal pairs X8 and X8B. Inverter buffers inverter IV12 and node nd2 that receive internal mask signals IDQM <3> and transmit them to node nd2 in response to third bus width signal pairs X8 and X8B. A second inversion delay unit 151 for generating the second write blocking signal WBL <2>, and a PMOS transistor P2 for pull-up driving the node nd2 in response to the read-write delay signal RWD. do. Here, since the node nd2 is pulled up during the read operation, the second write blocking signal WBL <2> is fixed at a low level.

The third transfer control unit 148 inverts the third internal mask signal IDQM <3> and outputs the inverted buffer IV13 to the node nd3 and the third light blocking signal by inverting and buffering the signal of the node nd3. And a third inversion delay unit 152 for generating (WBL <3>) and a PMOS transistor P3 for pull-up driving the node nd3 in response to the read-write delay signal RWD. Here, since the node nd3 is pulled up during the read operation, the third write blocking signal WBL <3> is fixed at a low level.

The fourth transfer control unit 149 receives the fourth internal mask signal IDQM <4> and transfers the inverter IV14 to the node nd4 in response to the first bus width signal pairs X32 and X32B. 3 Inverter buffers the inverter IV15 and node nd4 that receive the internal mask signal IDQM <3> and deliver them to the node nd4 in response to the first bus width signal pairs X32 and X32B. A fourth inversion delay unit 153 for generating a fourth write blocking signal WBL <4> and a PMOS transistor P4 for driving the node nd4 in response to the read-write delay signal RWD. do. Here, since the node nd4 is pulled up during the read operation, the fourth write blocking signal WBL <4> is fixed at a low level.

As such, the transfer control unit 145 may respond to the first to third bus width signal pairs X32, X32B, X16, X16B, X8, and X8B to form the first to fourth internal mask signals IDQM <1: 4>. May be selectively transmitted to the first to fourth write blocking signals WBL <1: 4>.

The write blocking signal generation unit 14 configured as described above may first or third bus width signals selectively enable the first to fourth internal mask signals IDQM <1: 4> according to the data bus width during the write operation. In response to the pairs X32, X32B, X16, X16B, X8, and X8B, they are selectively transmitted to the first to fourth write blocking signals WBL <1: 4>. In addition, during the read operation, the first to fourth write blocking signals WBL <1: 4> are disabled to the low level in response to the low-level read-write signal RW.

Meanwhile, as illustrated in FIG. 6, the output driver 2 may include first to thirty-second read data RD <1:32> input through the first to thirty-second global lead lines GRIO <1:32>. ) Is an inverter IV20 for transmitting the first to the 32nd output data DOUT <1:32> in response to the clock signals CLK and CLKB, and the first to fourth read blocking signals RBL <1: 4. NMOS transistor N1 which controls the transmission of the first to 32nd read data RD <1:32> in response to &quot;). Here, when the first to fourth read blocking signals RBL <1: 4> are enabled at a high level, the first to 32nd output data DOUT <1:32> may be fixed at a low level, and thus, the first to fourth read blocking signals RBL <1: 4> may be fixed at a low level. Transmission of the thirty-third read data RD <1:32> is blocked.

Substantially, the output driver 2 is composed of thirty-two internal circuits as many as the first to thirty-second read data RD <1:32>. More specifically, the first to eighth internal circuits are controlled by the first read blocking signal RBL <1>, and the ninth to 16th internal circuits are controlled by the second read blocking signal RBL <2>. The seventeenth to twenty-fourth internal circuits are controlled by the third read blocking signal RBL <3>, and the twenty-fifth to thirty-second internal circuits are controlled by the fourth lead blocking signal RBL <4>. .

The data pad unit 3 includes 32 data pads which respectively buffer the first to thirty-second output data DOUT <1:32> output from the output driver 2 and output them to the outside.

Meanwhile, as illustrated in FIG. 7, the write driver 4 includes a controller 40 and a data transmitter 42.

As illustrated in FIG. 8, the controller 40 receives the write enable signal BWEN and the first to fourth write blocking signals WBL <1: 4> and performs a negative logic sum operation to drive the first to 32nd drives. The signal DRV <1:32> and the first to 32nd setting signals SET <1:32> are generated, and the write enable signal BWEN and the first to fourth write blocking signals WBL <1: 4>), the NOA gate NR10 generating the first to thirty-second driving signals DRV <1:32>, and the write enable signal BWEN are delayed by a predetermined delay period. And a delay unit 400 for generating a thirty-second set signal SET <1:32>. Here, the write enable signal BWEN is a signal that is enabled at a low level in order to operate the write driver 4. When the write enable signal BWEN is enabled at the high level, the first to 32nd driving signals DRV <1:32> and the first to 32nd setting signals SET <1:32> may be delayed units. The high level is maintained at the same time for a delay period of 400). On the other hand, when the first to fourth light blocking signals WBL <1: 4> are input to the first to 32nd driving signals DRV <1:32>, the first to fourth light blocking signals WBL < 1: 4>) is disabled at a low level during the pulse width period.

Substantially, the controller 40 includes 32 internal circuits as many as the first to 32nd driving signals DRV <1:32> and the first to 32nd setting signals SET <1:32>. More specifically, the first to eighth internal circuits are controlled by the first write blocking signal WBL <1>, and the ninth to 16th internal circuits are controlled by the second write blocking signal WBL <2>. The seventeenth to twenty-fourth internal circuits are controlled by the third write blocking signal WBL <3>, and the twenty-fifth to thirty-second internal circuits are controlled by the fourth write blocking signal WBL <4>. .

As illustrated in FIG. 9, the data transmitter 42 may include a first driver 420, a second driver 422, a first latch 424, a second latch 426, and a third driver 428. ) And a fourth driver 430.

In the first driver 420, all of the first to 32nd driving signals DRV <1:32> and the first to 32nd setting signals SET <1:32> are enabled at a high level. When the thirty-second write data WD <1:32> is at a low level, the node nd5 is pulled down. In addition, the second driver 422 is enabled to both the first to 32nd driving signals DRV <1:32> and the first to 32nd setting signals SET <1:32> to a high level. When the first to thirty-second write data WD <1:32> are high level, the node nd6 is pulled down.

As described above, in the first and second driving units 420 and 422, the first to 32nd driving signals DRV <1:32> and the first to 32nd setting signals SET <1:32> are all included. The node nd5 or node nd6 is selectively pulled down in accordance with the level of the first to 32nd write data WD <1:32> in the high level enabled state.

The first latch unit 424 latches the signal of the node nd5, and the second latch unit 426 latches the signal of the node nd6.

The third driver 428 responds to an output signal of the first latch unit 424 and an output signal of the second latch unit 426 when the first to 32nd setting signals SET <1:32> are at a high level. The node nd7 is pulled up or pulled down. In addition, the fourth driver 430 outputs an output signal of the first latch unit 424 and an output signal of the second latch unit 426 when the first to 32nd setting signals SET <1:32> are high level. In response, the node nd8 is pulled up or pulled down.

When the write enable signal BWEN is enabled at the high level, the data transmitter 42 configured as described above may transmit the first to 32nd write data WD <1:32> during the delay period of the delay unit 400. The buffered data is transmitted to the first to 32nd local line pairs LIO <1:32> and LIOB <1:32>. On the other hand, when the first to fourth light blocking signals WBL <1: 4> are input, the first to 32th driving operations are performed during the high pulse width section of the first to fourth light blocking signals WBL <1: 4>. Since the signals DRV <1:32> are disabled at a low level, the transmission of the first to 32nd write data WD <1:32> is stopped.

On the other hand, the data transmission unit 42 is composed of 32 internal circuits as many as the number of the first to 32nd write data (WD <1:32>) input like the control unit 40.

An operation of the semiconductor memory device according to the exemplary embodiment of the present invention configured as described above will be described as follows.

First, the operation of the semiconductor memory device during the read operation will be described as follows.

The buffer unit 10 generates the first to fourth internal mask signals IDQM <1: 4> by buffering the first to fourth external mask signals DQM <1: 4>.

2 and 6, since the read-write signal RW is at a low level during a read operation, the read blocking signal generator 12 may generate a high level SDR mode signal SDRM and a low level read-write signal. In response to RW, the first through fourth internal mask signals IDQM <1: 4> are buffered to generate the first through fourth read blocking signals RBL <1: 4>, respectively. For example, when the levels of the first to fourth internal mask signals IDQM <1: 4> are low level, low level, high level, and high level, respectively, the first read blocking signal RBL <1> and the first lead blocking signal IDBL. The second read blocking signal RBL <2> is disabled at a low level, and the third read blocking signal RBL <3> and the fourth read blocking signal RBL <4> are enabled at a high level.

Therefore, since the NMOS transistor N1 is turned off in response to the first read blocking signal RBL <1>, the output driver 2 synchronizes the first to eighth read data with the clock signals CLK and CLKB. The NMOS transistor N1 is turned on in response to the RD <1: 8> as the first through eighth output data DOUT <1: 8>, and in response to the second read blocking signal RBL <2>. Since the signal is turned off, the ninth through sixteenth read data RD <9:16> are transferred to the ninth through sixteenth output data DOUT <9:16> in synchronization with the clock signals CLK and CLKB. In addition, since the NMOS transistor N1 is turned on in response to the third read blocking signal RBL <3>, the seventeenth through twenty-fourth output data DOUT <17:24> are fixed at a low level so that transmission may be stopped. Since the NMOS transistor N1 is turned on in response to the fourth read blocking signal RBL <4>, the 25th to 32nd output data DOUT <25:32> are fixed at a low level and then transmitted. Is blocked.

As described above, when the read-write signal RW is at the low level, the read blocking signal generator 12 may respectively correspond to the first to fourth internal mask signals IDQM <1: 4> according to the levels of the first to fourth internal mask signals IDQM <1: 4>. The read blocking signals RBL <1: 4> are generated, and the output driver 2 generates the first to 32nd read data RD according to the level of the first to fourth read blocking signals RBL <1: 4>. <1:32>).

Meanwhile, referring to FIG. 5, referring to the transmission control unit 145 of the light blocking signal generation unit 14, the first transmission control unit 146 may input first to third internal mask signals IDQM <1: 3>. Node nd1 is pulled-up in response to the low-level read-write delay signal RWD regardless of the level of the signal, and generates the first write blocking signal WBL <1> fixed to the low level. 2 The transfer control unit 147 pulls up the node nd2 in response to the low-level read-write delay signal RWD regardless of the level of the second and third internal mask signals IDQM <2: 3>. Since it is driven, it generates the second write blocking signal WBL <2> fixed to the low level. In addition, since the node nd3 of the third transfer control unit 148 and the node nd4 of the fourth transfer control unit 149 are also pulled up, the third write blocking signal WBL <3> and the fourth write blocking signal ( WBL <4>) is also fixed at low level.

As described above, the write blocking signal generator 14 may receive the first to fourth write blocking signals WBL <1: 4> fixed at the low level in response to the low-level read-write signal RW during the read operation. Create

As described above, during the read operation, the read blocking signal generator 12 buffers the first to fourth internal mask signals IDQM <1: 4> in response to the low-level read-write signal RW to output the driver. While generating the first to fourth read blocking signals RBL <1: 4> for controlling the data transmission of (2), the write blocking signal generator 14 generates the low-level read-write signal RW. In response, the first to fourth write blocking signals WBL <1: 4> are all disabled at a low level so that the coupling is performed on the first to 32nd global lead lines GRIO <1:32> by coupling. Prevents level changes in data from occurring.

Next, an operation of the semiconductor memory device during the write operation will be described.

3 to 5, the operation of the write blocking signal generator 14 will be described. The bus width signal generator 140 may include the first bus width mode signal X32M, the second bus width mode signal X8M, and the like. The read-write delay signal RWD is input to generate first to third bus width signal pairs X32, X32B, X16, X16B, X8, and X8B that are selectively enabled according to the data bus width.

For example, when the first bus width mode signal X32M is enabled at a high level, the first bus width signal X32 is enabled at a high level, and the first bus width inversion signal X32B is at a low level. While enabled, the second bus width signal X16 and the third bus width signal X8 are disabled at a low level, and the second bus width inversion signal X16B and the third bus width inversion signal X8B are Disabled to high level. In addition, when the second bus width mode signal X16M is enabled at a high level, the second bus width signal X16 is enabled at a high level, and the second bus width inversion signal X16B is enabled at a low level. On the other hand, the first bus width signal X32 and the third bus width signal X8 are disabled at a low level, and the first bus width inversion signal X32B and the third bus width inversion signal X8B are at a high level. Is disabled.

The transfer controller 145 may respond to the first to third internal bus signals IDQM <1: in response to the first to third bus width signal pairs X32, X32B, X16, X16B, X8 and X8B which are selectively enabled. 4> is selectively transmitted to the first to fourth write blocking signals WBL <1: 4>.

More specifically, in the X32 mode, all of the first to fourth external mask signals DQM <1: 4> are input from the outside, but in the X16 mode, the second and third external mask signals DQM <2: 3>) only, and in the X8 mode, only the third external mask signal DQM <3> is input. Therefore, an external mask signal whose input number varies depending on the data bus width must be selectively transmitted to the first to fourth write blocking signals WBL <1: 4>.

For example, when the first bus width mode signal X32M is at a high level, the first bus width signal pairs X32 and X32B are selectively enabled, so that the first transfer control unit 146 may include the first internal mask signal ( IDQM <1> is transmitted to the first write blocking signal WBL <1>, and the second transfer control unit 147 transmits the second internal mask signal IDQM <2> to the second write blocking signal WBL <2. >), The third transfer control unit 148 transfers the third internal mask signal IDQM <3> as the third write blocking signal WBL <3>, and the fourth transfer control unit 149 transmits the third internal mask signal IDQM <3>. The internal mask signal IDQM <4> is transferred to the fourth write blocking signal WBL <4>. Meanwhile, when the second bus width mode signal X16M is at a high level, the first transfer control unit 146 transfers the second internal mask signal IDQM <2> as the first write blocking signal WBL <1>. The second transfer control unit 147 transfers the second internal mask signal IDQM <2> as the second write blocking signal WBL <2>, and the third transfer control unit 148 transmits the third internal mask signal ( IDQM <3> is transmitted to the third write blocking signal WBL <3>, and the fourth transfer control unit 149 transmits the third internal mask signal IDQM <3> to the fourth write blocking signal WBL <4. >) In addition, when the third bus width mode signal X8M is at a high level, all of the third internal mask signals IDQM <3> are transmitted to the first to fourth write blocking signals WBL <1: 4>.

As such, the write blocking signal generator 14 may respond to the first to third bus width signal pairs X32, X32B, X16, X16B, X8, and X8B according to the preset data bus width. The internal mask signals IDQM <1: 4> are selectively transmitted to the first to fourth write blocking signals WBL <1: 4>.

Meanwhile, referring to FIG. 8, the controller 40 of the write driver 4 receives the write enable signal BWEN and the first to fourth write blocking signals WBL <1: 4> and receives a data transmission unit ( The first to 32nd driving signals DRV <1:32> and the first to 32nd setting signals SET <1:32> for controlling the operation of 42 are generated. More specifically, when the write enable signal BWEN is enabled at a low level, the first to 32nd driving signals DRV <1:32> are enabled at a high level, and the first to 32nd setting signals. (SET <1:32>) is delayed by the delay period of the delay unit 400 and then disabled to the low level. That is, the enable section of the first to 32nd driving signals DRV <1:32> and the enable section of the first to 32nd setting signals SET <1:32> are delay sections of the delay unit 400. Overlap. In this case, the first to 32nd driving signals DRV <1:32> are disabled at a low level when the first to fourth write blocking signals WBL <1: 4> are enabled at a high level.

Referring to FIG. 9, the data transmitter 42 may enable an enable period of the first to 32nd driving signals DRV <1:32> and a first to 32nd set signal SET <1:32>. The first to thirty-second local line pairs LIO <1:32> and LIOB <are buffered by buffering the first to thirtieth write data WD <1:32> during the delay period of the delay unit 400 in which the able interval overlaps. 1:32>). Meanwhile, when the first to 32nd driving signals DRV <1:32> are disabled at a low level according to the level of the first to fourth write blocking signals WBL <1: 4>, the data transmitter 42 ) Stops data transmission.

As described above, the write blocking signal generator 14 buffers the first to fourth internal mask signals IDQM <1: 4> in response to the high-level read-write signal RW during the write operation. The fourth write blocking signal WBL <1: 4> is generated, and the write driver 4 controls data transmission in response to the first to fourth write blocking signals WBL <1: 4>.

Meanwhile, referring to FIG. 2, the read blocking signal generator 12 may apply to the read-write signal RW having a high level regardless of the level of the first to fourth internal mask signals IDQM <1: 4>. In response, the first to fourth read blocking signals RBL <1: 4> are all disabled at a low level. That is, the read blocking signal generator 12 fixes the first to fourth read blocking signals RBL <1: 4> to a low level in response to the high level read-write signal RW during the write operation.

As described above, during the write operation, the write blocking signal generator 14 buffers the first to fourth internal mask signals IDQM <1: 4>, respectively, in response to the high-level read-write signal RW. While generating the first to fourth write blocking signals WBL <1: 4> for controlling the data transmission of (4), the read blocking signal generator 12 is a high-level read-write signal RW. In response to the first to fourth read blocking signals RBL <1: 4> to the low level, the data contained in the first to the 32nd global light lines GWIO <1:32> by coupling. It is possible to prevent the level change from occurring.

In summary, in the semiconductor memory device according to the present embodiment, any one of the read blocking signal and the write blocking signal is fixed to a predetermined level regardless of the toggling of the data mask signal according to the read operation or the write operation. It is possible to prevent the level change of data carried on the global line to be used from occurring.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the read blocking signal generator of FIG. 1.

FIG. 3 is a block diagram illustrating a configuration of a write blocking signal generation unit of FIG. 1.

FIG. 4 is a circuit diagram illustrating the bus width signal generator of FIG. 3.

FIG. 5 is a circuit diagram illustrating the transfer control unit of FIG. 3.

FIG. 6 is a circuit diagram illustrating the output driver of FIG. 1.

7 is a block diagram showing the configuration of the write driver of FIG.

FIG. 8 is a circuit diagram illustrating the controller of FIG. 7.

FIG. 9 is a circuit diagram illustrating the data transmitter of FIG. 7.

<Description of the symbols for the main parts of the drawings>

1: data control circuit 2: output driver

3: data pad section 4: write driver

10: buffer unit 12: lead blocking signal generation unit

14: light blocking signal generator RW: lead-light signal

Claims (17)

A read cutoff signal generator configured to generate a read cutoff signal for controlling transmission of read data by buffering the data mask signal during a read operation in response to the read-write signal; And And a write blocking signal generator configured to generate a write blocking signal for controlling transmission of write data by buffering the data mask signal during a write operation in response to the read-write signal. Claim 2 has been abandoned due to the setting registration fee. The data control circuit of claim 1, wherein the read-write signal becomes a first level during the read operation and a second level during the write operation. Claim 3 was abandoned when the setup registration fee was paid. The data control circuit of claim 2, wherein the read blocking signal generator generates a read blocking signal by buffering the data mask signal when the read-write signal has a first level. Claim 4 was abandoned when the registration fee was paid. The data control circuit of claim 2, wherein the read blocking signal generator generates a read blocking signal that is disabled when the read-write signal has a second level. Claim 5 was abandoned upon payment of a set-up fee. The data control circuit of claim 2, wherein the write blocking signal generator is configured to generate a write blocking signal by buffering the data mask signal when the read-write signal has a second level. Claim 6 was abandoned when the registration fee was paid. The data control circuit of claim 2, wherein the light blocking signal generation unit generates a light blocking signal that is disabled when the read-write signal is at a first level. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the lead blocking signal generator A first read blocking signal generator configured to generate a first read blocking signal by buffering a first data mask signal in response to the read-write signal; And And a second read blocking signal generator configured to generate a second read blocking signal by buffering a second data mask signal in response to the read-write signal. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, wherein the light blocking signal generator A bus width signal generator configured to receive the read-write signal, the first bus width mode signal, and the second bus width mode signal to generate first to third bus width signals selectively enabled according to a predetermined data bus width; ; And And in response to the first to third bus width signals, selectively transmitting the data mask signal as a write blocking signal, wherein the write blocking signal includes a transfer control unit that is disabled during a read operation. A data control circuit configured to generate a read blocking signal by buffering a data mask signal during a read operation in response to a read-write signal, and to generate a write blocking signal by buffering the data mask signal during a write operation; An output driver that buffers read data input through a global lead line and transmits the read data to a data pad, and controls transmission of the read data in response to the read blocking signal; And And a write driver that buffers write data input through a global light line and transmits the write data to a pair of local lines, and controls the transmission of the write data in response to the write blocking signal. Claim 10 was abandoned upon payment of a setup registration fee. The semiconductor memory device of claim 9, wherein the read-write signal becomes a first level during the read operation and becomes a second level during the write operation. Claim 11 was abandoned upon payment of a setup registration fee. Claim 12 was abandoned upon payment of a registration fee. The semiconductor memory device of claim 10, wherein the data control circuit generates a write blocking signal by buffering the data mask signal when the read-write signal is at a second level, and generates a read blocking signal that is disabled. Claim 13 was abandoned upon payment of a registration fee. 10. The method of claim 9, wherein the data control circuit is A read cutoff signal generator configured to generate a read cutoff signal for controlling transfer of read data from the data mask signal in response to the read-write signal; And And a write blocking signal generator configured to generate a write blocking signal for controlling transmission of write data from the data mask signal in response to the read-write signal. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, wherein the lead blocking signal generator A first read blocking signal generator configured to generate a first read blocking signal by buffering a first data mask signal in response to the read-write signal; And And a second read blocking signal generator configured to generate a second read blocking signal by buffering a second data mask signal in response to the read-write signal. Claim 15 was abandoned upon payment of a registration fee. The light blocking signal generating unit of claim 13, wherein the light blocking signal generating unit A bus width signal generator configured to receive the read-write signal, the first bus width mode signal, and the second bus width mode signal to generate first to third bus width signals selectively enabled according to a predetermined data bus width; ; And And a transfer control unit configured to selectively transfer the data mask signal as a write blocking signal in response to the first to third bus width signals, wherein the write blocking signal is disabled during a read operation. Claim 16 was abandoned upon payment of a setup registration fee. The semiconductor memory device of claim 9, wherein the output driver blocks transmission of the read data when the read blocking signal is enabled. Claim 17 has been abandoned due to the setting registration fee. The semiconductor memory device of claim 9, wherein the write driver blocks transmission of the write data when the write blocking signal is enabled.

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