KR20010084291A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided, which can judge a fail of a memory cell during a write operation by controlling a precharge operation when testing the semiconductor device operating at a high frequency with a low frequency apparatus. CONSTITUTION: The device comprises an active precharge signal generator(30), a mode signal generator(32), a PMOS transistor(P) and a latch(34) comprising inverters(I1,I2). A WCBR state is set if an inverted row address strobe signal(RASB) of a low level, an inverted column address strobe signal(CASB), an inverted write enable signal(WEB) and an inverted chip selection signal(CSB) are applied, and if a specific address is applied under the above state, the mode signal generator activates a signal(MRS_RDL) to a high level. The active precharge signal generator generates a pulse signal(PRDL) which is transitted to a high level after being transitted to a low level in response to a signal(TCKE) or a signal(TWE) if the signal(MRS_RDL) is activated to a high level. The PMOS transistor makes a signal(PRB) transit to a high level by being turned on in response to the pulse signal of a low level. The latch inverts and latches the signal(PRB). A row address latch(16) outputs a signal(LRAi) by latching a row address(RAi) in response to a signal(PR) of a high level, and outputs a signal(LRAi) of a low level in response to the signal(PR) of a low level.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of accurately testing a semiconductor device operating at a high frequency using low frequency equipment.

In the process of high integration, memory cells become smaller and the process becomes more difficult. In this regard, defects caused by inputting and outputting data to and from memory cells appear in various forms. In addition, there is a difficulty in using high frequency equipment along with test time in order to screen such defects according to the trend of high integration as well as high speed. It is important to screen cell defects efficiently while eliminating this problem, which reduces the cost of production.

In particular, it is important to effectively screen the defects caused by the write operation among the memory cell defects. In the synchronous dynamic semiconductor memory device, the write operation is performed at various timings. That is, when a row address is input together with the active signal input, the word line corresponding to the external row address is selected by the input address. When a read and write command is applied together with a column address for selecting a bit line, read and write operations are performed.

However, when testing a semiconductor memory device operating at a high frequency by using a low frequency device, a low frequency signal is applied to the semiconductor memory device, thereby preventing accurate testing.

When the write operation is terminated when the semiconductor memory device performs the write operation, the precharge operation is performed. The semiconductor memory device operating at a high frequency in response to the low frequency signal applied from the low frequency equipment performs the precharge operation. The time tRDL from the rising edge of the clock signal of the cycle in which the command is applied until the data is written to the memory cell becomes long.

In other words, the time tRDL of a semiconductor memory device operating at a high frequency is set to be short. When a test is performed by a low frequency device, the time tRDL becomes long, and a memory cell to be determined to fail is determined to be normal. There is this.

In addition, when the test is performed in the wafer state, the operation of the semiconductor device operating at a high frequency is limited because the limit is limited to operating at a high frequency due to input / output capacitance by an input pin of a probe card. There is a difficulty in screening the action.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of accurately determining a defect of a memory cell during a write operation by controlling a precharge operation when testing a semiconductor device operating at a high frequency with low frequency equipment.

The semiconductor memory device of the present invention for achieving the above object is a mode signal generating means for activating the mode signal under the control of the tester during the test, an active signal for generating an active signal in response to the control signals applied from the tester Generating means, deactivating means for deactivating the active signal in response to the mode signal and a precharge control signal applied from the tester, and latching and decoding an address in response to the active signal to form a word line And an address decoder for generating selection signals.

1 is a block diagram showing the structure of a conventional semiconductor memory device.

2 is a block diagram showing a configuration of a semiconductor memory device of the present invention.

3 is a circuit diagram of one embodiment of the active precharge signal generator shown in FIG.

FIG. 4 is an operation timing diagram for explaining the operation when the circuit shown in FIG. 3 is applied to the apparatus shown in FIG.

FIG. 5 is a circuit diagram of another embodiment of the active precharge signal generator shown in FIG.

FIG. 6 is an operation timing diagram for explaining the operation when the circuit shown in FIG. 5 is applied to the apparatus shown in FIG.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the semiconductor memory device of the present invention.

1 is a block diagram showing the structure of a conventional semiconductor memory device, which includes a memory cell array 10, a row decoder 12, an active signal generator 14, a row address latch 16, and a row address predecoder 18. FIG. It consists of).

A bit line precharge operation will be described using the configuration shown in FIG. 1 as follows.

The active signal generator 14 transitions to the "high" level when the "low" level inverted chip select signal CSB and the "low" level inverted row address signal RASB are applied at the rising edge of the clock signal CLK. After the output signal PR is generated and the active command is applied, the inverted column address signal CASB of the "low" level and the inverted write enable signal WEB of the "low" level at the rising edge of the clock signal CLK. Is applied, an output signal PR which transitions to the "low" level after a predetermined time is generated. The row address latch 16 latches the i-bit row address RAi in response to the signal " high " level to output the latched output signal LRAi. The row address predecoder 18 decodes the latched output signal LRAi to generate a decoded output signal DRAij. The row decoder 12 generates word line select signals WL1, ..., WLn in response to the decoding output signal DRAij.

When the output signal PR of the active signal generator 14 transitions to the "low" level, the bit line precharge operation of the memory cell array 10 is performed.

However, when testing a semiconductor memory device operating at a high frequency by using a low frequency test device, a memory device in which a fail occurs during a write operation is determined to be a normal memory cell because a bit line precharge time is delayed.

That is, the write time of the semiconductor memory device operating at a high frequency is set to be short, and it is necessary to determine whether the data is correctly written to the memory cell in a short time. When the precharge time is delayed, the write time becomes longer and according to the specification. There is a problem that it is impossible to determine whether it operates correctly.

FIG. 2 is a block diagram showing the configuration of a semiconductor memory device of the present invention, in which the active precharge signal generator 30, the mode signal generator 32, the PMOS transistor P, and the inverters ( A latch 34 composed of I1 and I2 is added and configured.

The function of each of the added blocks shown in FIG. 2 is as follows.

The mode signal generator 32 is applied with an inverted row address strobe signal RABS, an inverted column address strobe signal CASB, an inverted write enable signal WEB, and an inverted chip select signal CSB having a "low" level. WCBR state is set, and when a specific address is applied in this state, the signal MRS_RDL is activated to the "high" level.

The active precharge signal generator 30 transitions to the "high" level after a predetermined time after the signal MRS_RDL is activated to the "high" level and then transitions to the "low" level in response to the signal TCKE or the signal TWE. To generate a pulse signal PRDL. The signal TCKE is a negative pulse generated after the time tRDL from the rising edge of the clock signal CLK of the cycle in which the write or command is applied to the precharge start time has elapsed when the command is applied by the WCBR timing. It is a signal. When the inverted write enable signal WEB is applied, the signal TWE transitions to a “high” level and then, from the rising edge of the clock signal CLK of the cycle to which the write command is applied, to the precharge start time. Negative pulse signal generated after time tRDL has elapsed. The PMOS transistor P is turned on in response to the pulse signal PRDL of the "low" level to cause the signal PRB to transition to the "high" level. The latch 34 inverts and latches the signal PRB. The row address latch 16 latches the row address RAi in response to the signal "PR" at the "high" level to output the signal LRAi, and "low" in response to the signal PR at the "low" level. Output the level signal LRAi.

That is, when the signal TCKE or the signal TWE is generated while the signal MRS_RDL is activated, a pulse signal PRDL having a "low" level is generated. When the pulse signal PRDL of the "low" level is generated, the signal PRB transitions to the "high" level and the signal PR transitions to the "low" level. Accordingly, the word line select signals WL1, ..., WLn all transition to the "low" level and the precharge operation is performed.

In the semiconductor memory device of the present invention, when a write command is applied during the test, the signal PR transitions to the "low" level after the write time of writing data to the memory cell has elapsed, and the bit line precharge operation is performed.

Therefore, even when testing a semiconductor memory device operating at a high frequency by using a low frequency test device, it is possible to prevent a problem that the fail-in memory cell is determined to be a normal memory cell as the precharge time increases.

FIG. 3 is a circuit diagram of an embodiment of the active precharge signal generator shown in FIG. 2, inverting and delaying circuit 40 composed of inverters I3, I7, NAND gate NA1, and inverters I4, I5, I6. ) And a NOR gate (NOR).

The operation of the circuit shown in Fig. 3 is as follows.

The inverter I3 inverts and outputs the signal TWE of the "high" level. The NAND gate NA1 generates a signal of the "low" level in response to the signal of the "high" level MRS_RDL. The inversion and delay circuit 40 inverts and delays the signal of the "low" level to generate a signal of the "high" level. The NOR gate NOR non-logically combines the output signal of the NAND gate NA1 of the "low" level and the output signal of the inverter I6 to generate a pulse signal of the "high" level. The inverter I7 inverts the pulse signal of the "high" level to generate the pulse signal PRDL of the "low" level.

That is, the active precharge signal generator shown in Fig. 3 makes the pulse signal PRDL transition to the "low" level in response to the transition to the "low" level of the signal TWE and then to the "high" level after a predetermined time. Occurs.

FIG. 4 shows an operation timing diagram for explaining the operation when the circuit shown in FIG. 3 is applied and tested to the semiconductor memory device shown in FIG.

First, the inverting chip select signal CSB of the "low" level, the inverted low address strobe signal RASB, the inverted column address strobe signal CASB, and the inverted write enable signal at the rising edge of the clock signal CLK. When the WEB is applied, the mode signal generator 32 generates a signal MRS_RDL of the "high" level. Thereafter, when the inverting chip select signal CSB having the "low" level and the inverting low address strobe signal RASB are applied at the rising edge of the clock signal CLK, the signal PRB is activated by the active signal generator 14. Generate a signal PRB that transitions to the "low" level. Then, the row address latch 16, the row address predecoder 18, and the row decoder 12 operate to generate word line select signals WL1, ..., WLn. Thereafter, at the rising edge of the clock signal CLK, an inverting chip select signal CSB having a "low" level, an inverting column address strobe signal CASB, and an inverting write enable signal WEB are applied to the inverting write. When the positive pulse signal TWE inverting the enable signal WEB is applied, the active precharge signal generator 30 transitions to the "low" level in response to the transition of the signal TWE to the "low" level. After a predetermined time, a negative pulse signal PRDL is generated, which transitions to the "high" level. When the pulse signal PRDL transitions to the "low" level, the PMOS transistor P is turned on so that the signal PRB transitions to the "high" level.

Therefore, when the write command is applied, the signal PRB transitions to the "high" level as soon as the time tRDL for writing data to the memory cell has elapsed from the rising edge of the clock signal CLK of the cycle in which the write command is applied. As a result, the bit line precharge operation may be performed.

FIG. 5 is a circuit diagram of another embodiment of the active precharge signal generator shown in FIG. 2, which is composed of an inverter I8 and a NAND gate NA2.

The operation of the circuit shown in Fig. 5 is as follows.

The inverter I8 inverts the pulse signal TCKE of the "low" level to generate a pulse signal of the "high" level. The NAND gate NA2 inverts the "high" level pulse signal in response to the "high" level signal MRS_RDL to generate a "low" level pulse signal PRDL.

When the pulse signal PRDL of the "low" level is generated, the PMOS transistor P is turned on to bring the signal PRB to the "high" level.

The signal TCKE applied to the circuit shown in FIG. 5 is a negative pulse signal, and the active precharge signal generator shown in FIG. 5 transitions to the "low" level in response to the transition of the signal TCKE to the "low" level. In response to the transition of the signal TCKE to the "high" level, a pulse signal PRDL is generated which transitions to the "high" level.

Accordingly, the active precharge signal generator shown in Fig. 5 generates a "low" level pulse signal when the time tRDL from the rising edge of the clock signal of the cycle to which the write or read command is applied to the precharge start time has elapsed. Occurs.

FIG. 6 shows an operation timing diagram for explaining the operation when the circuit shown in FIG. 5 is applied and tested to the semiconductor memory device shown in FIG.

Timing of the clock signal CLK, the inverted chip select signal CSB, the inverted row address strobe signal RASB, the inverted column address strobe signal CASB, the inverted write enable signal WEB, and the signal MRS_RDL Is the same as the timing shown in FIG.

The signal TCKE is a negative pulse signal applied after the time tRDL from the rising edge of the cycle in which the write command is applied to the precharge start time has elapsed. The signal PRDL is a negative pulse signal generated in response to the signal TCKE. When the signal PRDL transitions to the "low" level, the signal PRB transitions to the "high" level. Then, the signal PR is transitioned to the "low" level and the row address latch 16, the row address predecoder 18, and the row decoder 12 are disabled, thereby making the word line select signals WL1, ..., WLn) is not activated. Thus, the bit line precharge operation may be performed.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Accordingly, the present invention enables accurate testing of a semiconductor memory device operating at a high frequency by applying a precharge control signal from a test device operating at a low frequency to control the precharge operation.

Claims (3)

Mode signal generating means for activating a mode signal under control of the tester during the test; Active signal generating means for generating an active signal in response to control signals applied from the tester; Deactivating means for deactivating the active signal in response to the mode signal and a precharge control signal applied from the tester during the test; And And an address decoder for latching and decoding an address in response to the active signal to generate word line selection signals. The method of claim 1 wherein the deactive means is Precharge signal generating means for generating a precharge signal in response to the mode signal and a precharge control signal applied from the tester during the test; Deactivating means for deactivating the active signal in response to the precharge signal; And And a latch for inverting and latching the active signal and outputting the latch to the address decoder. The method of claim 2, wherein the precharge signal is And a pulse signal generated after a predetermined time from the rising edge of the clock signal of the cycle in which the write command is applied during the test.