KR100524927B1 - Word Line Control Circuit for Bank Interleave function - Google Patents

Abstract

 A used word line control circuit for the bank interleave function is disclosed. The word line control circuit for the bank interleave function according to the present invention comprises: first signal generating means for receiving a predetermined function selection signal from the outside, delaying the function selection signal for a predetermined time, and outputting it as a bank interleaving operation selection signal; Second signal generating means for receiving the control signal, inverting the write control signal and outputting it as a column address input control signal, and logically combining the bank interleave operation selection signal and the column address input control signal, and using the logical combined result as the row control signal. A plurality of banks in response to a row control means for outputting, a logical combination of the inverted row active signal and a row control signal, and a logic combination means for outputting the logical combined result as a row address enable signal, and a plurality of banks in response to the row address enable signal Sequentially input row addresses for, It has a row decoder that decodes the right addresses to generate decoded row addresses and block selection information, and the bank interleave function can be efficiently used in the merged active mode (MERGED BSENSE) in memory devices having many banks such as Rambus DRAM. By doing so, it is possible to reduce the test time during the burn-in stress test, thereby increasing the productivity.

Description

Word Line Control Circuit for Bank Interleave function

The present invention relates to a semiconductor memory device, and more particularly, to a word line control circuit for a bank interleave function.

In general, in the case of Dynamic Random Access Memory (DRAM), in the case of an Enhanced Data Out (EDO) DRAM and a Synchronous DRAM (SDRAM), a row address for controlling a row address in the word line direction is used. There is a Low Address Strobe (RAS) input terminal that represents a signal. In addition, the RAMBUS DRAM (hereinafter, RDRAM) has two signal input terminals that function as RAS unlike other DRAMs. One of them is a low active signal input terminal BSENSE which receives a signal functioning as a ROW ACTIVE, and the other is a precharge signal input terminal PRECH which receives a precharge signal. That is, since the Rambus DRAM is composed of many banks, RAS is divided into two terminals to efficiently control the operation of the bank.

However, when performing stress tests such as Burn-In tests on Rambus DRAMs, testers with fewer tester drive pins have a "Merged BSENSE Mode" feature that merges the functions of the two terminals into one. It is often used. In other words, the merged low active mode is a test method that is effectively used in testers with fewer drive pins.

1 is a waveform diagram illustrating a conventional operation in a merged low active mode. Referring to FIG. 1, a row address X_ADD of a bank selected to enable a word line in response to a first time point T1 in which the low active signal BSENSE is enabled from the high level to the low level is an address input terminal. Is applied through. On the other hand, when the low active signal BSENSE is enabled at a low level, the low address enable signal PDRAEB is at a low level. In this state, when the write enable signal WE is activated to the high level and the column active signal COLLAT is enabled, the column address Y_ADD is input through the column address input terminal. Here, the column active signal COLLAT is a signal that can be compared with a CAS (COLUMN ADDRESS STROBE) of another DRAM and may be referred to as a signal for activating a column direction. Therefore, when the column address Y_ADD is input, data writing is performed in the selected bank. In addition, when data writing is completed, the low active signal BSENSE is disabled to a high level. At this time, if the time when BSENSE is disabled is T2, the precharge bank address BANK is input at T2 to disable the word line to precharge the selected bank. In addition, the row address enable signal PDRAEB becomes high again in response to the time T2, that is, the rising edge of BSENSE.

FIG. 2 is a circuit diagram illustrating generation of a conventional row address enable signal PDRAEB and includes inverters 20 and 22. Referring to FIG. 2, the low active signal BSENSE applied to the inverters 20 and 22 is delayed for a predetermined time and output as the row address enable signal PDRAEB.

That is, in the related art, when the low active signal BSENSE becomes low level, the low address enable signal PDRAEB also becomes low level. When the low active signal BSENSE becomes high level, the low address enable signal PDRAEB also becomes high. It is set to be a level. For this reason, when the row address enable signal PDRAEB is at the low level, the row decoder (not shown) may not operate normally, and may not decode the input row address or generate block selection information.

In order to reduce the test time, the Rambus DRAM frequently uses the BANK INTERLEAVE function provided in the DA (DIRECT ACCESS) mode. The bank interleave function refers to a method of sequentially activating a plurality of banks, writing data, and controlling the written banks simultaneously to precharge sequentially. In other words, by using the bank interleave function, test time can be shortened because many banks can be enabled at the time of a stress test such as a burn-in test.

3 is a waveform diagram illustrating a bank interleave function of a conventional Rambus DRAM. Referring to FIG. 3, the row addresses X_ADD of the plurality of banks BAN0 to BANK6 are applied based on the time when the low active signal BSENSE transitions from the high level to the low level. At this time, when the column active signal COLLAT is enabled and the column address Y_ADD is applied, the low active signal BSENSE maintains a high level. Further, when the column address is enabled and data writing is performed, the precharge addresses BANK0 to BANK6 of the plurality of banks are sequentially applied by the precharge signal PRECH applied through the precharge signal input terminal. do.

As described above, the bank interleave function can select many banks at one time, thus making it possible to select more word lines. Therefore, there is an advantage that the stress test time can be reduced during burn-in stress. On the other hand, in the merged low active function of FIG. 1, since the precharge is completed after selecting one bank to write data, it is possible to select another bank, which requires more test time.

As such, when performing a stress test using a tester limited by the number of drive pins, when a bank interleave function is to be used together, a terminal for inputting a low active signal BSENSE and a precharge signal PRECH may be input. There are many difficulties because the terminals are not divided. For example, in a bank interleave operation, whenever a BSENSE goes from a high level to a low level, a row address for one bank may be input and latched, and the process may be repeated to receive row addresses for different banks. . However, as in the merged low active function, while the BSENSE remains at the low level, the low address enable signal PDRAEB is also at the low level. Therefore, there is a problem in that the bank interleave function cannot be efficiently performed because the row decoder cannot operate and cannot receive the row address.

SUMMARY OF THE INVENTION The present invention provides a word for a bank interleave function that can efficiently perform a bank interleave function even in a merged low active mode by allowing a row address to be accepted even when a low active signal remains constant. It is to provide a line control circuit.

In order to achieve the above object, the word line control circuit for the bank interleave function according to the present invention receives a predetermined function selection signal from the outside, delays the function selection signal by a predetermined time and outputs it as a bank interleave operation selection signal. Generating means, a second signal generating means for receiving the write control signal from the outside, inverting the write control signal and outputting it as a column address input control signal, and logically combining the bank interleave operation selection signal and the column address input control signal, A row control means for outputting a result as a row control signal, a logic combination means for logically combining the inverted row active signal and a row control signal, and outputting the logical combined result as a row address enable signal, and a row address enable signal Row address for multiple banks in response Input by one, and is preferably composed of a row decoder to generate the decoded row address and the block selecting information for decoding the row address.

Hereinafter, a word line control circuit for a bank interleave function according to the present invention will be described with reference to the accompanying drawings.

Figure 4 is a circuit diagram of a preferred embodiment for explaining a word line control circuit for the bank interleave function according to the present invention, the inverter 440, the first signal generator 400, the second signal generator 420, row The controller 450, the NAND gate 460, and the row decoder 470 are included. The first signal generator 400 of FIG. 4 includes a first pad 402 and inverters 404 and 406, and the second signal generator 420 includes a second pad 422 and an inverter 424. It includes. In addition, the row controller 450 includes an inverter 452 and a NAND gate 454.

The first signal generator 400 of FIG. 4 receives a function selection signal applied from an external tester, delays the function selection signal by a predetermined time through the inverters 405 and 406 connected in series, and selects the bank interleaving operation selection signal S1. ) Here, the bank interleave operation selection signal S1 represents a signal for selecting to use the bank interleave function in the merged low active mode. That is, S1 is a signal indicating to accept a row address for bank interleave operation.

In addition, the bank interleave operation selection signal S1 may be generated by the mode register setting (hereinafter, referred to as MRS) in the memory without being received from the external tester through the first pad 402. As such, when the bank interleave operation is used in the merged low active function, the operation selection signal S1 may be set to a high level.

The second signal generator 420 receives the write control signal from an external tester, inverts the write control signal in the inverter 424, and outputs it as the column address input control signal S2. Here, the column address may be implemented by latching the row address input when the column address input control signal S2 is at a high level to input the column address. At this time, the column address input control signal S2 can also be generated by itself using the MRS. In particular, S2 preferably uses the write enable signal WE.

The row controller 450 receives the bank interleave operation selection signal S1 generated by the first signal generator 400 and the column address input control signal S2 generated by the second signal generator 420. The row control signal ROW_C is generated by logically combining the signals S1 and S2. Specifically, the column address input control signal S2 is inverted in the inverter 452 and applied to the second input of the NAND gate 454. The NAND gate 454 inverts AND the output of the bank interleave operation selection signal S1 and the inverter 452, and outputs the inverted AND product as the row control signal ROW_C.

The NAND gate 460 is a low active signal (inverted by the inverter 440). ) And the row control signal ROW_C generated by the row controller 450 are inversely ANDed, and the result of the inverted AND is output as the row address enable signal PDRAEB. Here, the NAND gate 460 is a logic combining means for generating the row address enable signal PDRAEB, and may be implemented by a combination of other logic gates.

The row decoder 470 inputs and decodes a plurality of row addresses RAn applied through an address buffer (not shown) in response to the row address enable signal PDRAEB output from the NAND gate 460. The row addresses DRAjk and the block selection information BLSi are generated. Referring to FIG. 4, it is assumed that n of row addresses RAn applied from an address input terminal through an address buffer (not shown) is 0-11, and j and k of decoded addresses DRAjk are 0-8. Assume In addition, it is assumed that i of the block selection information BLSi for selecting one of the plurality of banks is 0 to 7.

A process of generating the row address enable signal PDRAEB in the word line control circuit of FIG. 4 will be described in detail. That is, even when the low active signal BSENSE goes from the high level to the low level, the row address enable signal PDRAEB is generated by the signals S1 and S2 generated by the first and second signal generators 400 and 420. High level state can be maintained. For example, when the bank interleave operation selection signal S1 is high level and the column address input control signal S2 is low level when BSENSE is low level, the output of the NAND gate 454 becomes low level. The row address enable signal PDRAEB output at 460 is at a high level.

When the low active signal BSENSE is at the low level, the output of the NAND gate 454 is at a high level when the bank interleave operation selection signal S1 is at a high level and the column address input control signal S2 is at a high level. The row address enable signal PDRAEB is at a low level.

As described above, in the present invention, even when the low active signal BSENSE is at the low level, the row address enable signal PDRAEB is generated by the signals S1 and S2 generated by the first and second signal generators 400 and 402. Since it can be activated to a high level, the row decoder 470 may operate normally to generate decoded row address DRAjk and block selection information BLSi.

5 is a detailed circuit diagram of the row decoder 470 shown in FIG. Referring to FIG. 5, the row decoder 470 may include an address input unit 520, an address transmitter 530, a latch unit 540, an address output unit 560, and a block selection information generator 570.

The address input unit 520 of FIG. 5 inputs and combines the row addresses RA0 to RA11 applied to the address buffer (not shown), and outputs the combined result. Here, the address input unit 520 includes NAND gates 500 to 508 and inverters 510 to 518. That is, the NAND gate 500 inverts the AND by inputting the row addresses RA0 and RA1, and outputs the result of the inversion AND. The NAND gate 502 inputs the row addresses RA2 to RA4 to invert AND and output the result of the inverted AND. In addition, the NAND gate 504 inputs the row addresses RA5 and RA6 to invert AND and the NAND gate 506 inverts AND to the row addresses RA7 and RA8. In addition, the NAND gate 508 inverts ANDs the row addresses RA9 to RA11 and outputs the result of the inversion AND. The inverters 510 to 518 of the address input unit 520 invert the outputs of the NAND gates 500 to 508, respectively, and output the respective inverted results to the address transfer unit 530.

The address transmitter 530 includes an inverter 535 and transmission gates TG51 to TG55. In addition, the address transmitter 530 inputs the row address enable signal PDRAEB and the inverted signal of the PDRAEB output from the NAND gate 460 of FIG. 4 as a transmission control signal, respectively, and responds to the transmission control signal. The signals are applied to the inputs of the respective transmission gates TG51 to TG55.

The latch unit 540 includes a plurality of latches connected to output terminals of the transmission gates TG51 to TG55 of the address transmitter 530, respectively, and latches the transmitted address to output the latched result. That is, the first latch consists of inverters 541 and 542 connected to each other, the second latch consists of inverters 543 and 544, and the third latch comprises inverters 545 and 546. And a fourth latch consists of inverters 547, 548, and a fifth latch consists of inverters 549, 550.

The address output unit 560 includes inverters 561 to 565 connected to the outputs of the latches of the latch unit 540, and inverts the result output from the latches, and decodes the inverted result to the decoded row address ( DRAjk). That is, the address output from the inverter 561 is DRA01, the address output from the inverter 562 is DRA234, the address output from the inverter 563 is DRA56, and the address output from the inverter 564 is DRA78, and the address output from the inverter 565 is DRA91011.

The block selection information generator 570 is configured of serially connected inverters 572 and 574 to delay the decoded row address DRA91011 for a predetermined time to generate block selection information BLSi for selecting a plurality of banks.

That is, since the row decoder 470 illustrated in FIG. 5 can turn on the transmission gates TG51 to TG55 only when the row address enable signal PDRAEB is at a high level, the address combined in the address input unit 520 may be used. Can be transmitted. Accordingly, when the PDRAEB is activated at a high level, the row address RAn is input through an address input terminal and an address buffer (not shown), and the input row address is combined and latched to decode the block selection information BLSi. Generate a row address DRAjk.

6 is a waveform diagram illustrating a bank interleave operation in the word line control circuit according to the present invention. Referring to FIG. 6, T1 represents a time point when BSENSE is activated at a low level. That is, the row addresses X_ADD for the plurality of banks B0, B2, B4, and B6 are sequentially input based on the time point T1 when the BSENSE is activated at the low level. In addition, T2 represents a time point when BSENSE is inactive from a low level to a high level, and is a time point at which precharges of respective banks are made. That is, a plurality of bank addresses are sequentially applied based on the time point T2 when the BSENSE transitions to the high level. Referring to FIG. 6, in the present invention, row addresses of different banks may be input even in a period in which the low active signal BSENSE maintains a low level, and free in a period in which the low active signal BSENSE maintains a high level. A charge bank address can be entered. In addition, the period T61 in which the row address enable signal PDRAEB is at a low level indicates a time point at which the column address Y_ADD is received. In this case, the row address is no longer applied by setting the PDRAEB to a low level. To prevent it.

4 to 6, the operation of the word line control circuit for the bank interleave function according to the present invention will be described in detail as follows. First, the low active signal BSENSE is enabled when the bank interleave operation selection signal S1 applied through the first pad 402 or generated using the mode register setting MRS is enabled at a high level. In this case, the row address X_ADD of each bank is sequentially applied at the time point T1. Here, when the column address input control signal S2, that is, the write enable signal WE is activated, and the column active signal COLLAT is enabled, the row decoder 470 latches the input row addresses to form a word line. Enable At this time, as the row address enable signal PDRAEB becomes low level by the enabled column address input control signal S2, the row address is no longer applied, and the column address Y_ADD is applied through the address input terminal. Input to enable the bit line. That is, during the period T61 in which the row address enable signal PDRAEB is at the low level, the row address is no longer accepted.

In addition, when data writing for each bank is completed and the column address input control signal S2 becomes low level, the row address enable signal PDRAEB transitions to the high level again at the falling edge of S2. At this time, the addresses B0 to B6 of pre-charge banks are sequentially applied based on the time T2 at which BSENSE becomes a high level again, and the word line is disabled by the applied precharge bank address. do.

As described above, in the present invention, the signals merged by implementing the address can be accepted while the BSENSE is maintained using the signals S1 and S2 applied through the pad or generated by the mode register setting. In the active mode, bank interleave operation can be used efficiently.

According to the present invention, it is possible to reduce the test time during burn-in stress testing by efficiently performing the bank interleaving function in a merged low active mode (MERGED BSENSE) in a memory device having many banks such as Rambus DRAM. This has the effect of increasing productivity.

1 is a waveform diagram illustrating an operation in a conventional merged low active mode (Merged BSENSE).

2 is a diagram illustrating a conventional row address enable signal generation circuit.

3 is a waveform diagram illustrating a conventional bank interleave function.

4 is a circuit diagram of an embodiment for explaining a word line control circuit for the bank interleave function according to the present invention.

FIG. 5 is a detailed circuit diagram illustrating the row decoder of the word line control circuit shown in FIG. 4.

6 is a waveform diagram illustrating an operation of a word line control circuit for a bank interleave function according to the present invention.

Claims (3)

First signal generating means for receiving a predetermined function selection signal from the outside and delaying the function selection signal for a predetermined time and outputting it as a bank interleaving operation selection signal; Second signal generating means for receiving a write control signal externally and inverting the write control signal and outputting it as a column address input control signal; Row control means for logically combining the bank interleave operation selection signal and the column address input control signal and outputting the logical combined result as a row control signal; Logic combining means for logically combining the inverted row active signal and the row control signal and outputting the logical combined result as a row address enable signal; And And a row decoder sequentially inputting row addresses for a plurality of banks in response to the row address enable signal, and decoding the row addresses to generate decoded row addresses and block selection information. Line control circuit. The method of claim 1, And said bank interleave operation select signal and said column address input control signal are generated inside a memory device by a mode register setting. The method of claim 1, wherein the column address input control signal, And a write enable signal applied through the write enable signal input terminal.