KR100335268B1 - Multi-word line enable device using automatic refresh - Google Patents

Abstract

The present invention utilizes an automatic refresh cycle that uses multiple wordline enable operations in a synchronous DRAM to reduce test time and improve the operation of the chip by reducing the logic added for multiwordline enablement. The present invention relates to a multi-word line enable device using refresh.

Description

Multi-wordline Enable Device Using Automatic Refresh

The present invention relates to a multi-word line enable device using automatic refresh, and in particular, by using an automatic refresh cycle that uses a multi-word line enable operation in a synchronous DRAM, thereby reducing test time and adding for multi-word line enable. The present invention relates to a multi-wordline enable device using automatic refresh, which reduces chip logic and improves chip operation.

In general, automatic refresh or CAS BBeForras refresh (hereinafter referred to as CBR Refresh) is a refresh built in a DRAM chip instead of giving a refresh address from the outside. The address counter generates a row address to perform a refresh.

In 64K DRAM, a refresh control signal (/ REF) was given to an extra pin that was not used to decide whether or not to accept an internal address.

That is, if the refresh control signal / REF is " low " before the las control signal / RAS, the refresh is performed using an internally generated address in a subsequent cycle, and the address applied from the outside is Ignored

When one low address has finished refreshing, the internal address counter is ready for the next refresh cycle and is counted up by one bit.

This feature eliminates the need for a refresh address counter external to the DRAM.

On the other hand, when the refresh control pin is removed and the abnormal control signal sequence that is not used in the DRAM, that is, the cas control signal (/ CAS) becomes "low" before the las control signal (/ RAS) (referred to as CBR below CAS Before RAS) As a previous refresh control signal (/ REF) was input, a scheme for ignoring the external address and accepting the internal address has been designated as a standard since 256K DRAM.

In order for the CBR to be valid, the cas control signal (/ CAS) must be "low" before the cas control signal set-up time (referred to as t _CSR less than / CAS Set-up Time) than the las control signal (/ RAS), It must remain “low” for at least the CAS control signal hold time (referred to as t _CHR below / CAS Hold Time).

On the other hand, in the recent multi-bit test (Multi-Bit Test) adopted to shorten the test time in the high-density DRAM, abnormal combination of the word line enable control signal (/ WE) is activated as "low" when entering WCBR, that is, CBR. Use

In order to avoid confusion with this mode, a time provision is added to ensure that the wordline enable control signal / WE is "high" when entering the CBR.

1 is a circuit configuration diagram of a conventional refresh controller, as shown therein, a delay unit 3A for delaying a refresh command (Autorefresh) input from the outside for a predetermined time; A latch (3B) for latching an output of the delay unit (3A) to output a precharge signal; An inverter (I2) for inverting the precharge signal (precharge) latched from the latch (3B); A PMOS transistor PM1 that receives the output of the inverter I2 as a gate terminal and outputs a control signal auto #; An NMOS transistor NM1 connected in series with the PMOS transistor PM1 to receive a refresh command (Autorefresh) input from the outside through a gate terminal to precharge the control signal auto #; And inverters I3 and I4 connected to the connection point of the PMOS transistor PM1 and the NMOS transistor NM1 to buffer the control signal auto # and input the buffer signal to the latch 3B.

2A to 2D are timing diagrams of FIG. 1, which will be described below with reference to FIG. 2.

First, an external refresh command (Autorefresh) as shown in FIG. 2A is input to the delayer 3A, and outputs a delayed signal delayed for a predetermined time as shown in FIG. It is input to the gate terminal of the MOS transistor NM1.

When the refresh command Autohigh is input to the gate terminal of the NMOS transistor NM1 as "high" as shown in FIG. 2A, the NMOS transistor NM1 is turned on to turn on. Precharge the control signal auto # to " low "

On the other hand, the delay signal delay as shown in FIG. Outputs a precharge signal of " high "

As described above, the precharge signal precharge output from the latch 3B is inverted to “low” through the inverter I2, and then input to the gate terminal of the PMOS transistor PM1 to be input to the PMOS transistor PM1. By turning on, the control signal auto # in the "low" state as shown in (b) of FIG. 2 transitions to "high".

Thus, the conventional refresh controller is switched state at the falling edge of the same signal when the auto refresh signal is toggled.

That is, when an automatic refresh command is input as shown in FIG. 2A, the rising edge of the signal turns on the NMOS transistor NM1, which is a pull-down element of the circuit, to be turned on. 2, the output signal auto # is changed to " low ", and this value is stored in the latch 3B to set flip-flops by the NAND gates NAND1 and NAND2.

In addition, the rising edge of this signal transitions the delay node to " high " as shown in (c) of FIG. 2 by the delayer 3A, which is a low path modeling delay stage to ensure tRAS and tRP. The "high" rising edge of this delay node flips the output of the flip-flop, causing the precharge signal to be generated as shown in FIG.

FIG. 3 is a block diagram of a conventional refresh counter. As shown therein, an external address buffered from an address buffer (not shown) is counted from an external refresh command (Autorefresh) input from an external device to output a distributed internal address. Is composed of a plurality of frequency dividers 4A, 4B, and 4C.

Fig. 4 is an internal circuit diagram of the frequency dividers 4A, 4B, and 4C of the refresh counter, which is omitted since it is a general frequency divider which is a known technique.

In the conventional circuit, circuits of the frequency dividers 4A, 4B, and 4C whose clocks are rcnt_1 and rcntb_1, which are inputted from the front end or the command, are used.

rcntb_1 is a clock signal obtained by inverting rcnt_1.

This circuit is in the form of a simple ring oscillator that inverts the states of rcnt and rcntb at the falling edge of the copper signal by the clock signal rcnt_1.

5A to 5D are timing diagrams for FIG. 3, which will be described below with reference to FIG. 5.

First, when a refresh command (Autorefresh) as shown in FIG. 5A from the outside is input to the first frequency divider 4A, the first frequency divider 4A is an external address buffered from an address buffer (not shown). 5 is counted to output the first internal address int_add <0> distributed as shown in FIG. 5 (b), and the first internal address int_add <0> output from the first frequency divider 4A is set to the first number. A second internal address int_add <1> input to the second frequency divider 4B and distributed as shown in FIG. 5C is output, and a second internal address int_add output from the second frequency divider 4B. <1> is input to the third frequency divider 4C and outputs the third internal address int_add <2> distributed as shown in FIG.

Here, the conventional multi-word line enable technology will be described below.

The first is a method of testing the durability of a chip by repeatedly operating the chip in a very poor environment during a Qualification Test of a product.

Here, the operation of the chip means that the DRAM repeatedly executes the commands of Low Activation, Read / Write, and Pre-Charge. The durability of the unit cell device is tested by applying a high voltage to the word line compared to the operating power supply voltage.

In this case, in the conventional chip, one word line is normally enabled by one row active command, which causes an increase in test time.

Secondly, in the case of the conventional refresh counter, each internal counter has a simple ring oscillator structure. In this case, the low address that is currently activated in the chip cannot be known outside the chip. There was a problem.

That is, when a failure occurs during the test, the roo address where the failure occurs is unknown.

Accordingly, the present invention was devised to solve the above-mentioned problems, and by using an automatic refresh cycle that uses a multi-word line enable operation in a synchronous DRAM, the test time is reduced and multi-word line enable is performed. The aim is to provide a multi-wordline enable device using automatic refresh that reduces the additional logic to improve the operation of the chip.

1 is a circuit diagram illustrating a conventional refresh controller.

2A to 2D are timing diagrams of FIG. 1.

3 is a block diagram of a conventional refresh counter.

4 is an internal circuit diagram of the frequency divider of FIG.

5A to 5D are timing diagrams of FIG. 3.

6 is a block diagram of a multi-word line enable apparatus using automatic refresh according to the present invention.

7 is a circuit diagram illustrating a refresh controller in the block diagram of FIG. 6.

8A to 8E are timing diagrams for FIG. 7.

9A to 9E are simulation results for FIG. 7.

FIG. 10 is a block diagram illustrating a refresh counter in the block diagram of FIG. 6. FIG.

11 is an internal circuit diagram for the frequency divider of FIG.

12A to 12B are timing diagrams of FIG. 10.

13A to 13A are simulation result diagrams for FIG. 10.

<Explanation of symbols for the main parts of the drawings>

10: address buffer 20: mode register

30: refresh controller 40: refresh counter

50: Roo Predecoder 60: Roo Decoder

In order to achieve the above object, the present invention includes an address buffer for buffering an external address input from the outside; A mode register for outputting a test mode flag signal informing of entering a test mode by using a code not used in a mode register set cycle; A refresh controller which receives a test mode flag from the mode register and an auto refresh command from the outside and outputs a refresh control signal for controlling an auto precharge operation; A refresh counter which is controlled according to the auto refresh command and a bank address and outputs an internal address using a starting address first inputted when entering a test mode among external addresses buffered from the address buffer; A row free decoder controlled according to a refresh control signal of the refresh controller to decode an external address buffered from the address buffer in a normal operation and to decode an internal address input from the refresh counter in a test mode; And a row decoder to decode the address decoded by the row free decoder to drive the multi word lines in each bank.

In the present invention, a multi-word line is enabled at the time of an acknowledgment test, and a normal row path (using a circuit used for a conventional automatic refresh (or CBR refresh) and a circuit used for a mode register set) is used. This feature enables multi-word line enablement without modifying or affecting the normal row path, and improves the existing refresh counter's ability to accept external addresses using a simple ring oscillator method. The counter is incremented with a seed address.

Through this, in the existing refresh counter test mode, the address of the currently active active row is not known, but in the case of the present invention, it can be confirmed.

The operation principle according to the present invention will be described in detail as follows.

The 64 Mega or higher synchronous DRAM (SDRAM) consists of four or more internal banks.

Each bank is enabled by a bank address (hereinafter referred to as BA or BA) input in a row active cycle.

In this case, the bank enable means that the word lines of 4K cells are enabled in the case of 64 megabytes.

In normal operation of synchronous DRAM (SDRAM), word lines of more than 4K cells are not enabled at the same time.

That is, one low active command means that only one bank is enabled.

Refresh is usually 4K cycle or 8K cycle refresh at 64Mb.

In this case, 4K cycle means enabling and refreshing word lines (corresponding to 4 banks) of 16K cells at a time, which is half of that for 8K cycles. Enable at once.)

That is, 2 to 4 times word lines are enabled at once according to the refresh selection (Option) with respect to the normal.

In the refresh process, precharge of automatically enabled word lines is performed by an internal simulator made by modeling the time when the cell is refreshed to ensure tRAS and tRP. At the end of one refresh cycle.

FIG. 6 is a block diagram of a multi-word line enable apparatus using automatic refresh according to the present invention. As shown therein, an address buffer 10 for buffering an external address input to an address pad (not shown); A mode register 20 which receives the buffered address information from the address buffer 10 and outputs a test mode flag, and receives a test mode flag and a refresh command from the outside from the mode register 20 to output a refresh control signal; A refresh controller 30 to receive a refresh controller 30, an external address buffered from the address buffer 10 and a refresh command received from the outside, and output a counted internal address, and a refresh control signal of the refresh controller 30 Is controlled according to the input from the refresh counter 40 And a and Lawrence predecoder 50 decodes the internal address, Lawrence decoder 60 for driving the multi-word line in each bank, decodes the internal address decoding from the Lawrence pre-decoder 50.

7 is a circuit configuration diagram of the refresh controller 30. As shown therein, a delay means 31 for delaying a refresh command (Autorefresh) input from the outside for a predetermined time and an output of the delay means 31 are shown. A latch means 32 for latching and outputting a precharge signal, a precharge signal fed back from the latch means 32 and a test mode signal TM input from the mode register 20. And a control means 33 for receiving a refresh signal Autorefresh input from the outside and outputting a control signal auto # and a buffering control signal auto # output from the control means 33 to the latch means. The buffer means 34 which inputs to 32 is comprised.

The delay means 31 and the latch means 32 have the same configuration as the delayers 3A and the latches 3B of the conventional refresh controller, and a detailed description thereof will be omitted.

The control means 33 receives an inverter I31 for inverting a precharge signal fed back from the latch means 32 and the output of the inverter I31 through a gate terminal to depress the power supply voltage. -Is connected in series to the PMOS transistor PM31 for up-up, the inverter I32 for inverting the test mode signal TM input from the mode register 20, and the PMOS transistor PM31 in series, A NMOS transistor NM31 for receiving the output of I32 as a gate terminal and precharging the control signal auto #, and a drain terminal connected to a source terminal of the NMOS transistor NM31, are refreshed from the outside. A gate terminal is connected to the NMOS transistor NM32 for receiving a signal (Autorefresh) as a gate terminal and pulling down to a ground potential, and a bulk terminal of the NMOS transistor NM31. Constructed by the drain terminal and the source terminal and the common connection of the switch transistor (PM31) comprises a PMOS transistor (PM32) for outputting a control signal (auto #).

The buffer means 34 is connected to the connection point of the PMOS transistors PM31 and PM32 and the NMOS transistor NM31 of the control means 33, and buffers the control signal auto # to latch the latch means. It consists of an even number of inverters (two in the figure, I33 and I34) input to (32).

8A to 8E are timing diagrams of FIG. 7, and FIGS. 9A to 9E are simulation diagrams showing simulation results of FIG. 7, with reference to FIGS. 8 and 9. The operation of FIG. 7 is as follows.

First, a refresh command (Autorefresh) as shown in FIGS. 8 and 9 (a) input from the outside is input to the delay unit 31 and delayed for a predetermined time as shown in FIGS. 8 and 9 (d). Is output to the gate terminal of the NMOS transistor NM32 of the control means 33.

As shown in the above operation, in the state in which the refresh command (Autorefresh) is input to " high " as shown in FIGS. 8 and 9, the gate terminal of the NMOS transistor NM32. As described above, when the test mode signal TM having the "high" level is input to the inverter I32 of the control means 33, the signal inverted to the "low" level through the inverter I32 is applied to the NMOS transistor NM31. Input to the gate terminal, the NMOS transistor NM31 is turned off.

By the turn-off operation of the NMOS transistor NM31, the PMOS transistor PM32 having a gate terminal connected to the bulk terminal of the NMOS transistor NM31 is turned on, so that the PMOS transistor PM32 is turned on. By precharging the power supply voltage by the turn-on operation, the control signal auto # of " high " level is output to the buffer means 34 as shown in Figs.

The "high" level control signal auto # as shown in FIGS. 8 and 9 (C) buffered through the inverters I33 and I34 of the buffer means 32 is connected to the NAND gate of the latch means 32. The delay signal (delay) as shown in (D) of FIG. 8 and FIG. 9 which is input to the NAND31 and delayed for a predetermined time from the delay means 31 is input to the NAND gate NAND32 of the latch means 32, 8 and 9, the precharge signal is not output.

Accordingly, the present invention uses a code MRS, which is not currently used and reserved in the set cycle of the mode register 20 used in the existing circuit, to signal a test mode (hereinafter referred to as TM). Make.

This signal is sent to the refresh controller 30 to prevent the automatic precharge operation described above from occurring.

In this case, when the automatic refresh command is input under the test mode, the multi word line is enabled.

In other words, the situation is the same as that of the normal row enable except that the external address is not accepted and the multi-word line is enabled.

In this case, the row address provided to the row predecoder 50 is not an address applied externally, but an internal address generated by the refresh counter 40.

At this time, the refresh counter 40 receives an external address at the time of automatic refresh that is applied for the first time after entering the test mode.

Subsequently, when the chip is tested for acceptance, the chip first enters the test mode, and when the chip is operated, the automatic refresh command is used instead of the ROH active command, and the start address is applied only once with the initial automatic refresh command. .

In this way, the test time can be reduced by 1/2 to 1/4 times according to the refresh selection.

10 is a block diagram of the refresh counter 40. As shown therein, an external address (ext_add) buffered from the address buffer 10 receives a refresh signal Autorefresh and a bank address BA input from the outside. ) And a plurality of frequency dividers 41, 42, 43 for outputting the distributed internal address int_add.

In the present invention, the refresh counter 40 shows only three stages.

The number of steps depends on the number of addresses required.

Compared to the conventional circuit, it can be seen that three signals (refresh signal Autorefresh, bank address BA, and external address ext_add buffered from the address buffer 10) are added for each step.

FIG. 11 is an internal circuit diagram of the frequency dividers 41, 42, and 43 of the refresh counter 40. The logical AND logic logic node NAND41 and the pass transistor T41 are added to the rcntb node to accept an external address. It is a form.

12A to 12B are timing diagrams of FIG. 10, and FIGS. 13A to 13A are simulation diagrams showing simulation results of FIG. 10. FIG. 12 and FIG. The operation of 10 is as follows.

First, a refresh signal (Autorefresh) as shown in FIGS. 12 and 13 is input from the outside into the logical product calculation logic NAND41 of the first frequency divider 41, and also shown in FIGS. When the same bank address BA is input, the AND logic NAND41 inputs a "low" level to the gate terminals of the PMOS and NMOS transistors of the pass transistor T41 by the inverse AND logic. .

In such a state, since the external address ext_add buffered from the address buffer 10 turns on the pass transistor T41 as shown in FIGS. 12 and 13 (C), the first frequency divider 41 is used. Counts an external address buffered from the address buffer 10 and outputs the first internal address int_add <0> distributed as shown in FIGS. 12D and 13B.

The first internal address int_add <0> as shown in FIGS. 12D and 13B output from the first frequency divider 41 is input to the second frequency divider 42. In the same state, since the external address ext_add buffered from the address buffer 10 turns on the pass transistor T41 as shown in FIGS. 12E and 13D, the second frequency divider 42 ) Outputs a second internal address int_add <1> distributed as shown in FIGS. 12A and 13G.

The second internal address int_add <1> as shown in FIG. 12 (bar) and FIG. 13 (G) output from the second frequency divider 42 is input to the third frequency divider 43. In the same state, since the external address ext_add buffered from the address buffer 10 turns on the pass transistor T41 as shown in FIG. 13E, the second frequency divider 42 of FIG. ) And outputs the third internal address int_add <2>.

Therefore, as shown in the simulation diagram of FIG. 13, although the start address is indicated as "0" in this figure, the start address set by the refresh counter 40 cannot be known in the actual operation.

Referring to the waveform of the present invention, the bank addresses as shown in FIG. 13B input together with the auto refresh signal input as shown in FIG. The external address is set to each refresh counter 40 as shown in FIG. 2, and it can be seen that the external address changes according to toggling of the auto refresh signal.

In the automatic refresh situation, the bank address is don't care.

Therefore, in the present invention, one bank address is used as a flag that causes the refresh counter 40 to accept the start address.

It can be seen that each internal address in the figure has a unity force and wraps around, as shown in FIGS.

Accordingly, in the present invention, as in the circuit of the refresh controller 30 modified to prevent the generation of the precharge signal automatically generated in the refresh situation, the test mode signal ( If TM) is "high", that is, the flip-flop is prevented from being set by the automatic refresh command when entering the test mode, and thus the precharge signal is not generated.

As described in detail above, the present invention can reduce the test time by enabling the multi-word line to be enabled during the chip's acceptance test, and enable the multi-word line by modifying some of the existing normal instructions. For this purpose, there is no addition of a large number of circuits and deformation of the row path as is conventionally performed, thereby improving chip operation.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and changes belong to the following claims Should be seen.

Claims (5)

An address buffer for buffering an external address input from the outside; A mode register for outputting a test mode flag signal informing of entering a test mode by using a code not used in a mode register set cycle; A refresh controller which receives a test mode flag from the mode register and an auto refresh command from the outside and outputs a refresh control signal for controlling an auto precharge operation; A refresh counter which is controlled according to the auto refresh command and a bank address and outputs an internal address using a starting address first inputted when entering a test mode among external addresses buffered from the address buffer; A row free decoder controlled according to a refresh control signal of the refresh controller to decode an external address buffered from the address buffer in a normal operation and to decode an internal address input from the refresh counter in a test mode; And And a row decoder configured to decode the address decoded by the row free decoder to be subdivided into each bank to drive the multi word lines in the respective banks. The method of claim 1, The refresh controller, Delay means for delaying the auto refresh command for a predetermined time; Latch means for latching an output of said delay means to output a precharge control signal for controlling an auto precharge operation; Control means controlled in accordance with the precharge control signal fed back from the latch means and outputting a control signal using a test mode flag signal input from the mode register and the auto refresh command; And And a buffer means for buffering a control signal output from said control means and inputting it to said latch means. The method of claim 2, The control means, A first inverter for inverting the precharge control signal fed back from the latch means; A second inverter for inverting a test mode flag signal input from the mode register; A first PMOS transistor connected in series between a power supply voltage and a ground voltage and receiving an output of the first inverter through a gate terminal, a first NMOS transistor receiving an output of the second inverter through a gate terminal and the auto refresh; A second NMOS transistor receiving a command through a gate terminal; And And a second PMOS transistor having a gate terminal and a drain terminal connected to an output terminal formed by a common connected drain of the first PMOS transistor and the first NMOS transistor, and to which a power supply voltage is applied to a source. Multi-wordline enable device using automatic refresh. The method of claim 1, The refresh counter, And a plurality of frequency dividers controlled according to the auto refresh command and a bank address to output an internal address using an external address buffered from the address buffer. The method of claim 4, wherein Each frequency divider, Arithmetic logic for logically combining the auto refresh command and a bank address; And And a pass transistor which is controlled according to an output signal of the operation logic and selectively transmits a staring address first input when entering a test mode from an external address buffered from the address buffer to an output terminal. Multi-wordline enable device.