KR100873618B1 - Word-Line Test Control Circuit - Google Patents

Abstract

The word line test control circuit of the present invention includes: a burn-in test control unit which receives a burn-in test signal and logically combines it to output a test enable signal; A precharging control unit configured to receive a test enable signal, a bank active signal, and a multi-word line test signal and to logically combine the test enable signal to output a row decoder control signal; And a row decoder control unit for activating or deactivating the wordline off signal according to the row decoder control signal. It characterized by having a.

Probe Test, Wordline Test, Precharging

Description

Word Line Test Control Circuit {Word-Line Test Control Circuit}

1 is a block diagram of a burn-in and wordline test control circuit according to the prior art;

2 is a timing diagram of a burn-in and word line test control circuit according to the prior art;

3 is a block diagram of a wordline test control circuit according to an embodiment of the present invention;

4 is a detailed circuit diagram of the burn-in test control unit shown in FIG.

5 is a detailed circuit diagram of the precharging control unit shown in FIG. 3;

6 is a detailed circuit diagram of the row decoder control unit shown in FIG. 3;

7 is a timing diagram of a wordline test control circuit in accordance with the present invention;

8 is a block diagram of a wordline test control circuit according to another embodiment of the present invention;

FIG. 9 is a detailed circuit diagram of the precharging control unit shown in FIG. 8;

FIG. 10 is a detailed circuit diagram of the burn-in test control unit shown in FIG. 8.

<Description of Symbols for Main Parts of Drawings>

100, 110, 120: burn-in test control unit 200: row decoder control unit

300: main word line control unit 400, 430: precharging control unit

410: first logic unit 420: second logic unit

TECHNICAL FIELD The present invention relates to semiconductor integrated circuits, and more particularly, to word line test control circuits.

Burn-in test is a method of stressing cells and devices by applying a high voltage or high temperature to stabilize the characteristics of the semiconductor memory circuit. Burn-in test methods include an all wordline test, an even wordline test, and an odd wordline test. Each test method applies a high voltage stress to a corresponding word line for a predetermined time. An all-word line test activates all word lines in a bank, and an even word line test checks all word lines corresponding to an even word line. The active word line test activates all word lines corresponding to the odd word line.

Quarterly word line testing can differentiate between high and low leakage failures due to voltage drops when adjacent cell gates are activated in a bulb recess gate cell. This is a test to use.

The method divides all word lines in the bank into four blocks, performs the word line test of the first block, and when the word line test of the first block ends, performs the word line test of the second block, and the second quarter word. When the line test ends, the third quarter wordline test is performed until the end of the last test. The word lines are divided into 1, 2, 3, 4, 1, 2, 3, 4,.. Corresponds to, 1,2,3,4 blocks. That is, if one word line corresponds to the first block, two word lines adjacent to the word line correspond to the second block and the fourth block, respectively.

1 is a block diagram of a burn-in and wordline test control circuit according to the prior art.

The burn-in and word line test control circuit shown in FIG. 1 is composed of a burn-in test control unit 100, a row decoder control unit 200, and a main word line control unit 300.

The burn-in test control unit 100 includes an all wordline test signal TAWL, an even wordline test signal TEWL, an odd wordline test signal TOWL, and a quarter word. The line test signal T14WL is input and logically combined to output a test enable signal TALLWD.

In addition to the burn-in test, as illustrated in FIG. 1 for a quarter-word line test, the burn-in test control unit 100 performs the four-minute test in addition to the all / even / or word line test signals TAWL, TEWL, and TOWL. 1 word line test signal T14WL is inputted.

Accordingly, the burn-in test control unit 100 is a test that is activated when the test mode of one of the all wordline test, the even wordline test, the odd wordline test, and the quarter wordline test is executed. Outputs the enable signal TALLWD.

The quarter word line test signal is a signal that is activated during the quarter word line test, and the all word line test signal TAWL is a signal that is activated during the all word line test. The even / or word line test signal TEWL / TOWL is a signal that is activated during the even / or word line test.

The row decoder control unit 200 receives the test enable signal TALLWD and the input signals R1ACB, R2ACB, BSB, and NXEN, and outputs a wordline off signal WLOFF. The test enable signal TALLWD. When () is activated, the word line off signal WLOFF is deactivated, and when the test enable signal TALLWD is deactivated, the word line off signal WLOFF is controlled according to the input signal.

That is, when the test enable signal TALLWD is activated, the test mode is entered and the wordline off signal WLOFF is deactivated irrespective of the input signal, and when the test enable signal TALLWD is deactivated, the normal state is normal. The word line off signal WLOFF, which is controlled by the input signal, is outputted after entering the operation mode.

The R1ACB signal is a signal related to whether the word line off signal WLOFF is enabled during an active / precharging operation, and is a signal in which a bank active signal BA <i> is delayed for a predetermined time. The R2ACB signal is a signal related to whether or not the row decoder enable signal XDEC_EN is enabled during an active / precharging operation, and is a signal in which the bank active signal BA <i> is delayed for a predetermined time. The BSB signal is a cell mat select signal in a bank, and the NXEN signal is a row address enable signal.

The main word line control unit 300 outputs an inversion signal MWLB of the main word line signal controlled by the word line off signal WLOFF. The main word line control unit 300 is controlled by the main word line enable signal and the row decoder enable signal XDEC_EN in addition to the word line off signal WLOFF to convert the inverted signal MWLB of the main word line signal. Output

The main word line enable signal MWD_EN is a signal related to the enable of the main word line, and the row decoder enable signal XDEC_EN is a signal related to the enable of the row decoder.

The operation of the burn-in and word line test control circuit shown in FIG. 1 will now be described.

During the all wordline test, since the all wordline test signal TAWL is activated, the burn-in test control unit 100 outputs the activated test enable signal TALLWD. Accordingly, the row decoder control unit 200 receiving the activated test enable signal TALLWD receives the word line off signal WLOFF which is deactivated regardless of the level of the input signals R1ACB, R2ACB, NXEN, and BSB. ) Therefore, the main word line control unit 300 receives the deactivated word line off signal WLOFF to deactivate the inverted signal MWLB of the main word line signal. Thus, an all word line test is performed in which all main word lines are energized with high voltage applied thereto.

In the case of the even word line test and the odd word line test, since the inverted signal of the main word line signal is inactivated, it corresponds to the word line and the odd word line corresponding to the even word line by an internal circuit in the semiconductor integrated circuit although not shown. Activates the word line. Accordingly, an even word line test and an odd word line test are performed, in which the even word line and the odd word line are respectively applied with a high voltage for a predetermined time.

Problems of the burn-in and wordline test control circuits according to the prior art arise during quarter-wordline testing. In the same structure as the conventional quarter-word test control circuit, the output signal of the burn-in test control unit 100 is configured such that the main word lines of all banks are activated regardless of the active command.

In the quarter word line test mode, the quarter word line test signal T14WL is activated, and as in the all-word line test, the main word line signal MWL is activated. Although not shown, when entering the quarter word line test mode, when the main word line signal MWL is activated, a quarter word line in the bank is activated, and then a precharging operation is performed. The next quarter word line is activated, and then a series of processes are performed in which the precharging operation is performed.

However, even during the precharging operation, the word line off signal WLOFF is still unconditionally deactivated so that the main word line signal MWL is always activated so that the precharging operation is not performed.

That is, in a quarter-word line test mode, the word line of the first block is still turned on, and if the word line of the second block is turned on by the next active operation, the word lines of the first block and the second block are both turned on. If this is done four times, all word lines are turned on, causing problems on a quarter word line test.

2 is a timing diagram of a burn-in and wordline test control circuit according to the prior art.

In the quarter test mode, the quarter test signal T14WL is activated. Thus, the test enable signal TALLWD, which is the output of the burn-in test control unit 100, is activated. In bank 0, as the active command signal is activated, the word line off signal WLOFF0 is deactivated, and the inversion signal MWLB0 of the main word line signal is also deactivated to turn on the corresponding word line. Thereafter, even when the active command signal of the bank 0 is inactivated, the word line off signal WLOFF0 and the inversion signal MWLB0 of the main word line signal are inactive, so that the corresponding word line is still turned on. Will be maintained. As a result, the precharging operation is not performed. If the operation continues, all word lines are turned on during the quarter test. The same applies to the case of bank 3 as shown in FIG.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, a word line that can test a function such as read, write operation by performing a precharge command after the active command in the multi-word line test It is an object to provide a test control circuit.

According to another aspect of the present invention, there is provided a word line test control circuit including a burn-in test control unit configured to receive a burn-in test signal and output a test enable signal by logically combining the test enable signal; A precharging control unit receiving a word line test signal and performing logical combination to output a row decoder control signal; And a row decoder control unit for activating or deactivating a wordline off signal according to the row decoder control signal.

A precharging control unit may receive a word line test control bank active signal and a multi word line test signal and logically combine the output lines to output a precharging control signal according to another exemplary embodiment of the present invention; A burn-in test control unit configured to receive a logic combination and output a row decoder control signal; And a row decoder control unit for activating or deactivating a wordline off signal according to the row decoder control signal.

Details of the above object and technical configuration of the present invention and the resulting effects thereof will be more clearly understood from the following detailed description based on the accompanying drawings.

In addition, the present invention can be applied not only to a quarter word line test but also to other multi-word line tests such as one third and fifth word line tests. Hereinafter, the present invention is a multi-word line test signal (T1NWL), which is a case in which a test is performed by dividing a total word line including a quarter word line test signal (T14WL) and the like by N / N (N is a natural number). Will be described as is entered.

3 is a block diagram of a wordline test control circuit in accordance with the present invention.

As shown, the wordline test control circuit of the present invention includes a burn-in test control unit 110, a precharging control unit 400, a row decoder control unit 200, and a main wordline control unit 300.

The singer burn-in test control unit 110 receives the burn-in test signals TAWL, TEWL, and TOWL and performs a logical combination to output a test enable signal TALLWD. The burn-in test control unit 110 outputs a test enable signal TALLWD that is activated when any one of the burn-in test signals TAWL, TEWL, and TOWL is activated. That is, when the burn-in test control unit 110 enters one of the burn-in test modes, the burn-in test control unit 110 performs a test operation and outputs a test enable signal TALLWD, which is a control signal for stopping the normal operation.

The burn-in test control unit 110 differs from the burn-in test control unit 100 shown in FIG. 1 in that the quarter word line test signal T14WL shown in FIG. 1 is not input. As a result, the wordline test control circuit according to the present invention outputs a wordline off signal WLOFF that is activated or deactivated according to the active mode and the precharge mode.

The precharging control unit 400 receives the test enable signal TALLWD, the bank active signal BA <i> and the multi-word line test signal T1NWL, and logically combines the row decoder control signal TALLWD_BAI. Outputs The precharging control unit 400 outputs an activated low decoder control signal TALLWD_BAI when the test enable signal TALLWD is enabled. In addition, when the test enable signal TALLWD is disabled and the multi-wordline test signal T1NWL is enabled, the precharging control unit 400 according to the bank active signal BA <i>. Outputs the activated or deactivated row decoder control signal TALLWD_BAI. In addition, the precharging control unit 400 outputs an inactivated row decoder control signal TALLWD_BAI when both the test enable signal TALLWD and the multi-word line test signal T1NWL are disabled.

The row decoder control unit 200 activates or deactivates the word line off signal WLOFF according to the row decoder control signal TALLWD_BAI. The row decoder control unit 200 outputs a signal for controlling the row decoder, and generates the word line off signal WLOFF according to the input signals R1ACB, R2ACB, NXEN, and BSB in addition to the row decoder control signal TALLWD_BAI. do.

The main word line control unit 300 controls the main word line signal according to the word line off signal WLOFF. The main word line control unit 300 is implemented by a general main word line control circuit.

4 is a detailed circuit diagram illustrating an embodiment of the burn-in test control unit 110 shown in FIG. 3.

As illustrated, the burn-in test control unit 110 receives the all wordline test signal TAWL, the odd wordline test signal TOWL, and the even wordline test signal TEWL, and performs an OR operation to test enable the test enable unit 110. Output the signal TALLWD.

Therefore, when any one of the all word line test signal TAWL, the odd word line test signal TOWL, and the even word line test signal TEWL is at a high level, the test enable signal TALLWD is high. Level.

FIG. 5 is a detailed circuit diagram of the precharging control unit 400 shown in FIG. 3.

As shown, the precharging control unit 400 includes a first logic unit 410 and a second logic unit 420.

The first logic unit 410 receives the multi-word line test signal T1NWL and the bank active signal BA <i> and performs a logical multiplication to output a precharging control signal PRCHA_CTRL. Accordingly, the first logic unit 410 may be implemented by the NAND gate ND1 and the inverter IV2 as shown in FIG. 5.

The second logic unit 420 performs an OR operation on the precharging control signal PRCHA_CTRL and the test enable signal TALLWD to output a row decoder control signal TALLWD_BAI. Accordingly, the second logic unit 420 may be implemented by the NOR gate NOR2 and the inverter IV3 as shown in FIG. 5.

In the multi-word line test, the multi-word line test signal T1NWL is enabled, the bank active signal BA <i> is activated according to an active command, and the precharging control signal PRCHA_CTRL is enabled. Therefore, the output of the second logic unit 420 outputs the enabled row decoder control signal TALLWD_BAI since the precharging control signal PRCHA_CTRL is an enabled signal.

In addition, in the multi-wordline test mode, the bank active signal BA <i> is inactivated according to a precharging command, and thus the precharging control signal PRCHA_CTRL is disabled. Accordingly, since the output of the second logic unit 420 is a signal in which the precharging control signal PRCHA_CTRL is disabled, and the test enable signal TALLWD is also a disabled signal, the disabled row decoder control signal is disabled. Outputs (TALLWD_BAI).

Accordingly, since the row decoder control signal TALLWD_BAI is at a different level according to the active mode and the precharging mode during the multi-word line test, the row decoder control unit receiving the row decoder control signal TALLWD_BAI and proceeding thereafter is performed. The output of the 200 and the main word line control unit 300 can operate normally.

FIG. 6 is a detailed circuit diagram illustrating an embodiment of the row decoder control unit 200 shown in FIG. 3.

As illustrated, the row decoder control unit 200 may include a plurality of inverters IV5 to IV15 that receive and logically combine the input signals R1ACB, R2ACB, NXEN, BSB and the row decoder control signal TALLWD_BAI. It is composed of a plurality of NAND gates ND3 to ND9.

When the row decoder control signal TALLWD_BAI is at a high level, the row decoder control unit 200 has a potential of the first node N1 at a low level, and the output of the fourth NAND gate ND4 is at the output of the R2ACB and BSB. High level regardless of signal. Thus, the word line off signal WLOFF is fixed at a low level.

In addition, when the row decoder control signal TALLWD_BAI is at a low level, the row decoder control unit 200 has a high potential of the first node N1, and the output of the fourth NAND gate ND4 is It has the level of the logical sum of the BSB, R2ACB signal. Therefore, the word line off signal WLOFF is a signal obtained by delaying the output of the fourth NAND gate ND4 by a predetermined time.

Referring to Figures 3 to 6 will be described the operation of the word line test control circuit according to the present invention.

In the multi-wordline test, the multi-wordline test signal T1NWL is enabled. In addition, the all word line test signal TAWL, the even word line test signal TEWL, and the odd word line test signal TOWL are disabled, and thus the test enable signal TALLWD is inactivated.

Thereafter, since the bank active signal BA <i> is enabled according to an active command, the row decoder control signal TALLWD_BAI is activated, and thus the wordline off signal WLOFF is inactivated. The inversion signal MWLB of the word line signal is inactivated. Thus, one-N word lines (N is a natural number) of all word lines in the multi-mode are turned on.

Thereafter, since the bank active signal BA <i> is disabled according to a precharging command, the row decoder control signal TALLWD_BAI is inactivated, and thus the wordline off signal WLOFF is activated. The inversion signal MWLB of the main word line signal is activated.

Thus, one-Nth word line in the multi mode is turned off. Therefore, in the subsequent active operation of the next Nth word line, the word line which first performed the active operation is turned off, and only the corresponding word line is turned on so that the multi-word line test is normally performed. Proceed.

In addition, during the all wordline test, the even wordline test, and the odd wordline test, the test enable signal TALLWD is activated, so that the row decoder unit 200 activates the test enable signal TALLWD. Therefore, the word line off signal WLOFF is inactivated. Therefore, the inversion signal MWLB of the main word line signal is inactivated and the word line is turned on.

In addition, in the normal operation mode, the all wordline test signal TAWL, the even wordline test signal TEWL, the odd wordline test signal TOWL, and the multi-wordline test signal T1NWL are all disabled. Therefore, all of the test enable signals TALLWD are inactive. Therefore, the output of the row decoder control unit 200 performs a normal operation according to the input signals R1ACB, R2ACB, NXEN, BSB.

This implements a wordline test control circuit capable of operating in the normal operating mode, the burn-in test mode, and the multi test mode.

7 is a timing diagram of a wordline test control circuit in accordance with the present invention.

When the active command signal BA <0> of the bank 0 is activated, the word line off signal WLOFF0 is inactivated. Therefore, the inversion signal MWLB0 of the main word line signal is inactivated and the corresponding word line is turned on.

Thereafter, when the active command signal of the bank 0 is inactivated according to a precharging command, the word line off signal WLOFF0 is activated, and the inversion signal MWLB0 of the main word line signal is also activated. Therefore, the corresponding word line is turned off in an operation for precharging. Thus, in the precharging mode, the wordline off signal WLOFF0 is activated. In this way, in accordance with the active and precharging commands, the wordline off signal is activated or deactivated to proceed active and precharging thereafter.

In addition, when the active command signal BA <3> of the bank 3 is activated, the word line test corresponding to the bank 3 is performed as in the case of the bank 1.

As described above, in the multi-word line test, active and precharging is performed for each bank, and one-by-n word lines are turned on and turned off during precharging, and the next one-nth word lines are turned on. And turn off during precharging.

8 is a block diagram illustrating another embodiment of a wordline test control circuit of the invention.

As shown, the wordline test control circuit shown in FIG. 8 includes a precharging control unit 430, a burn-in test control unit 120, a row decoder control unit 200, and a main wordline control unit 300. do.

The precharging control unit 430 receives the bank active signal BA <i> and the multi-word line test signal T1NWL and logically combines the precharging control signal PRCHA_CTRL to output the precharging control signal PRCHA_CTRL.

The burn-in test control unit 120 receives the output signal of the precharging control unit 430 and the burn-in test signals TAWL, TEWL, and TOWL and logically combines the output signal of the precharge control unit 430 to output the row decoder control signal TALLWD_BAI.

The row decoder control unit 200 activates or deactivates a word line off signal WLOFF according to the row decoder control signal TALLWD_BAI.

The main word line control unit 300 receives the word line off signal WLOFF and controls the main word line signal.

9 is a detailed circuit diagram of the precharging control unit 430 shown in FIG. 8.

The precharging control unit 430 receives the bank active signal BA <i> and the multi-word line test signal T1NWL and performs an AND operation to output the precharging control signal PRCHA_CTRL. As illustrated in FIG. 9, the precharging control unit 430 may be implemented by a NAND gate ND2 and an inverter IV4.

FIG. 10 is a detailed circuit diagram of the burn-in test control unit 120 shown in FIG. 8.

The burn-in test control unit 120 receives the precharging control signal PRCHA_CTRL, the all word line test signal TAWL, the even word line test signal TEWL, and the odd word line test signal TOWL. The OR operation is performed to output the row decoder control signal TALLWD_BAI. The burn-in test control unit 120 may be implemented with a NOR gate NOR3 and an inverter IV16.

Therefore, the precharge control signal PRCHA_CTRL is enabled only when the bank active signal BA <i> is enabled during the multi-mode word line test, so that the burn-in test control unit 120 and the The word line off signal WLOFF by the row decoder control unit 200 may be activated in the precharging mode and may be deactivated in the active mode.

Accordingly, in the multi-word line test, various functions can be tested by solving the problem that the word line is not turned off during precharging, which is a problem of the prior art.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof.

Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Therefore, the word line test control circuit of the present invention can perform the active mode and the precharging mode normally in the multi-word line test, and can test various functions, thereby increasing the efficiency of the test equipment.

The word line test control circuit of the present invention has the effect of shortening test time and increasing productivity by discriminating a fail for each function through a multi-word line test mode.

Claims (17)

A burn-in test control unit which receives the burn-in test signal and logically combines the burn-in test signal to output a test enable signal; A precharging control unit which receives the test enable signal, a bank active signal, and a multi-word line test signal, and logically combines the test enable signal to output a row decoder control signal; And A row decoder control unit for activating or deactivating a wordline off signal according to the row decoder control signal; And a word line test control circuit. The method of claim 1, The precharging control unit, Outputting the activated row decoder control signal when the multi word line test signal is activated and the bank active signal is enabled; And outputting the deactivated row decoder control signal when the multi word line test signal is activated and the bank active signal is disabled. The method of claim 2, The precharging control unit, A first logic unit receiving the multi-word line test signal and the bank active signal and performing an AND operation to output a precharging control signal; And A second logic unit for ORing the precharging control signal and the test enable signal; And a word line test control circuit. The method of claim 1, The row decoder control unit, And outputting the disabled wordline off signal when the row decoder control signal is activated. The method of claim 4, wherein The row decoder control unit, And outputting the wordline off signal that is enabled when the row decoder control signal is inactivated. The method of claim 1, And a main wordline control unit configured to receive the wordline off signal and control a main wordline signal. The method of claim 1, The burn-in test signal, And a word line test signal, an even word line test signal and an odd word line test signal. The method of claim 7, wherein The burn-in test control unit, And if any one of the all wordline test signal, the even wordline test signal, and the odd wordline test signal is enabled, outputting the activated test enable signal. The method of claim 1, The multi word line test signal, And when the bank active signal is activated, a signal for sequentially activating and deactivating one-quarter word lines of the total word lines in the bank. A precharging control unit which receives the bank active signal and the multi word line test signal and logically combines the precharge control signals to output a precharge control signal; A burn-in test control unit configured to receive the precharging control signal and the burn-in test signal and to logically combine the precharge control signal and output a row decoder control signal; And A row decoder control unit for activating or deactivating a wordline off signal according to the row decoder control signal; And a word line test control circuit. The method of claim 10, The precharging control unit, Outputting the activated precharging control signal when the bank active signal is enabled, And output the deactivated precharge control signal when the bank active signal is disabled. The method of claim 10, The precharging control unit, A first logic unit receiving the multi-word line test signal and the bank active signal and performing an AND operation; And a word line test control circuit. The method of claim 10, The row decoder control unit, And outputting the disabled wordline off signal when the row decoder control signal is activated. The method of claim 13, The row decoder control unit, And outputting the wordline off signal that is enabled when the row decoder control signal is inactivated. The method of claim 10, And a main wordline control unit configured to receive the wordline off signal and control a main wordline signal. The method of claim 10, The burn-in test signal, And a word line test signal, an even word line test signal, and an odd word line test signal. The method of claim 10, The multi word line test signal, And when the bank active signal is activated, a signal for sequentially activating and deactivating one-quarter word lines of the total word lines in the bank.

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