JPH01261752A - Memory test circuit - Google Patents

Abstract

PURPOSE:To easily test a RAM circuit by using a reading address supplied to a ROM circuit as a writing address to the RAM circuit and writing data read out from the ROM circuit into the RAM circuit. CONSTITUTION:At the time of testing the RAM circuit 2, a reading address signal 101 supplied to the ROM circuit 1 is used as a writing address of the RAM circuit 2. A reading data signal 102 read out from the ROM circuit 1 at that time is supplied to the RAM circuit 2 and the data are written by using the writing address. Even when addresses and data can not be easily suppled to the RAM circuit 2 due to the existence of many circuits connected to the prestage of the RAM circuit 2, the addresses and data can be easily supplied to the RAM circuit 2 by said procedure. Consequently, it is unnecessary to form an excess external terminal for testing the RAM circuit 2 and the RAM circuit 2 can be easily tested.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory test circuit, and more particularly to a RAM test method for a large-scale integrated circuit incorporating a ROM (read only memory) circuit and a RAM (random access memory) circuit.

Conventionally, in the RAM test method for this type of large-scale integrated circuit, when testing the RAM, the write address and write data for testing to the address register and data supply circuit for the RAM are transferred to the circuit in the previous stage of the RAM circuit. Created according to the number of stages, and write the created write address and write data to RA.
There is a method of testing by supplying it to the M circuit.

There is also a method of testing by directly supplying test write addresses and write data to the RAM circuit from external terminals of the large-scale integrated circuit.

In such conventional RAM test methods, write addresses and write data for testing are created according to the number of circuit stages in the preceding stage of the RAM circuit, so if the number of circuit stages in the preceding stage of the RAM circuit is deep, The disadvantage is that it is not easy to create write addresses and write data.

In addition, if the test write address and write data are directly supplied to the RAM circuit from an external terminal, it is easy to create the test write address and write data, but the absolute amount of external terminals is insufficient. In large-scale integrated circuits, it is difficult to provide external terminals for RAM testing.

The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and provides a memory test circuit that can easily test a RAM circuit without providing an external terminal for RAM testing. The purpose is to provide.

A memory test circuit according to the present invention is a memory test circuit for a large-scale integrated circuit having a read-only first storage means and a readable and writable second storage means, means for making a read address supplied to the first storage means a write address to the second storage means when testing the storage means; and means for writing data into the second storage means using the write address.

Kangai Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, a large-scale integrated circuit according to an embodiment of the present invention includes a ROM circuit 1, a RAM circuit 2, and a ROM address register circuit 3 , a RAM address register circuit 4, a RAM test instruction circuit 5, and a selection circuit 6.7.

When the ROM circuit 1 receives the read address signal 101 from the ROM address register circuit 3, it outputs the read data signal 102 to the selection circuit 7 and the next stage logic circuit (not shown).

When the RAM write signal 109 is input, the RAM circuit 2 writes the write data signal 108 from the selection circuit 7 to the address specified by the address signal 107 from the selection circuit 6. If not, the read data signal 110 read from the address specified by the address signal 107 from the selection circuit 6
is output to the next stage logic circuit (not shown).

The RAM test instruction circuit 5 receives the RAM test instruction signal 104
, 105 are output to the selection circuit 6.7, respectively.

The selection circuit 6 selects the read address signal 101 from the ROM address register circuit 3 and the RA according to the RAM test instruction signals 104 and 105 from the RAM test instruction circuit 5.
One of the address signals 103 from the M address register circuit 4 is selected and sent to RA as the address signal 107.
It is output to M circuit 2.

In response to the RAM test instruction signals 104 and 105 from the RAM test instruction circuit 5, the selection circuit 7 outputs a read data signal 102 from the ROM circuit 1 and a RAM write data signal 106 from a previous stage logic circuit (not shown). One of them is selected and sent to the RAM as the write data signal 108.
It is output to circuit 2.

Next, the operation of one embodiment of the present invention will be explained using FIG.

During normal operation, the RAM test instruction circuit 5 is at logic “0”.
Therefore, the RAM test instruction signal 104 becomes logic "0" and the RAM test instruction signal 105 becomes logic "1".
” becomes.

Therefore, the selection circuit 6 selects the address signal 103 from the RAM address register circuit 4, and this address signal 103 is sent to the RAM circuit 2 as the address signal 107.
is output to.

Further, in the selection circuit n7, the RAM write data signal 106 from the previous stage logic circuit is selected, and this RAM write data signal 106 is sent to the RA as the write data signal 108.
It is output to M circuit 2.

When performing a RAM circuit test, the RAM test instruction circuit 5 becomes logic "1", so the RAM test instruction signal 104 becomes logic "1", and the RAM test instruction signal 1
05 becomes logic "0".

Therefore, the selection circuit 6 selects the read address signal 101 from the ROM address register circuit 3, and this read address signal 101 is outputted to the RAM circuit 2 as an address signal 107.

Further, the selection circuit 7 selects the readout data signal 102 from the ROM circuit 1 and outputs this readout data signal 102 to the RAM circuit 2 as a write data signal 108.

As a result, a common address is given to the ROM circuit 1 and the RAM circuit 2 at the same time, so that the read data signal 102 read from the ROM circuit 1 is written to the RAM circuit 2. At this time, a RAM write signal 109 is input to the RAM circuit 2.

By sequentially adding up the ROM address register circuit 3, the above-described processing operation is repeated, and all addresses in the RAM circuit 2 are written by the read data signal 102 from the ROM circuit 1. This write operation is R
When the read address signal 103 from the OM address register circuit 3 reaches the highest address of the RAM circuit 2, it is stopped.

When writing of the read data signal 102 from the ROM circuit 1 to all addresses of the RAM circuit 2 is completed, the read address signal 101 is sequentially written to the ROM circuit 1 and the RAM circuit 2.
, the contents of ROM circuit 1 and RAM times F! The contents of @2 are sequentially read out, and the read data signal 102 from the ROM circuit 1 and the read data signal 11 from the RAM circuit 2 are read out sequentially.
The RAM circuit 2 is tested by being compared with 0 by a comparison circuit (not shown).

In this way, when testing the RAM circuit 2, the ROM circuit 1
The read address signal 101 supplied to the RAM circuit 2 is set as the write address of the RAM circuit 2, and the read data signal 102 read from the ROM circuit is supplied to the RAM circuit 2, and the data is written using the write address. By making use of the data stored in the ROM circuit 1, even in cases where addresses and data cannot be easily supplied to the RAM circuit 2 due to the large number of circuit stages preceding the RAM circuit 2, the data stored in the ROM circuit 1 can be used. Addresses and data can easily be supplied to RAM times FI&2.

Therefore, the RAM circuit 2 can be easily tested without providing an extra external terminal for testing the RAM circuit 2, and the reliability of the RAM circuit 2 can be improved. That is, the failure detection rate of RAM' times FI@2 can be improved.

As explained above, according to the present invention, when testing a read/write RAM circuit, the read address supplied to the read-only ROM circuit is used as the write address to the RAM circuit, and at this time, the ROM circuit By writing the data read from the RAM circuit into the RAM circuit using this write address, it is possible to easily test the RAM circuit without providing an external terminal for RAM testing. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1...ROM circuit 2...RAM circuit 5...RAM test tower illustration circuit 6...Selection circuit

Claims (1)

[Claims] (1) A memory test circuit for a large-scale integrated circuit having a read-only first storage means and a readable and writable second storage means, wherein the first storage means is tested when the second storage means is tested. means for setting a read address supplied to a storage means as a write address to the second storage means; and a means for writing data to the second storage means using the read address to write data to the second storage means using the write address. A memory test circuit characterized in that it is provided with means for writing to.