JPH0367188A - Ic tester - Google Patents

Abstract

PURPOSE:To generate many phase clocks by generating new access information by arithmetic operation and selecting either the new access information or access information without performing arithmetic operation. CONSTITUTION:The access information for reading out timing data TD by accessing the timing setting memory 8 of a timing generator 13 and selection information are stored in an instruction memory IM 2 in a pattern generator 3, the new access information is generated by the arithmetic operation in an arithmetic operation logical circuit (ALU) 4 without changing the access informa tion, and either the access information obtained by the arithmetic operation 4 or the access information without the arithmetic operation is selected based on the selection information, so that various kinds of access information is generated and replenished by the operation 4 even though many pieces of access information are not stored in the generator 3. Therefore, the access information is instantaneously generated in accordance with the number of generated TD and many phase clocks are generated without increasing the number of steps of a pattern program and an inspecting speed is prevented from lowering.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC tester, and more specifically, when performing an asynchronous test of an LSI, a large number of different The present invention relates to an IC tester that can select one of the phase clocks having a phase of and generate it in real time.

[Prior Art] FIG. 3 shows a conventional configuration of this type of IC tester, centering on a pattern generator section. In the same figure, 10 is
The CPU is a CPU that sets a program necessary for pattern generation in a pattern generation book 12 via an interface 11, and sets timing data for necessary timing generation in a timing generator 13. Data from the pattern generator 12 and timing generator 13 are sent to the pin electronics 18, and test patterns and the like are output from the pin electronics 18 to the device under test (DUT) 19 in correspondence with the pins.

In addition, 20 is a test voltage fE generation circuit, and the CPU
Based on the data from DUTl9.10, a bias voltage for DUTl9, a setting voltage for setting the level of a test pattern, etc. are generated, and DUTl9. The pin electronics 18 are respectively supplied.

The pattern generation change 12 usually includes an instruction memory 14 composed of ROM and RAM, a program counter 15, a controller 16, a pattern memory 17,
It is composed of a register 17a for storing a timing selection signal, etc., and contains sequence control data 9 (SQ) such as address control information for generating an address (A) for the instruction memory 14 and the next address for the pattern memory 17, and an index address. ) and a timing switching signal (
TC). Then, the sequence control data (SQ) is sent to the controller 16, and under the control of the controller 16, the address of the next instruction memory 14 is calculated and set in the program counter 15.
Alternatively, the program califter 15 is updated.

The pattern memory 17 is the instruction memory 14
It is accessed by the address information (A) sent from the controller and generates data such as address data, pattern data, and expected value data, and also generates read/write control signals (part of control information C) for DUTl 9. and sends them to pin electronics 18.

Timing generator 13 stores timing data received from CPU10 in timing setting memory. Each piece of timing data indicates the timing of a different phase, and the number gives the generated phase level (number of phases), one of which is selected by a timing switching signal (TC) obtained from the instruction memory 14.

Timing switching is performed by adding a timing switching signal (TC) to the address of the timing setting memory via the register 17a, but since this is added in real time, timing data of various phases are transferred from the timing setting memory in real time. is read out. The real-time timing data read out in this way is applied to a timing generation circuit, which generates a phase clock having a phase corresponding to the timing data using the rate signal as a reference, and this phase clock is used as a timing signal to externally output. Output to.

[Problem to be solved] By the way, in the testing of single-conductor storage devices such as VRAM and dual-port memory, recently there has been a so-called test that tests to what extent they operate stably even if they are out of synchronization with the reference clock. , there is a requirement for asynchronous testing. To perform this asynchronous test, since it is not possible to generate clocks completely asynchronously, we can generate a large number of phase clocks and sequentially generate phase clocks that are slightly out of phase with one of them, or with phase clocks that are slightly shifted in phase. The asynchronous test will be performed using the respective phase clocks.

Therefore, in order to perform an asynchronous test, it is necessary to generate a large number of phase clocks whose number of timings is nearly 1,000. This is a very large phase level (number of phases) compared to the conventional tens to tens of culms.Furthermore, since it has to be generated in real time, the instruction memory must be programmed in accordance with the number of timing occurrences. It is necessary to increase the number of steps or rewrite the program in the instruction memory each time the timing is changed. As a result, the number of steps in the overall pattern program increases,
Inspection speed decreases.

The present invention solves the problems of the prior art, and provides an IC tester that can generate timing signals with multiple phases in real time without increasing the number of pattern program steps. The purpose is to provide.

[Means for Solving the Problems] The configuration of the IC tester of the present invention to achieve such an object includes a register and an arithmetic operation for performing an arithmetic operation between the value of this register and the value given from the outside. The timing generator has a timing data memory storing various timing data. Then, access information and selection information for accessing the timing data memory are stored in the pattern generator, and the access information is added to the arithmetic logic circuit as a value given from the outside, and the access information calculated by the arithmetic logic circuit is One of information and access information is selected by selection information, and the timing data memory is accessed using the selected access information to select one of a large number of timing data.

[Operation] In this way, the access information and selection information for accessing the memory of the timing generator to read timing data are stored in the instruction memory, etc. inside the pattern generator, and arithmetic operations can be performed without changing the access information. In addition to generating new access information through calculations, it also selects between access information obtained as a result of arithmetic operations and access information without arithmetic operations according to selection information, so that a large amount of access information is not stored in the pattern generator. However, various access information can be generated additionally by forming tp using arithmetic operations.

Therefore, necessary access information can be generated in real time even if access information is not stored in the pattern generator according to the number of generated timing data, and a phase clock can be generated in real time accordingly. As a result, many phase clocks can be generated without increasing the number of steps in the entire pattern program, and the inspection speed does not need to be reduced.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram centered on the pattern generator portion of an embodiment to which the IC tester of the present invention is applied.
FIG. 2 is an explanatory diagram of data stored in the instruction memory of the pattern generator. In addition, components equivalent to those in the third garden will be designated by the same symbols.

In FIG. 1, l is a pattern generator, and a part of its instruction memory 2 is provided with a timing switching data area 3.

As shown in FIG. 2, this timing switching data area 3 includes an access information area 3a for accessing the memory of timing generation D13 and an arithmetic logic circuit (hereinafter referred to as ALU).
) a selection information area 3b for storing selection information on whether or not to select the output on the 4 side. The access information and selection information stored in these areas are transferred from the instruction memory 2 to the controller 16. pattern memory 1
It is read out together with the data added to 7. The read access information is sent to ALU 4 and selection circuit 5 in register 1.
7a and simultaneously read out from the instruction memory 2 (data stored in the pattern area 3d) is stored in the pattern memory 1.
7 to access that address.

As a result of this access, pattern data etc. are obtained from the pattern memory 17, some of them are sent to registers due to the delay, and after the timing is matched with the phase clock etc. obtained from the timing generator 13, the data is processed as before. Sent to pin electronics t8.

The selection circuit 5 receives the selection information read from the instructor memory 2 via the register 17a, and selects the selection information from the ALU.
4 or the access information of the instruction memory 2, and stores the selected information in the register 6 as the access information.

The ALU 4 receives the access information sent from the instruction memory 2 via the register 17a as an addition or subtraction value, and stores it in the register 6 to add or subtract (arithmetic operation) to the sorted previous access information. and
The result is sent to the selection circuit 5.

The register 6 sends the stored data (access information) to the address signal terminal (AI') of the timing setting memory 8 of the timing generator 13, and
It is also added to the input side of AlO2 to which it is added.

Here, the timing generator 13 is a timing generation circuit block 13a provided corresponding to the pin of DUTI9.
, 13b+..., and a timing generation circuit block 13al13b-...
A phase clock is input from a timing generation circuit block selected from among the timing generation circuit blocks iB to the pins of the DUTi 9, and is supplied to the pin electronics 18.

Each timing generation circuit block is composed of a timing setting memory 8 (as a specific example of the timing data memory of the present invention), a timing generation circuit 9, etc., and an address signal terminal (A D
R> is connected to the output of register 6. Here, the timing generation circuit 9 includes a counter, a rate signal generation circuit (or a test cycle signal generation circuit, not shown), a reference cross signal generation circuit, etc., and receives timing data read from the timing setting memory 8. The reference clock is counted up to the count value (timing data value) stored in this counter based on the rate signal stored in the counter and obtained from the rate signal generation circuit (or test periodic signal generation circuit), and this count is 41'L phase clock is generated at the point when r is completed.

FIG. 2 shows the storage state of data in the instruction memory 2, and when the flag as selection information stored in the selection information storage area 3b is "0", the corresponding access information area 3a is accessed. The information is address information for accessing the timing setting memory 8. Further, when the flag in the selection information area 3b is "1", the access information in the corresponding access information area 3a is a numerical value to be added or subtracted in AlO2.

Next, the overall operation will be explained with reference to FIG. 2.

When the program counter 15 is updated and the address Ai of the instruction memory 2 is accessed,
The address information "5" of the access information area 3a is read out, and at this time, the flag (selection information) of the selection information area 3b is "0", so the selection circuit 5 selects the output of the instruction memory 2, Address information "5" is sent to register 6. As a result, address 5 of the timing setting memory 8 is accessed, and the timing data stored at address 5 is added to the timing generation circuit 9. As a result, the timing generation circuit 9 generates a phase clock at the timing set by this timing data, and outputs it to the pin electronics 18.

Next, when the program counter 15 is incremented and the address AI+l of the instruction memory 2 is accessed, since the flag in the selection information area 3b is "1", the selection circuit 5 is switched to the AlO4 side. A selection circuit 5 selects the output of AlO2. At this time, AlO2 is supplied with the address information "5" of 1+iiJ from the register 6, so the access information of the address Ai"l added from the other hand manually"
“1” is added by “+1”, and as a result, address information of “6” is stored in the register 6. Then, address 6 of the timing setting memory 8 is accessed, and the timing data stored at address 6 is It is added to the timing generation circuit 9.

At this time, control information PiI (10 times) for accessing this address AI+l 10 times is stored in the sequence information area M3e of the instruction memory 2 of the address signal terminal. Therefore, this address is accessed 10 times in a row, and the above “+1” addition is 1
Performed 0 times. As a result, the addresses of the timing setting memory 8 are changed from address 6 to address 7, address 8, address 9, and 1.
Address 0, Address 11, Address 12, Address 13, Address 14, 1
Address 5 and 10 steps are accessed.

In this way, address information for 10 steps can be generated by accessing address signal terminals at the same address. As a result, the phase clock and phase shift set by each timing data stored in the accessed address can be obtained in real time.

Next, the program counter 15 is incremented and the address A1+2 of the instruction memory 2 is accessed, but at this time also the flag is set to "1".
'', and control information (rebby) 1 accesses address A1+2 10 times to sequence information area 3C.
0 times) is stored, the selection circuit 5
The output of ALU 4 remains selected, and this address is accessed ten times in succession. However, since the access information this time is "-1", the ALU 4 performs processing to subtract "1" from the value "15" in register 6.
Contrary to the above, the address of the timing setting memory 8 moves from address t5 to address 14, and the addresses 3, 12, ti, 10, 9, 8, 7, 6, 5 above address 14 are moved from address t5 to address 14. Address information for the address and 10 stenobes can be generated by accessing the address A1+2, which is the same address, and is output from the real-time timing generator 13 with a phase clock having a phase set by each timing data.

By doing the above, the instruction memory pattern program, which conventionally required 21 steps, can be reduced to 3 steps.
It can be done in steps.

As explained above, in the embodiment, the register for setting the ALU operation value is the address information from which the timing setting memory was accessed one time ago. If the register that stores the ALU result is set separately from the register that stores the previous address information, accessing the address of the timing setting memory will be based on the address information that was accessed immediately before. Without limitation, a value stored in this separately provided register can be determined as the augend value. Therefore, previously calculated address information can be used at any time.

□In this invention, the object of arithmetic operation is one +)i
It is not limited to the address information calculated in f.

[Effects of the invention 1-. As can be understood from the explanation, in the present invention, access information and selection information for accessing the memory of the timing generator to read timing data are stored in an instruction memory or the like inside the pattern generator. The system generates new access information by performing arithmetic operations on the access information without changing it, and also selects between access information obtained as a result of arithmetic operations according to the selection information and access information without arithmetic operations. Various types of access information can be generated by arithmetic operations and re-generated without storing a large number of information in a pattern generator.

Therefore, necessary access information can be generated in real time even if access information is not stored in the pattern generator according to the number of generated timing data, and a phase clock can be generated in real time accordingly. As a result, many phase curves can be generated without substantially increasing the number of stem knobs in the entire pattern proger, and the inspection speed can be maintained without decreasing.

[Brief explanation of drawings]

FIG. 1 is a block diagram centered on the pattern generator portion of an embodiment to which the IC tester of the present invention is applied, FIG. 2 is an explanatory diagram of data stored in the instruction memory of the pattern generator, and FIG. FIG. 3 is a block diagram centered on the pattern generator portion of a conventional IC tester. 1.12...Pattern generator. 2.14... Instruction memory, 3... Timing switching data area, 3a... Access information area, 3b... Selection information area, 4... Calculation logic circuit (
ALU), 5... Selection circuit, 6, 7... Register, 8... Timing setting memory, 9... Timing generation circuit, 1
0...CPU, 11...Interface, 13...
・Timing generation L15...Program counter, 1
6... Controller, 18... Pin electronics, 19... Device under test (CUT).

Claims (1)

[Claims] (1) In an IC tester equipped with a pattern generator and a timing generator having a timing data memory storing a large amount of timing data, an arithmetic operation is performed between a register and the value of this register and a value given from the outside. an arithmetic logic circuit that performs an arithmetic operation, the pattern generator stores access information and selection information for accessing the timing data memory, and the access information is used as a value given from the outside to perform the arithmetic operation. One of the access information and the access information calculated by the arithmetic logic circuit is selected by the selection information, and the timing data memory is accessed by the selected access information, and the timing data memory is accessed by the selected access information. An IC tester characterized in that one of timing data is selected.