JPH0927194A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction by non-activating an input gate of a latch circuit in case of activation of a signal based on the output of a rising detection circuit. SOLUTION: The output of a clocked inverter 33 is connected to an input node of an inverter 32 in a latch circuit 10, and latch constitution is formed. An output of the latch circuit 10 is an output of the inverter 32. Clocked inverters 33 and 31 are constituted so that either of them is operated by a control signal ATDL and an inversion signal. When an output signal OEC of an OE control circuit is 'L' state, the signal ATDL outputs a pulse in accordance with the signal ATD, when the OEC is a 'H' state, the signal ATDL is fixed to L. Thereby, while the OEC pulse is activated, the control signal ATDL of the latching circuit 10 does not depend on the signal ATD being an address transfer signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an OE mode.

[0002]

2. Description of the Related Art A static random access memory (hereinafter referred to as SRAM) which is a conventional semiconductor memory device.
Is schematically shown in FIG. FIG. 3 shows an input circuit 1 for inputting an address signal, a row decoder 2 for inputting an output signal of the input circuit 1 to select a memory cell row, and a memory cell in a predetermined column from the selected memory cell row. A column decoder 3, an address transition detection (ATD) circuit 7 that detects a change in the address signal and generates a pulse, a sense amplifier 9 that amplifies data read from a memory cell, and a sense amplifier output is latched. Latch circuit 10
And an output driver circuit 11 for outputting data to an external terminal
It is composed of The control signal of the conventional SRAM is generated by the control signal generating circuit 8, and the control signal generating circuit 8 outputs the output pulse signal of the ATD circuit 7 and the write enable signal XWE (X means negative logic, active L). ,
This is a circuit for logically synthesizing the chip select signal CSB and the output enable signal XOE.

Generally, as a method of reading SRAM,
An address access mode (address mode is abbreviated) that outputs memory cell information to the outside in response to a change in the address signal, and an OE that fixes the address signal and changes the output enable signal to output the memory cell information to the outside. The access mode (abbreviated as OE mode) is raised. In addition, as a method for performing high-speed reading, an output that shortens the output transition period by detecting the address change in the address mode and shifting the output potential to the intermediate potential until the data in the memory cell is transmitted to the output driver circuit. The preset method can be increased. In FIG. 3, the output preset circuit 12 is controlled by the control signal PRE output from the control signal generation circuit 8.

FIG. 4 shows signal waveforms of a conventional semiconductor memory device. FIG. 4A shows each signal waveform in the address mode. The chip select signal C
SB is "High", XWE is "High", XOE
Is fixed to "Low". With the change of the address signal Add, the ATD circuit outputs the ATD pulse signal.
The potential of the data of the memory cell selected by the address signal is amplified by the sense amplifier activated by the control signal SAC, and the amplified data of the memory cell is input to the latch circuit controlled by the control signal ATDL. The latch circuit is controlled so that when the sense amplifier is activated and the output potential is determined, the input part of the latch circuit is connected to the output of the sense amplifier, and is disconnected after a predetermined time. In addition, PR which is an activation signal of the output preset circuit
E is created by receiving the ATD pulse signal and has an intermediate potential due to the output preset circuit during operation of the output driver circuit, so that data can be output at high speed.

FIG. 4B shows each signal waveform in the OE mode. CSB is "High" and XWE is "."
It is fixed to "High" and XOE is variable.
In this mode, although the read data is stored in the input portion of the output driver circuit, the output potential I is output because the output driver control signal OEA is "Low".
/ O is in a high impedance state. Next, the output driver control signal 0EA becomes "High",
Data is output to the external terminal.

[0006]

Since the address is fixed in the OE mode, the output preset circuit does not operate. For this reason, in the OE mode, since the potential change of the output potential is large, noise is likely to occur, and this influence causes the input potential to change. The fluctuation of the input potential generated here causes the ATD circuit to operate, the control signal ATDL of the latch circuit is generated, and erroneous data is input to the latch circuit. As a result, there is a possibility that erroneous data may be output to the output potential I / O. For this reason, the transistor capability of the output driver circuit must be reduced, and as a result, the access time, especially the access in the OE mode, is delayed.

[0007]

In order to solve the above problems, the semiconductor memory device of the present invention prevents the ATD signal from affecting the output latch circuit in the OE mode. Specifically, the change in XOE is detected, and the input gate of the output latch is controlled by either the result or ATD. It is also characterized in that XOE to the output driver is delayed.

[0008]

FIG. 1 shows an embodiment of the present invention. The description of the same parts as in FIG. 3 will be omitted. 1 includes an input circuit 14 for the output enable signal XOE, a rising edge detection circuit 15, a pulse width setting circuit 16, a delay circuit 18, and a control signal generation circuit 8. The output of the XOE input circuit 14 is connected to an output enable signal (OE) control circuit composed of the rising edge detection circuit 15 and the pulse width setting circuit 16 which are connected in series. The output signal OEC of the OE control circuit is connected to the latch control signal generation circuit 8. The signal OEB output from the OE input circuit 14 via the delay circuit 18 becomes a control signal for the output driver circuit 12. The rising edge detection circuit 15 is a circuit that receives the output of the OE input circuit 14 and generates a pulse when changing from a non-reading time to a reading time, that is, when XOE changes from “High” to “Low”. The rising edge detection circuit 15 may use a differentiating circuit. The output of the rising edge detection circuit 15 is connected to the pulse width setting circuit 16. The pulse width setting circuit 16 is a circuit that sets the input rising pulse signal to the width of the period in which the output potential is fixed.

Next, an AT which is a control signal for the latch circuit 10
The circuit structure which synthesize | combines DL is shown. The ATDL created in the control signal generation circuit 8 includes a NOR circuit to which the output of the pulse width setting circuit 16 and an inverted signal of the ATD signal are input, an output of the NOR circuit, a write enable signal XWE, and a chip select signal CSB. It is composed of connected NAND circuits. Further, the control signal of the output driver circuit, OEB, delays XOE by the delay circuit 18 so that the ATDL is activated and the data in the latch is not affected.

The latch circuit 10 has a clocked inverter 31 to which the output of the sense amplifier 9 is input, an inverter 32 to which the output of the clocked inverter is connected, and a clocked inverter 3 which is connected to the output of the inverter 32.
3 The output of the clocked inverter 33 is connected to the input node of the inverter 32 and has a latch configuration. The output of the latch circuit 10 is the output of the inverter 32. One of the clocked inverter 33 and the clocked inverter 31 is configured to operate according to the control signal ATDL and its inverted signal. ATDL
Outputs a pulse corresponding to the ATD signal when OEC is "Low", and the ATDL signal is fixed to "Low" when OEC is "High". Therefore, while the OEC pulse is active, the control signal ATDL of the latch circuit does not depend on the ATD signal which is the address transition signal.

FIG. 2 shows the signal waveforms of the present invention, showing the case of OE mode operation. By activating the OE signal when the address signal is fixed, a read signal pulse OEC is generated from the OE signal control circuit, and the control signal ATDL for the latch circuit is generated. At the rise of ATDL, the latch circuit is disconnected from the output of the sense amplifier and activates the latch operation. At this time, the signal OEB delayed until the activation timing of ATDL is activated, and the output driver circuit operates. As a result, the address input potential fluctuates and an ATD pulse signal is generated, but ATDL is OE.
Since the C pulse signal does not depend on the ATD pulse signal while being activated, the latch circuit is separated from the output of the sense amplifier and maintains the latched state. Therefore, the output potential will not be inverted due to noise during the period until the OEC pulse signal is output and the output potential is determined.

[0012]

As described above, according to the semiconductor memory device of the present invention, in the structure having the latch circuit for latching the data of the memory cell, the semiconductor memory device is affected by the noise generated when the large output potential changes in the OE mode. Since it does not exist, malfunction can be prevented. Since it is not affected by noise, the transistor capability of the output driver circuit can be increased and the speed can be easily increased in the OE mode.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is each output waveform of the present invention.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is each output waveform of a conventional example.

[Explanation of symbols]

1. Address signal input circuit, 2. Row decoder, 3.
Column decoder, 4. Bit line load circuit, 5. Memory cell, 6. Column gate, 7. ATD circuit, 8. Control signal generating circuit, 9. Sense amplifier, 10. Latch circuit, 1
1. Output driver circuit, 12. Output preset circuit, 1
4. XOE input circuit, 15. Rising edge detection circuit, 1
6. Pulse width setting circuit, 18. Delay circuit, 31/33.
Clocked inverter, 32.34. Inverter

Claims (4)

[Claims] 1. An address transition detection circuit for detecting a change in an address signal to generate a pulse signal, a latch circuit for latching data read from a memory cell selected by the address signal, and an output enable signal. Activation of the output enable signal in a semiconductor memory device having an output driver circuit controlled by a circuit for outputting the output of the latch circuit to an external terminal and a latch control signal generation circuit for generating a control signal for controlling the latch circuit. Rising edge detection circuit for detecting a pulse signal and a pulse width setting circuit and the output pulse of the address transition detection circuit are logically synthesized, and the signal based on the output of the rising edge detection circuit is activated, the latch Semiconductor memory device characterized by deactivating an input gate of a circuit 2. The semiconductor memory device according to claim 1, further comprising a delay circuit that delays the input output enable signal and supplies the delayed output enable signal to the output driver circuit. 3. The semiconductor device according to claim 2, further comprising a pulse width setting circuit that changes an output pulse width of the rising edge detection circuit. 4. An output preset circuit for shifting the potential of the external terminal to an intermediate potential based on an output pulse signal of the address transition detection circuit.
4. The semiconductor memory device according to any one of claims 1 to 3.